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Searched refs:MC_CGM_MUX_CSC_CG_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Selector.c259 …Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= (MC_CGM_MUX_CSC_CG_MASK | MC_CGM_MUX_CSC_FCG_MASK… in Clock_Ip_ResetCgmXCscCssCsGrip()
277 …ock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~(MC_CGM_MUX_CSC_FCG_MASK | MC_CGM_MUX_CSC_CG_MASK); in Clock_Ip_ResetCgmXCscCssCsGrip()
296 …Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= (MC_CGM_MUX_CSC_CG_MASK | MC_CGM_MUX_CSC_FCG_MASK… in Clock_Ip_SetCgmXCscCssCsGrip()
314 …ock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~(MC_CGM_MUX_CSC_FCG_MASK | MC_CGM_MUX_CSC_CG_MASK); in Clock_Ip_SetCgmXCscCssCsGrip()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Selector.c436 …Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= (MC_CGM_MUX_CSC_CG_MASK | MC_CGM_MUX_CSC_FCG_MASK… in Clock_Ip_ResetCgmXCscCssCsGrip()
454 …ock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~(MC_CGM_MUX_CSC_FCG_MASK | MC_CGM_MUX_CSC_CG_MASK); in Clock_Ip_ResetCgmXCscCssCsGrip()
501 …Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= (MC_CGM_MUX_CSC_CG_MASK | MC_CGM_MUX_CSC_FCG_MASK… in Clock_Ip_SetCgmXCscCssCsGrip()
519 …ock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~(MC_CGM_MUX_CSC_FCG_MASK | MC_CGM_MUX_CSC_CG_MASK); in Clock_Ip_SetCgmXCscCssCsGrip()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Specific.h177 #define MC_CGM_MUX_CSC_CG_MASK MC_CGM_MUX_4_CSC_CG_MASK macro
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
DClock_Ip_Specific.h333 #define MC_CGM_MUX_CSC_CG_MASK MC_CGM_MUX_5_CSC_CG_MASK macro