MC_CGM_MUX_2_CSC_SELCTL_MASK (reference) in projects: hal_nxp-3.5.0

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Searched refs:MC_CGM_MUX_2_CSC_SELCTL_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Data.c	3368 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_3_DIV_MASK, … 3369 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_3_DIV_MASK, … 3381 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, … 3391 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_1_DIV_MASK, … 3392 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_2_DIV_MASK, … 3393 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_5_DIV_MASK, … 3394 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, … 3399 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_4_DIV_MASK, … 3427 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, … 3429 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_1_DIV_MASK, … [all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
D	S32K344_MC_CGM.h	`494 #define MC_CGM_MUX_2_CSC_SELCTL_MASK (0x1F000000U) macro 497 … (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_2_CSC_SELCTL_MASK)`
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
D	S32Z2_MC_CGM.h	`540 #define MC_CGM_MUX_2_CSC_SELCTL_MASK (0x3F000000U) /* Merged from fields with differen… macro 543 …int32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_2_CSC_SELCTL_MASK) /* Me…`
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_Data.c	`3695 …{MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_…`

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