1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_MC_CGM.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_MC_CGM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_MC_CGM_H_) /* Check if memory map has not been already included */ 58 #define S32K344_MC_CGM_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MC_CGM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MC_CGM_Peripheral_Access_Layer MC_CGM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MC_CGM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PCFS_SDUR; /**< PCFS Step Duration, offset: 0x0 */ 74 uint8_t RESERVED_0[84]; 75 __IO uint32_t PCFS_DIVC8; /**< PCFS Divider Change 8 Register, offset: 0x58 */ 76 __IO uint32_t PCFS_DIVE8; /**< PCFS Divider End 8 Register, offset: 0x5C */ 77 __IO uint32_t PCFS_DIVS8; /**< PCFS Divider Start 8 Register, offset: 0x60 */ 78 uint8_t RESERVED_1[668]; 79 __IO uint32_t MUX_0_CSC; /**< Clock Mux 0 Select Control Register, offset: 0x300 */ 80 __I uint32_t MUX_0_CSS; /**< Clock Mux 0 Select Status Register, offset: 0x304 */ 81 __IO uint32_t MUX_0_DC_0; /**< Clock Mux 0 Divider 0 Control Register, offset: 0x308 */ 82 __IO uint32_t MUX_0_DC_1; /**< Clock Mux 0 Divider 1 Control Register, offset: 0x30C */ 83 __IO uint32_t MUX_0_DC_2; /**< Clock Mux 0 Divider 2 Control Register, offset: 0x310 */ 84 __IO uint32_t MUX_0_DC_3; /**< Clock Mux 0 Divider 3 Control Register, offset: 0x314 */ 85 __IO uint32_t MUX_0_DC_4; /**< Clock Mux 0 Divider 4 Control Register, offset: 0x318 */ 86 __IO uint32_t MUX_0_DC_5; /**< Clock Mux 0 Divider 5 Control Register, offset: 0x31C */ 87 __IO uint32_t MUX_0_DC_6; /**< Clock Mux 0 Divider 6 Control Register, offset: 0x320 */ 88 uint8_t RESERVED_2[16]; 89 __IO uint32_t MUX_0_DIV_TRIG_CTRL; /**< Clock Mux 0 Divider Trigger Control Register, offset: 0x334 */ 90 __O uint32_t MUX_0_DIV_TRIG; /**< Clock Mux 0 Divider Trigger Register, offset: 0x338 */ 91 __I uint32_t MUX_0_DIV_UPD_STAT; /**< Clock Mux 0 Divider Update Status Register, offset: 0x33C */ 92 __IO uint32_t MUX_1_CSC; /**< Clock Mux 1 Select Control Register, offset: 0x340 */ 93 __I uint32_t MUX_1_CSS; /**< Clock Mux 1 Select Status Register, offset: 0x344 */ 94 __IO uint32_t MUX_1_DC_0; /**< Clock Mux 1 Divider 0 Control Register, offset: 0x348 */ 95 uint8_t RESERVED_3[48]; 96 __I uint32_t MUX_1_DIV_UPD_STAT; /**< Clock Mux 1 Divider Update Status Register, offset: 0x37C */ 97 __IO uint32_t MUX_2_CSC; /**< Clock Mux 2 Select Control Register, offset: 0x380 */ 98 __I uint32_t MUX_2_CSS; /**< Clock Mux 2 Select Status Register, offset: 0x384 */ 99 __IO uint32_t MUX_2_DC_0; /**< Clock Mux 2 Divider 0 Control Register, offset: 0x388 */ 100 uint8_t RESERVED_4[48]; 101 __I uint32_t MUX_2_DIV_UPD_STAT; /**< Clock Mux 2 Divider Update Status Register, offset: 0x3BC */ 102 __IO uint32_t MUX_3_CSC; /**< Clock Mux 3 Select Control Register, offset: 0x3C0 */ 103 __I uint32_t MUX_3_CSS; /**< Clock Mux 3 Select Status Register, offset: 0x3C4 */ 104 __IO uint32_t MUX_3_DC_0; /**< Clock Mux 3 Divider 0 Control Register, offset: 0x3C8 */ 105 uint8_t RESERVED_5[48]; 106 __I uint32_t MUX_3_DIV_UPD_STAT; /**< Clock Mux 3 Divider Update Status Register, offset: 0x3FC */ 107 __IO uint32_t MUX_4_CSC; /**< Clock Mux 4 Select Control Register, offset: 0x400 */ 108 __I uint32_t MUX_4_CSS; /**< Clock Mux 4 Select Status Register, offset: 0x404 */ 109 __IO uint32_t MUX_4_DC_0; /**< Clock Mux 4 Divider 0 Control Register, offset: 0x408 */ 110 uint8_t RESERVED_6[48]; 111 __I uint32_t MUX_4_DIV_UPD_STAT; /**< Clock Mux 4 Divider Update Status Register, offset: 0x43C */ 112 __IO uint32_t MUX_5_CSC; /**< Clock Mux 5 Select Control Register, offset: 0x440 */ 113 __I uint32_t MUX_5_CSS; /**< Clock Mux 5 Select Status Register, offset: 0x444 */ 114 __IO uint32_t MUX_5_DC_0; /**< Clock Mux 5 Divider 0 Control Register, offset: 0x448 */ 115 uint8_t RESERVED_7[48]; 116 __I uint32_t MUX_5_DIV_UPD_STAT; /**< Clock Mux 5 Divider Update Status Register, offset: 0x47C */ 117 __IO uint32_t MUX_6_CSC; /**< Clock Mux 6 Select Control Register, offset: 0x480 */ 118 __I uint32_t MUX_6_CSS; /**< Clock Mux 6 Select Status Register, offset: 0x484 */ 119 __IO uint32_t MUX_6_DC_0; /**< Clock Mux 6 Divider 0 Control Register, offset: 0x488 */ 120 uint8_t RESERVED_8[48]; 121 __I uint32_t MUX_6_DIV_UPD_STAT; /**< Clock Mux 6 Divider Update Status Register, offset: 0x4BC */ 122 __IO uint32_t MUX_7_CSC; /**< Clock Mux 7 Select Control Register, offset: 0x4C0 */ 123 __I uint32_t MUX_7_CSS; /**< Clock Mux 7 Select Status Register, offset: 0x4C4 */ 124 __IO uint32_t MUX_7_DC_0; /**< Clock Mux 7 Divider 0 Control Register, offset: 0x4C8 */ 125 uint8_t RESERVED_9[48]; 126 __I uint32_t MUX_7_DIV_UPD_STAT; /**< Clock Mux 7 Divider Update Status Register, offset: 0x4FC */ 127 __IO uint32_t MUX_8_CSC; /**< Clock Mux 8 Select Control Register, offset: 0x500 */ 128 __I uint32_t MUX_8_CSS; /**< Clock Mux 8 Select Status Register, offset: 0x504 */ 129 __IO uint32_t MUX_8_DC_0; /**< Clock Mux 8 Divider 0 Control Register, offset: 0x508 */ 130 uint8_t RESERVED_10[48]; 131 __I uint32_t MUX_8_DIV_UPD_STAT; /**< Clock Mux 8 Divider Update Status Register, offset: 0x53C */ 132 __IO uint32_t MUX_9_CSC; /**< Clock Mux 9 Select Control Register, offset: 0x540 */ 133 __I uint32_t MUX_9_CSS; /**< Clock Mux 9 Select Status Register, offset: 0x544 */ 134 __IO uint32_t MUX_9_DC_0; /**< Clock Mux 9 Divider 0 Control Register, offset: 0x548 */ 135 uint8_t RESERVED_11[48]; 136 __I uint32_t MUX_9_DIV_UPD_STAT; /**< Clock Mux 9 Divider Update Status Register, offset: 0x57C */ 137 __IO uint32_t MUX_10_CSC; /**< Clock Mux 10 Select Control Register, offset: 0x580 */ 138 __I uint32_t MUX_10_CSS; /**< Clock Mux 10 Select Status Register, offset: 0x584 */ 139 __IO uint32_t MUX_10_DC_0; /**< Clock Mux 10 Divider 0 Control Register, offset: 0x588 */ 140 uint8_t RESERVED_12[48]; 141 __I uint32_t MUX_10_DIV_UPD_STAT; /**< Clock Mux 10 Divider Update Status Register, offset: 0x5BC */ 142 __IO uint32_t MUX_11_CSC; /**< Clock Mux 11 Select Control Register, offset: 0x5C0 */ 143 __I uint32_t MUX_11_CSS; /**< Clock Mux 11 Select Status Register, offset: 0x5C4 */ 144 __IO uint32_t MUX_11_DC_0; /**< Clock Mux 11 Divider 0 Control Register, offset: 0x5C8 */ 145 uint8_t RESERVED_13[48]; 146 __I uint32_t MUX_11_DIV_UPD_STAT; /**< Clock Mux 11 Divider Update Status Register, offset: 0x5FC */ 147 } MC_CGM_Type, *MC_CGM_MemMapPtr; 148 149 /** Number of instances of the MC_CGM module. */ 150 #define MC_CGM_INSTANCE_COUNT (1u) 151 152 /* MC_CGM - Peripheral instance base addresses */ 153 /** Peripheral MC_CGM base address */ 154 #define IP_MC_CGM_BASE (0x402D8000u) 155 /** Peripheral MC_CGM base pointer */ 156 #define IP_MC_CGM ((MC_CGM_Type *)IP_MC_CGM_BASE) 157 /** Array initializer of MC_CGM peripheral base addresses */ 158 #define IP_MC_CGM_BASE_ADDRS { IP_MC_CGM_BASE } 159 /** Array initializer of MC_CGM peripheral base pointers */ 160 #define IP_MC_CGM_BASE_PTRS { IP_MC_CGM } 161 162 /* ---------------------------------------------------------------------------- 163 -- MC_CGM Register Masks 164 ---------------------------------------------------------------------------- */ 165 166 /*! 167 * @addtogroup MC_CGM_Register_Masks MC_CGM Register Masks 168 * @{ 169 */ 170 171 /*! @name PCFS_SDUR - PCFS Step Duration */ 172 /*! @{ */ 173 174 #define MC_CGM_PCFS_SDUR_SDUR_MASK (0xFFFFU) 175 #define MC_CGM_PCFS_SDUR_SDUR_SHIFT (0U) 176 #define MC_CGM_PCFS_SDUR_SDUR_WIDTH (16U) 177 #define MC_CGM_PCFS_SDUR_SDUR(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_SDUR_SDUR_SHIFT)) & MC_CGM_PCFS_SDUR_SDUR_MASK) 178 /*! @} */ 179 180 /*! @name PCFS_DIVC8 - PCFS Divider Change 8 Register */ 181 /*! @{ */ 182 183 #define MC_CGM_PCFS_DIVC8_RATE_MASK (0xFFU) 184 #define MC_CGM_PCFS_DIVC8_RATE_SHIFT (0U) 185 #define MC_CGM_PCFS_DIVC8_RATE_WIDTH (8U) 186 #define MC_CGM_PCFS_DIVC8_RATE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVC8_RATE_SHIFT)) & MC_CGM_PCFS_DIVC8_RATE_MASK) 187 188 #define MC_CGM_PCFS_DIVC8_INIT_MASK (0xFFFF0000U) 189 #define MC_CGM_PCFS_DIVC8_INIT_SHIFT (16U) 190 #define MC_CGM_PCFS_DIVC8_INIT_WIDTH (16U) 191 #define MC_CGM_PCFS_DIVC8_INIT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVC8_INIT_SHIFT)) & MC_CGM_PCFS_DIVC8_INIT_MASK) 192 /*! @} */ 193 194 /*! @name PCFS_DIVE8 - PCFS Divider End 8 Register */ 195 /*! @{ */ 196 197 #define MC_CGM_PCFS_DIVE8_DIVE_MASK (0xFFFFFU) 198 #define MC_CGM_PCFS_DIVE8_DIVE_SHIFT (0U) 199 #define MC_CGM_PCFS_DIVE8_DIVE_WIDTH (20U) 200 #define MC_CGM_PCFS_DIVE8_DIVE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVE8_DIVE_SHIFT)) & MC_CGM_PCFS_DIVE8_DIVE_MASK) 201 /*! @} */ 202 203 /*! @name PCFS_DIVS8 - PCFS Divider Start 8 Register */ 204 /*! @{ */ 205 206 #define MC_CGM_PCFS_DIVS8_DIVS_MASK (0xFFFFFU) 207 #define MC_CGM_PCFS_DIVS8_DIVS_SHIFT (0U) 208 #define MC_CGM_PCFS_DIVS8_DIVS_WIDTH (20U) 209 #define MC_CGM_PCFS_DIVS8_DIVS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_PCFS_DIVS8_DIVS_SHIFT)) & MC_CGM_PCFS_DIVS8_DIVS_MASK) 210 /*! @} */ 211 212 /*! @name MUX_0_CSC - Clock Mux 0 Select Control Register */ 213 /*! @{ */ 214 215 #define MC_CGM_MUX_0_CSC_RAMPUP_MASK (0x1U) 216 #define MC_CGM_MUX_0_CSC_RAMPUP_SHIFT (0U) 217 #define MC_CGM_MUX_0_CSC_RAMPUP_WIDTH (1U) 218 #define MC_CGM_MUX_0_CSC_RAMPUP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_RAMPUP_SHIFT)) & MC_CGM_MUX_0_CSC_RAMPUP_MASK) 219 220 #define MC_CGM_MUX_0_CSC_RAMPDOWN_MASK (0x2U) 221 #define MC_CGM_MUX_0_CSC_RAMPDOWN_SHIFT (1U) 222 #define MC_CGM_MUX_0_CSC_RAMPDOWN_WIDTH (1U) 223 #define MC_CGM_MUX_0_CSC_RAMPDOWN(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_RAMPDOWN_SHIFT)) & MC_CGM_MUX_0_CSC_RAMPDOWN_MASK) 224 225 #define MC_CGM_MUX_0_CSC_CLK_SW_MASK (0x4U) 226 #define MC_CGM_MUX_0_CSC_CLK_SW_SHIFT (2U) 227 #define MC_CGM_MUX_0_CSC_CLK_SW_WIDTH (1U) 228 #define MC_CGM_MUX_0_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_0_CSC_CLK_SW_MASK) 229 230 #define MC_CGM_MUX_0_CSC_SAFE_SW_MASK (0x8U) 231 #define MC_CGM_MUX_0_CSC_SAFE_SW_SHIFT (3U) 232 #define MC_CGM_MUX_0_CSC_SAFE_SW_WIDTH (1U) 233 #define MC_CGM_MUX_0_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_0_CSC_SAFE_SW_MASK) 234 235 #define MC_CGM_MUX_0_CSC_SELCTL_MASK (0xF000000U) 236 #define MC_CGM_MUX_0_CSC_SELCTL_SHIFT (24U) 237 #define MC_CGM_MUX_0_CSC_SELCTL_WIDTH (4U) 238 #define MC_CGM_MUX_0_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_0_CSC_SELCTL_MASK) 239 /*! @} */ 240 241 /*! @name MUX_0_CSS - Clock Mux 0 Select Status Register */ 242 /*! @{ */ 243 244 #define MC_CGM_MUX_0_CSS_RAMPUP_MASK (0x1U) 245 #define MC_CGM_MUX_0_CSS_RAMPUP_SHIFT (0U) 246 #define MC_CGM_MUX_0_CSS_RAMPUP_WIDTH (1U) 247 #define MC_CGM_MUX_0_CSS_RAMPUP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_RAMPUP_SHIFT)) & MC_CGM_MUX_0_CSS_RAMPUP_MASK) 248 249 #define MC_CGM_MUX_0_CSS_RAMPDOWN_MASK (0x2U) 250 #define MC_CGM_MUX_0_CSS_RAMPDOWN_SHIFT (1U) 251 #define MC_CGM_MUX_0_CSS_RAMPDOWN_WIDTH (1U) 252 #define MC_CGM_MUX_0_CSS_RAMPDOWN(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_RAMPDOWN_SHIFT)) & MC_CGM_MUX_0_CSS_RAMPDOWN_MASK) 253 254 #define MC_CGM_MUX_0_CSS_CLK_SW_MASK (0x4U) 255 #define MC_CGM_MUX_0_CSS_CLK_SW_SHIFT (2U) 256 #define MC_CGM_MUX_0_CSS_CLK_SW_WIDTH (1U) 257 #define MC_CGM_MUX_0_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_0_CSS_CLK_SW_MASK) 258 259 #define MC_CGM_MUX_0_CSS_SAFE_SW_MASK (0x8U) 260 #define MC_CGM_MUX_0_CSS_SAFE_SW_SHIFT (3U) 261 #define MC_CGM_MUX_0_CSS_SAFE_SW_WIDTH (1U) 262 #define MC_CGM_MUX_0_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_0_CSS_SAFE_SW_MASK) 263 264 #define MC_CGM_MUX_0_CSS_SWIP_MASK (0x10000U) 265 #define MC_CGM_MUX_0_CSS_SWIP_SHIFT (16U) 266 #define MC_CGM_MUX_0_CSS_SWIP_WIDTH (1U) 267 #define MC_CGM_MUX_0_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SWIP_SHIFT)) & MC_CGM_MUX_0_CSS_SWIP_MASK) 268 269 #define MC_CGM_MUX_0_CSS_SWTRG_MASK (0xE0000U) 270 #define MC_CGM_MUX_0_CSS_SWTRG_SHIFT (17U) 271 #define MC_CGM_MUX_0_CSS_SWTRG_WIDTH (3U) 272 #define MC_CGM_MUX_0_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_0_CSS_SWTRG_MASK) 273 274 #define MC_CGM_MUX_0_CSS_SELSTAT_MASK (0xF000000U) 275 #define MC_CGM_MUX_0_CSS_SELSTAT_SHIFT (24U) 276 #define MC_CGM_MUX_0_CSS_SELSTAT_WIDTH (4U) 277 #define MC_CGM_MUX_0_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_0_CSS_SELSTAT_MASK) 278 /*! @} */ 279 280 /*! @name MUX_0_DC_0 - Clock Mux 0 Divider 0 Control Register */ 281 /*! @{ */ 282 283 #define MC_CGM_MUX_0_DC_0_DIV_MASK (0x70000U) 284 #define MC_CGM_MUX_0_DC_0_DIV_SHIFT (16U) 285 #define MC_CGM_MUX_0_DC_0_DIV_WIDTH (3U) 286 #define MC_CGM_MUX_0_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_0_DIV_SHIFT)) & MC_CGM_MUX_0_DC_0_DIV_MASK) 287 288 #define MC_CGM_MUX_0_DC_0_DE_MASK (0x80000000U) 289 #define MC_CGM_MUX_0_DC_0_DE_SHIFT (31U) 290 #define MC_CGM_MUX_0_DC_0_DE_WIDTH (1U) 291 #define MC_CGM_MUX_0_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_0_DE_SHIFT)) & MC_CGM_MUX_0_DC_0_DE_MASK) 292 /*! @} */ 293 294 /*! @name MUX_0_DC_1 - Clock Mux 0 Divider 1 Control Register */ 295 /*! @{ */ 296 297 #define MC_CGM_MUX_0_DC_1_DIV_MASK (0x70000U) 298 #define MC_CGM_MUX_0_DC_1_DIV_SHIFT (16U) 299 #define MC_CGM_MUX_0_DC_1_DIV_WIDTH (3U) 300 #define MC_CGM_MUX_0_DC_1_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_1_DIV_SHIFT)) & MC_CGM_MUX_0_DC_1_DIV_MASK) 301 302 #define MC_CGM_MUX_0_DC_1_DE_MASK (0x80000000U) 303 #define MC_CGM_MUX_0_DC_1_DE_SHIFT (31U) 304 #define MC_CGM_MUX_0_DC_1_DE_WIDTH (1U) 305 #define MC_CGM_MUX_0_DC_1_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_1_DE_SHIFT)) & MC_CGM_MUX_0_DC_1_DE_MASK) 306 /*! @} */ 307 308 /*! @name MUX_0_DC_2 - Clock Mux 0 Divider 2 Control Register */ 309 /*! @{ */ 310 311 #define MC_CGM_MUX_0_DC_2_DIV_MASK (0xF0000U) 312 #define MC_CGM_MUX_0_DC_2_DIV_SHIFT (16U) 313 #define MC_CGM_MUX_0_DC_2_DIV_WIDTH (4U) 314 #define MC_CGM_MUX_0_DC_2_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_2_DIV_SHIFT)) & MC_CGM_MUX_0_DC_2_DIV_MASK) 315 316 #define MC_CGM_MUX_0_DC_2_DE_MASK (0x80000000U) 317 #define MC_CGM_MUX_0_DC_2_DE_SHIFT (31U) 318 #define MC_CGM_MUX_0_DC_2_DE_WIDTH (1U) 319 #define MC_CGM_MUX_0_DC_2_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_2_DE_SHIFT)) & MC_CGM_MUX_0_DC_2_DE_MASK) 320 /*! @} */ 321 322 /*! @name MUX_0_DC_3 - Clock Mux 0 Divider 3 Control Register */ 323 /*! @{ */ 324 325 #define MC_CGM_MUX_0_DC_3_DIV_MASK (0x70000U) 326 #define MC_CGM_MUX_0_DC_3_DIV_SHIFT (16U) 327 #define MC_CGM_MUX_0_DC_3_DIV_WIDTH (3U) 328 #define MC_CGM_MUX_0_DC_3_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_3_DIV_SHIFT)) & MC_CGM_MUX_0_DC_3_DIV_MASK) 329 330 #define MC_CGM_MUX_0_DC_3_DE_MASK (0x80000000U) 331 #define MC_CGM_MUX_0_DC_3_DE_SHIFT (31U) 332 #define MC_CGM_MUX_0_DC_3_DE_WIDTH (1U) 333 #define MC_CGM_MUX_0_DC_3_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_3_DE_SHIFT)) & MC_CGM_MUX_0_DC_3_DE_MASK) 334 /*! @} */ 335 336 /*! @name MUX_0_DC_4 - Clock Mux 0 Divider 4 Control Register */ 337 /*! @{ */ 338 339 #define MC_CGM_MUX_0_DC_4_DIV_MASK (0x70000U) 340 #define MC_CGM_MUX_0_DC_4_DIV_SHIFT (16U) 341 #define MC_CGM_MUX_0_DC_4_DIV_WIDTH (3U) 342 #define MC_CGM_MUX_0_DC_4_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_4_DIV_SHIFT)) & MC_CGM_MUX_0_DC_4_DIV_MASK) 343 344 #define MC_CGM_MUX_0_DC_4_DE_MASK (0x80000000U) 345 #define MC_CGM_MUX_0_DC_4_DE_SHIFT (31U) 346 #define MC_CGM_MUX_0_DC_4_DE_WIDTH (1U) 347 #define MC_CGM_MUX_0_DC_4_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_4_DE_SHIFT)) & MC_CGM_MUX_0_DC_4_DE_MASK) 348 /*! @} */ 349 350 /*! @name MUX_0_DC_5 - Clock Mux 0 Divider 5 Control Register */ 351 /*! @{ */ 352 353 #define MC_CGM_MUX_0_DC_5_DIV_MASK (0x70000U) 354 #define MC_CGM_MUX_0_DC_5_DIV_SHIFT (16U) 355 #define MC_CGM_MUX_0_DC_5_DIV_WIDTH (3U) 356 #define MC_CGM_MUX_0_DC_5_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_5_DIV_SHIFT)) & MC_CGM_MUX_0_DC_5_DIV_MASK) 357 358 #define MC_CGM_MUX_0_DC_5_DE_MASK (0x80000000U) 359 #define MC_CGM_MUX_0_DC_5_DE_SHIFT (31U) 360 #define MC_CGM_MUX_0_DC_5_DE_WIDTH (1U) 361 #define MC_CGM_MUX_0_DC_5_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_5_DE_SHIFT)) & MC_CGM_MUX_0_DC_5_DE_MASK) 362 /*! @} */ 363 364 /*! @name MUX_0_DC_6 - Clock Mux 0 Divider 6 Control Register */ 365 /*! @{ */ 366 367 #define MC_CGM_MUX_0_DC_6_DIV_MASK (0x70000U) 368 #define MC_CGM_MUX_0_DC_6_DIV_SHIFT (16U) 369 #define MC_CGM_MUX_0_DC_6_DIV_WIDTH (3U) 370 #define MC_CGM_MUX_0_DC_6_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_6_DIV_SHIFT)) & MC_CGM_MUX_0_DC_6_DIV_MASK) 371 372 #define MC_CGM_MUX_0_DC_6_DE_MASK (0x80000000U) 373 #define MC_CGM_MUX_0_DC_6_DE_SHIFT (31U) 374 #define MC_CGM_MUX_0_DC_6_DE_WIDTH (1U) 375 #define MC_CGM_MUX_0_DC_6_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DC_6_DE_SHIFT)) & MC_CGM_MUX_0_DC_6_DE_MASK) 376 /*! @} */ 377 378 /*! @name MUX_0_DIV_TRIG_CTRL - Clock Mux 0 Divider Trigger Control Register */ 379 /*! @{ */ 380 381 #define MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL_MASK (0x1U) 382 #define MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL_SHIFT (0U) 383 #define MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL_WIDTH (1U) 384 #define MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL_SHIFT)) & MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL_MASK) 385 386 #define MC_CGM_MUX_0_DIV_TRIG_CTRL_HHEN_MASK (0x80000000U) 387 #define MC_CGM_MUX_0_DIV_TRIG_CTRL_HHEN_SHIFT (31U) 388 #define MC_CGM_MUX_0_DIV_TRIG_CTRL_HHEN_WIDTH (1U) 389 #define MC_CGM_MUX_0_DIV_TRIG_CTRL_HHEN(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DIV_TRIG_CTRL_HHEN_SHIFT)) & MC_CGM_MUX_0_DIV_TRIG_CTRL_HHEN_MASK) 390 /*! @} */ 391 392 /*! @name MUX_0_DIV_TRIG - Clock Mux 0 Divider Trigger Register */ 393 /*! @{ */ 394 395 #define MC_CGM_MUX_0_DIV_TRIG_TRIGGER_MASK (0xFFFFFFFFU) 396 #define MC_CGM_MUX_0_DIV_TRIG_TRIGGER_SHIFT (0U) 397 #define MC_CGM_MUX_0_DIV_TRIG_TRIGGER_WIDTH (32U) 398 #define MC_CGM_MUX_0_DIV_TRIG_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DIV_TRIG_TRIGGER_SHIFT)) & MC_CGM_MUX_0_DIV_TRIG_TRIGGER_MASK) 399 /*! @} */ 400 401 /*! @name MUX_0_DIV_UPD_STAT - Clock Mux 0 Divider Update Status Register */ 402 /*! @{ */ 403 404 #define MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 405 #define MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 406 #define MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 407 #define MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_MASK) 408 /*! @} */ 409 410 /*! @name MUX_1_CSC - Clock Mux 1 Select Control Register */ 411 /*! @{ */ 412 413 #define MC_CGM_MUX_1_CSC_CLK_SW_MASK (0x4U) 414 #define MC_CGM_MUX_1_CSC_CLK_SW_SHIFT (2U) 415 #define MC_CGM_MUX_1_CSC_CLK_SW_WIDTH (1U) 416 #define MC_CGM_MUX_1_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_1_CSC_CLK_SW_MASK) 417 418 #define MC_CGM_MUX_1_CSC_SAFE_SW_MASK (0x8U) 419 #define MC_CGM_MUX_1_CSC_SAFE_SW_SHIFT (3U) 420 #define MC_CGM_MUX_1_CSC_SAFE_SW_WIDTH (1U) 421 #define MC_CGM_MUX_1_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_1_CSC_SAFE_SW_MASK) 422 423 #define MC_CGM_MUX_1_CSC_SELCTL_MASK (0x1F000000U) 424 #define MC_CGM_MUX_1_CSC_SELCTL_SHIFT (24U) 425 #define MC_CGM_MUX_1_CSC_SELCTL_WIDTH (5U) 426 #define MC_CGM_MUX_1_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_1_CSC_SELCTL_MASK) 427 /*! @} */ 428 429 /*! @name MUX_1_CSS - Clock Mux 1 Select Status Register */ 430 /*! @{ */ 431 432 #define MC_CGM_MUX_1_CSS_CLK_SW_MASK (0x4U) 433 #define MC_CGM_MUX_1_CSS_CLK_SW_SHIFT (2U) 434 #define MC_CGM_MUX_1_CSS_CLK_SW_WIDTH (1U) 435 #define MC_CGM_MUX_1_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_1_CSS_CLK_SW_MASK) 436 437 #define MC_CGM_MUX_1_CSS_SAFE_SW_MASK (0x8U) 438 #define MC_CGM_MUX_1_CSS_SAFE_SW_SHIFT (3U) 439 #define MC_CGM_MUX_1_CSS_SAFE_SW_WIDTH (1U) 440 #define MC_CGM_MUX_1_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_1_CSS_SAFE_SW_MASK) 441 442 #define MC_CGM_MUX_1_CSS_SWIP_MASK (0x10000U) 443 #define MC_CGM_MUX_1_CSS_SWIP_SHIFT (16U) 444 #define MC_CGM_MUX_1_CSS_SWIP_WIDTH (1U) 445 #define MC_CGM_MUX_1_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_SWIP_SHIFT)) & MC_CGM_MUX_1_CSS_SWIP_MASK) 446 447 #define MC_CGM_MUX_1_CSS_SWTRG_MASK (0xE0000U) 448 #define MC_CGM_MUX_1_CSS_SWTRG_SHIFT (17U) 449 #define MC_CGM_MUX_1_CSS_SWTRG_WIDTH (3U) 450 #define MC_CGM_MUX_1_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_1_CSS_SWTRG_MASK) 451 452 #define MC_CGM_MUX_1_CSS_SELSTAT_MASK (0x1F000000U) 453 #define MC_CGM_MUX_1_CSS_SELSTAT_SHIFT (24U) 454 #define MC_CGM_MUX_1_CSS_SELSTAT_WIDTH (5U) 455 #define MC_CGM_MUX_1_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_1_CSS_SELSTAT_MASK) 456 /*! @} */ 457 458 /*! @name MUX_1_DC_0 - Clock Mux 1 Divider 0 Control Register */ 459 /*! @{ */ 460 461 #define MC_CGM_MUX_1_DC_0_DIV_MASK (0x10000U) 462 #define MC_CGM_MUX_1_DC_0_DIV_SHIFT (16U) 463 #define MC_CGM_MUX_1_DC_0_DIV_WIDTH (1U) 464 #define MC_CGM_MUX_1_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_DC_0_DIV_SHIFT)) & MC_CGM_MUX_1_DC_0_DIV_MASK) 465 466 #define MC_CGM_MUX_1_DC_0_DE_MASK (0x80000000U) 467 #define MC_CGM_MUX_1_DC_0_DE_SHIFT (31U) 468 #define MC_CGM_MUX_1_DC_0_DE_WIDTH (1U) 469 #define MC_CGM_MUX_1_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_DC_0_DE_SHIFT)) & MC_CGM_MUX_1_DC_0_DE_MASK) 470 /*! @} */ 471 472 /*! @name MUX_1_DIV_UPD_STAT - Clock Mux 1 Divider Update Status Register */ 473 /*! @{ */ 474 475 #define MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 476 #define MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 477 #define MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 478 #define MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_MASK) 479 /*! @} */ 480 481 /*! @name MUX_2_CSC - Clock Mux 2 Select Control Register */ 482 /*! @{ */ 483 484 #define MC_CGM_MUX_2_CSC_CLK_SW_MASK (0x4U) 485 #define MC_CGM_MUX_2_CSC_CLK_SW_SHIFT (2U) 486 #define MC_CGM_MUX_2_CSC_CLK_SW_WIDTH (1U) 487 #define MC_CGM_MUX_2_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_2_CSC_CLK_SW_MASK) 488 489 #define MC_CGM_MUX_2_CSC_SAFE_SW_MASK (0x8U) 490 #define MC_CGM_MUX_2_CSC_SAFE_SW_SHIFT (3U) 491 #define MC_CGM_MUX_2_CSC_SAFE_SW_WIDTH (1U) 492 #define MC_CGM_MUX_2_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_2_CSC_SAFE_SW_MASK) 493 494 #define MC_CGM_MUX_2_CSC_SELCTL_MASK (0x1F000000U) 495 #define MC_CGM_MUX_2_CSC_SELCTL_SHIFT (24U) 496 #define MC_CGM_MUX_2_CSC_SELCTL_WIDTH (5U) 497 #define MC_CGM_MUX_2_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_2_CSC_SELCTL_MASK) 498 /*! @} */ 499 500 /*! @name MUX_2_CSS - Clock Mux 2 Select Status Register */ 501 /*! @{ */ 502 503 #define MC_CGM_MUX_2_CSS_CLK_SW_MASK (0x4U) 504 #define MC_CGM_MUX_2_CSS_CLK_SW_SHIFT (2U) 505 #define MC_CGM_MUX_2_CSS_CLK_SW_WIDTH (1U) 506 #define MC_CGM_MUX_2_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_2_CSS_CLK_SW_MASK) 507 508 #define MC_CGM_MUX_2_CSS_SAFE_SW_MASK (0x8U) 509 #define MC_CGM_MUX_2_CSS_SAFE_SW_SHIFT (3U) 510 #define MC_CGM_MUX_2_CSS_SAFE_SW_WIDTH (1U) 511 #define MC_CGM_MUX_2_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_2_CSS_SAFE_SW_MASK) 512 513 #define MC_CGM_MUX_2_CSS_SWIP_MASK (0x10000U) 514 #define MC_CGM_MUX_2_CSS_SWIP_SHIFT (16U) 515 #define MC_CGM_MUX_2_CSS_SWIP_WIDTH (1U) 516 #define MC_CGM_MUX_2_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_SWIP_SHIFT)) & MC_CGM_MUX_2_CSS_SWIP_MASK) 517 518 #define MC_CGM_MUX_2_CSS_SWTRG_MASK (0xE0000U) 519 #define MC_CGM_MUX_2_CSS_SWTRG_SHIFT (17U) 520 #define MC_CGM_MUX_2_CSS_SWTRG_WIDTH (3U) 521 #define MC_CGM_MUX_2_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_2_CSS_SWTRG_MASK) 522 523 #define MC_CGM_MUX_2_CSS_SELSTAT_MASK (0x1F000000U) 524 #define MC_CGM_MUX_2_CSS_SELSTAT_SHIFT (24U) 525 #define MC_CGM_MUX_2_CSS_SELSTAT_WIDTH (5U) 526 #define MC_CGM_MUX_2_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_2_CSS_SELSTAT_MASK) 527 /*! @} */ 528 529 /*! @name MUX_2_DC_0 - Clock Mux 2 Divider 0 Control Register */ 530 /*! @{ */ 531 532 #define MC_CGM_MUX_2_DC_0_DIV_MASK (0x10000U) 533 #define MC_CGM_MUX_2_DC_0_DIV_SHIFT (16U) 534 #define MC_CGM_MUX_2_DC_0_DIV_WIDTH (1U) 535 #define MC_CGM_MUX_2_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_0_DIV_SHIFT)) & MC_CGM_MUX_2_DC_0_DIV_MASK) 536 537 #define MC_CGM_MUX_2_DC_0_DE_MASK (0x80000000U) 538 #define MC_CGM_MUX_2_DC_0_DE_SHIFT (31U) 539 #define MC_CGM_MUX_2_DC_0_DE_WIDTH (1U) 540 #define MC_CGM_MUX_2_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DC_0_DE_SHIFT)) & MC_CGM_MUX_2_DC_0_DE_MASK) 541 /*! @} */ 542 543 /*! @name MUX_2_DIV_UPD_STAT - Clock Mux 2 Divider Update Status Register */ 544 /*! @{ */ 545 546 #define MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 547 #define MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 548 #define MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 549 #define MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_2_DIV_UPD_STAT_DIV_STAT_MASK) 550 /*! @} */ 551 552 /*! @name MUX_3_CSC - Clock Mux 3 Select Control Register */ 553 /*! @{ */ 554 555 #define MC_CGM_MUX_3_CSC_CLK_SW_MASK (0x4U) 556 #define MC_CGM_MUX_3_CSC_CLK_SW_SHIFT (2U) 557 #define MC_CGM_MUX_3_CSC_CLK_SW_WIDTH (1U) 558 #define MC_CGM_MUX_3_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_3_CSC_CLK_SW_MASK) 559 560 #define MC_CGM_MUX_3_CSC_SAFE_SW_MASK (0x8U) 561 #define MC_CGM_MUX_3_CSC_SAFE_SW_SHIFT (3U) 562 #define MC_CGM_MUX_3_CSC_SAFE_SW_WIDTH (1U) 563 #define MC_CGM_MUX_3_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_3_CSC_SAFE_SW_MASK) 564 565 #define MC_CGM_MUX_3_CSC_SELCTL_MASK (0x1F000000U) 566 #define MC_CGM_MUX_3_CSC_SELCTL_SHIFT (24U) 567 #define MC_CGM_MUX_3_CSC_SELCTL_WIDTH (5U) 568 #define MC_CGM_MUX_3_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_3_CSC_SELCTL_MASK) 569 /*! @} */ 570 571 /*! @name MUX_3_CSS - Clock Mux 3 Select Status Register */ 572 /*! @{ */ 573 574 #define MC_CGM_MUX_3_CSS_CLK_SW_MASK (0x4U) 575 #define MC_CGM_MUX_3_CSS_CLK_SW_SHIFT (2U) 576 #define MC_CGM_MUX_3_CSS_CLK_SW_WIDTH (1U) 577 #define MC_CGM_MUX_3_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_3_CSS_CLK_SW_MASK) 578 579 #define MC_CGM_MUX_3_CSS_SAFE_SW_MASK (0x8U) 580 #define MC_CGM_MUX_3_CSS_SAFE_SW_SHIFT (3U) 581 #define MC_CGM_MUX_3_CSS_SAFE_SW_WIDTH (1U) 582 #define MC_CGM_MUX_3_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_3_CSS_SAFE_SW_MASK) 583 584 #define MC_CGM_MUX_3_CSS_SWIP_MASK (0x10000U) 585 #define MC_CGM_MUX_3_CSS_SWIP_SHIFT (16U) 586 #define MC_CGM_MUX_3_CSS_SWIP_WIDTH (1U) 587 #define MC_CGM_MUX_3_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_SWIP_SHIFT)) & MC_CGM_MUX_3_CSS_SWIP_MASK) 588 589 #define MC_CGM_MUX_3_CSS_SWTRG_MASK (0xE0000U) 590 #define MC_CGM_MUX_3_CSS_SWTRG_SHIFT (17U) 591 #define MC_CGM_MUX_3_CSS_SWTRG_WIDTH (3U) 592 #define MC_CGM_MUX_3_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_3_CSS_SWTRG_MASK) 593 594 #define MC_CGM_MUX_3_CSS_SELSTAT_MASK (0x1F000000U) 595 #define MC_CGM_MUX_3_CSS_SELSTAT_SHIFT (24U) 596 #define MC_CGM_MUX_3_CSS_SELSTAT_WIDTH (5U) 597 #define MC_CGM_MUX_3_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_3_CSS_SELSTAT_MASK) 598 /*! @} */ 599 600 /*! @name MUX_3_DC_0 - Clock Mux 3 Divider 0 Control Register */ 601 /*! @{ */ 602 603 #define MC_CGM_MUX_3_DC_0_DIV_MASK (0x30000U) 604 #define MC_CGM_MUX_3_DC_0_DIV_SHIFT (16U) 605 #define MC_CGM_MUX_3_DC_0_DIV_WIDTH (2U) 606 #define MC_CGM_MUX_3_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_0_DIV_SHIFT)) & MC_CGM_MUX_3_DC_0_DIV_MASK) 607 608 #define MC_CGM_MUX_3_DC_0_DE_MASK (0x80000000U) 609 #define MC_CGM_MUX_3_DC_0_DE_SHIFT (31U) 610 #define MC_CGM_MUX_3_DC_0_DE_WIDTH (1U) 611 #define MC_CGM_MUX_3_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DC_0_DE_SHIFT)) & MC_CGM_MUX_3_DC_0_DE_MASK) 612 /*! @} */ 613 614 /*! @name MUX_3_DIV_UPD_STAT - Clock Mux 3 Divider Update Status Register */ 615 /*! @{ */ 616 617 #define MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 618 #define MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 619 #define MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 620 #define MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_3_DIV_UPD_STAT_DIV_STAT_MASK) 621 /*! @} */ 622 623 /*! @name MUX_4_CSC - Clock Mux 4 Select Control Register */ 624 /*! @{ */ 625 626 #define MC_CGM_MUX_4_CSC_CLK_SW_MASK (0x4U) 627 #define MC_CGM_MUX_4_CSC_CLK_SW_SHIFT (2U) 628 #define MC_CGM_MUX_4_CSC_CLK_SW_WIDTH (1U) 629 #define MC_CGM_MUX_4_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_4_CSC_CLK_SW_MASK) 630 631 #define MC_CGM_MUX_4_CSC_SAFE_SW_MASK (0x8U) 632 #define MC_CGM_MUX_4_CSC_SAFE_SW_SHIFT (3U) 633 #define MC_CGM_MUX_4_CSC_SAFE_SW_WIDTH (1U) 634 #define MC_CGM_MUX_4_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_4_CSC_SAFE_SW_MASK) 635 636 #define MC_CGM_MUX_4_CSC_SELCTL_MASK (0x1F000000U) 637 #define MC_CGM_MUX_4_CSC_SELCTL_SHIFT (24U) 638 #define MC_CGM_MUX_4_CSC_SELCTL_WIDTH (5U) 639 #define MC_CGM_MUX_4_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_4_CSC_SELCTL_MASK) 640 /*! @} */ 641 642 /*! @name MUX_4_CSS - Clock Mux 4 Select Status Register */ 643 /*! @{ */ 644 645 #define MC_CGM_MUX_4_CSS_CLK_SW_MASK (0x4U) 646 #define MC_CGM_MUX_4_CSS_CLK_SW_SHIFT (2U) 647 #define MC_CGM_MUX_4_CSS_CLK_SW_WIDTH (1U) 648 #define MC_CGM_MUX_4_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_4_CSS_CLK_SW_MASK) 649 650 #define MC_CGM_MUX_4_CSS_SAFE_SW_MASK (0x8U) 651 #define MC_CGM_MUX_4_CSS_SAFE_SW_SHIFT (3U) 652 #define MC_CGM_MUX_4_CSS_SAFE_SW_WIDTH (1U) 653 #define MC_CGM_MUX_4_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_4_CSS_SAFE_SW_MASK) 654 655 #define MC_CGM_MUX_4_CSS_SWIP_MASK (0x10000U) 656 #define MC_CGM_MUX_4_CSS_SWIP_SHIFT (16U) 657 #define MC_CGM_MUX_4_CSS_SWIP_WIDTH (1U) 658 #define MC_CGM_MUX_4_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_SWIP_SHIFT)) & MC_CGM_MUX_4_CSS_SWIP_MASK) 659 660 #define MC_CGM_MUX_4_CSS_SWTRG_MASK (0xE0000U) 661 #define MC_CGM_MUX_4_CSS_SWTRG_SHIFT (17U) 662 #define MC_CGM_MUX_4_CSS_SWTRG_WIDTH (3U) 663 #define MC_CGM_MUX_4_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_4_CSS_SWTRG_MASK) 664 665 #define MC_CGM_MUX_4_CSS_SELSTAT_MASK (0x1F000000U) 666 #define MC_CGM_MUX_4_CSS_SELSTAT_SHIFT (24U) 667 #define MC_CGM_MUX_4_CSS_SELSTAT_WIDTH (5U) 668 #define MC_CGM_MUX_4_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_4_CSS_SELSTAT_MASK) 669 /*! @} */ 670 671 /*! @name MUX_4_DC_0 - Clock Mux 4 Divider 0 Control Register */ 672 /*! @{ */ 673 674 #define MC_CGM_MUX_4_DC_0_DIV_MASK (0x30000U) 675 #define MC_CGM_MUX_4_DC_0_DIV_SHIFT (16U) 676 #define MC_CGM_MUX_4_DC_0_DIV_WIDTH (2U) 677 #define MC_CGM_MUX_4_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_DC_0_DIV_SHIFT)) & MC_CGM_MUX_4_DC_0_DIV_MASK) 678 679 #define MC_CGM_MUX_4_DC_0_DE_MASK (0x80000000U) 680 #define MC_CGM_MUX_4_DC_0_DE_SHIFT (31U) 681 #define MC_CGM_MUX_4_DC_0_DE_WIDTH (1U) 682 #define MC_CGM_MUX_4_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_DC_0_DE_SHIFT)) & MC_CGM_MUX_4_DC_0_DE_MASK) 683 /*! @} */ 684 685 /*! @name MUX_4_DIV_UPD_STAT - Clock Mux 4 Divider Update Status Register */ 686 /*! @{ */ 687 688 #define MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 689 #define MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 690 #define MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 691 #define MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_4_DIV_UPD_STAT_DIV_STAT_MASK) 692 /*! @} */ 693 694 /*! @name MUX_5_CSC - Clock Mux 5 Select Control Register */ 695 /*! @{ */ 696 697 #define MC_CGM_MUX_5_CSC_CG_MASK (0x4U) 698 #define MC_CGM_MUX_5_CSC_CG_SHIFT (2U) 699 #define MC_CGM_MUX_5_CSC_CG_WIDTH (1U) 700 #define MC_CGM_MUX_5_CSC_CG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSC_CG_SHIFT)) & MC_CGM_MUX_5_CSC_CG_MASK) 701 702 #define MC_CGM_MUX_5_CSC_FCG_MASK (0x8U) 703 #define MC_CGM_MUX_5_CSC_FCG_SHIFT (3U) 704 #define MC_CGM_MUX_5_CSC_FCG_WIDTH (1U) 705 #define MC_CGM_MUX_5_CSC_FCG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSC_FCG_SHIFT)) & MC_CGM_MUX_5_CSC_FCG_MASK) 706 707 #define MC_CGM_MUX_5_CSC_SELCTL_MASK (0x3F000000U) 708 #define MC_CGM_MUX_5_CSC_SELCTL_SHIFT (24U) 709 #define MC_CGM_MUX_5_CSC_SELCTL_WIDTH (6U) 710 #define MC_CGM_MUX_5_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_5_CSC_SELCTL_MASK) 711 /*! @} */ 712 713 /*! @name MUX_5_CSS - Clock Mux 5 Select Status Register */ 714 /*! @{ */ 715 716 #define MC_CGM_MUX_5_CSS_GRIP_MASK (0x10000U) 717 #define MC_CGM_MUX_5_CSS_GRIP_SHIFT (16U) 718 #define MC_CGM_MUX_5_CSS_GRIP_WIDTH (1U) 719 #define MC_CGM_MUX_5_CSS_GRIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSS_GRIP_SHIFT)) & MC_CGM_MUX_5_CSS_GRIP_MASK) 720 721 #define MC_CGM_MUX_5_CSS_CS_MASK (0x20000U) 722 #define MC_CGM_MUX_5_CSS_CS_SHIFT (17U) 723 #define MC_CGM_MUX_5_CSS_CS_WIDTH (1U) 724 #define MC_CGM_MUX_5_CSS_CS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSS_CS_SHIFT)) & MC_CGM_MUX_5_CSS_CS_MASK) 725 726 #define MC_CGM_MUX_5_CSS_SELSTAT_MASK (0x3F000000U) 727 #define MC_CGM_MUX_5_CSS_SELSTAT_SHIFT (24U) 728 #define MC_CGM_MUX_5_CSS_SELSTAT_WIDTH (6U) 729 #define MC_CGM_MUX_5_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_5_CSS_SELSTAT_MASK) 730 /*! @} */ 731 732 /*! @name MUX_5_DC_0 - Clock Mux 5 Divider 0 Control Register */ 733 /*! @{ */ 734 735 #define MC_CGM_MUX_5_DC_0_DIV_MASK (0x70000U) 736 #define MC_CGM_MUX_5_DC_0_DIV_SHIFT (16U) 737 #define MC_CGM_MUX_5_DC_0_DIV_WIDTH (3U) 738 #define MC_CGM_MUX_5_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DC_0_DIV_SHIFT)) & MC_CGM_MUX_5_DC_0_DIV_MASK) 739 740 #define MC_CGM_MUX_5_DC_0_DE_MASK (0x80000000U) 741 #define MC_CGM_MUX_5_DC_0_DE_SHIFT (31U) 742 #define MC_CGM_MUX_5_DC_0_DE_WIDTH (1U) 743 #define MC_CGM_MUX_5_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DC_0_DE_SHIFT)) & MC_CGM_MUX_5_DC_0_DE_MASK) 744 /*! @} */ 745 746 /*! @name MUX_5_DIV_UPD_STAT - Clock Mux 5 Divider Update Status Register */ 747 /*! @{ */ 748 749 #define MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 750 #define MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 751 #define MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 752 #define MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_MASK) 753 /*! @} */ 754 755 /*! @name MUX_6_CSC - Clock Mux 6 Select Control Register */ 756 /*! @{ */ 757 758 #define MC_CGM_MUX_6_CSC_CG_MASK (0x4U) 759 #define MC_CGM_MUX_6_CSC_CG_SHIFT (2U) 760 #define MC_CGM_MUX_6_CSC_CG_WIDTH (1U) 761 #define MC_CGM_MUX_6_CSC_CG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSC_CG_SHIFT)) & MC_CGM_MUX_6_CSC_CG_MASK) 762 763 #define MC_CGM_MUX_6_CSC_FCG_MASK (0x8U) 764 #define MC_CGM_MUX_6_CSC_FCG_SHIFT (3U) 765 #define MC_CGM_MUX_6_CSC_FCG_WIDTH (1U) 766 #define MC_CGM_MUX_6_CSC_FCG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSC_FCG_SHIFT)) & MC_CGM_MUX_6_CSC_FCG_MASK) 767 768 #define MC_CGM_MUX_6_CSC_SELCTL_MASK (0x3F000000U) 769 #define MC_CGM_MUX_6_CSC_SELCTL_SHIFT (24U) 770 #define MC_CGM_MUX_6_CSC_SELCTL_WIDTH (6U) 771 #define MC_CGM_MUX_6_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_6_CSC_SELCTL_MASK) 772 /*! @} */ 773 774 /*! @name MUX_6_CSS - Clock Mux 6 Select Status Register */ 775 /*! @{ */ 776 777 #define MC_CGM_MUX_6_CSS_GRIP_MASK (0x10000U) 778 #define MC_CGM_MUX_6_CSS_GRIP_SHIFT (16U) 779 #define MC_CGM_MUX_6_CSS_GRIP_WIDTH (1U) 780 #define MC_CGM_MUX_6_CSS_GRIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_GRIP_SHIFT)) & MC_CGM_MUX_6_CSS_GRIP_MASK) 781 782 #define MC_CGM_MUX_6_CSS_CS_MASK (0x20000U) 783 #define MC_CGM_MUX_6_CSS_CS_SHIFT (17U) 784 #define MC_CGM_MUX_6_CSS_CS_WIDTH (1U) 785 #define MC_CGM_MUX_6_CSS_CS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_CS_SHIFT)) & MC_CGM_MUX_6_CSS_CS_MASK) 786 787 #define MC_CGM_MUX_6_CSS_SELSTAT_MASK (0x3F000000U) 788 #define MC_CGM_MUX_6_CSS_SELSTAT_SHIFT (24U) 789 #define MC_CGM_MUX_6_CSS_SELSTAT_WIDTH (6U) 790 #define MC_CGM_MUX_6_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_6_CSS_SELSTAT_MASK) 791 /*! @} */ 792 793 /*! @name MUX_6_DC_0 - Clock Mux 6 Divider 0 Control Register */ 794 /*! @{ */ 795 796 #define MC_CGM_MUX_6_DC_0_DIV_MASK (0x3F0000U) 797 #define MC_CGM_MUX_6_DC_0_DIV_SHIFT (16U) 798 #define MC_CGM_MUX_6_DC_0_DIV_WIDTH (6U) 799 #define MC_CGM_MUX_6_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_DC_0_DIV_SHIFT)) & MC_CGM_MUX_6_DC_0_DIV_MASK) 800 801 #define MC_CGM_MUX_6_DC_0_DE_MASK (0x80000000U) 802 #define MC_CGM_MUX_6_DC_0_DE_SHIFT (31U) 803 #define MC_CGM_MUX_6_DC_0_DE_WIDTH (1U) 804 #define MC_CGM_MUX_6_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_DC_0_DE_SHIFT)) & MC_CGM_MUX_6_DC_0_DE_MASK) 805 /*! @} */ 806 807 /*! @name MUX_6_DIV_UPD_STAT - Clock Mux 6 Divider Update Status Register */ 808 /*! @{ */ 809 810 #define MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 811 #define MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 812 #define MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 813 #define MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_6_DIV_UPD_STAT_DIV_STAT_MASK) 814 /*! @} */ 815 816 /*! @name MUX_7_CSC - Clock Mux 7 Select Control Register */ 817 /*! @{ */ 818 819 #define MC_CGM_MUX_7_CSC_CLK_SW_MASK (0x4U) 820 #define MC_CGM_MUX_7_CSC_CLK_SW_SHIFT (2U) 821 #define MC_CGM_MUX_7_CSC_CLK_SW_WIDTH (1U) 822 #define MC_CGM_MUX_7_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_7_CSC_CLK_SW_MASK) 823 824 #define MC_CGM_MUX_7_CSC_SAFE_SW_MASK (0x8U) 825 #define MC_CGM_MUX_7_CSC_SAFE_SW_SHIFT (3U) 826 #define MC_CGM_MUX_7_CSC_SAFE_SW_WIDTH (1U) 827 #define MC_CGM_MUX_7_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_7_CSC_SAFE_SW_MASK) 828 829 #define MC_CGM_MUX_7_CSC_SELCTL_MASK (0x1F000000U) 830 #define MC_CGM_MUX_7_CSC_SELCTL_SHIFT (24U) 831 #define MC_CGM_MUX_7_CSC_SELCTL_WIDTH (5U) 832 #define MC_CGM_MUX_7_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_7_CSC_SELCTL_MASK) 833 /*! @} */ 834 835 /*! @name MUX_7_CSS - Clock Mux 7 Select Status Register */ 836 /*! @{ */ 837 838 #define MC_CGM_MUX_7_CSS_CLK_SW_MASK (0x4U) 839 #define MC_CGM_MUX_7_CSS_CLK_SW_SHIFT (2U) 840 #define MC_CGM_MUX_7_CSS_CLK_SW_WIDTH (1U) 841 #define MC_CGM_MUX_7_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_7_CSS_CLK_SW_MASK) 842 843 #define MC_CGM_MUX_7_CSS_SAFE_SW_MASK (0x8U) 844 #define MC_CGM_MUX_7_CSS_SAFE_SW_SHIFT (3U) 845 #define MC_CGM_MUX_7_CSS_SAFE_SW_WIDTH (1U) 846 #define MC_CGM_MUX_7_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_7_CSS_SAFE_SW_MASK) 847 848 #define MC_CGM_MUX_7_CSS_SWIP_MASK (0x10000U) 849 #define MC_CGM_MUX_7_CSS_SWIP_SHIFT (16U) 850 #define MC_CGM_MUX_7_CSS_SWIP_WIDTH (1U) 851 #define MC_CGM_MUX_7_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_SWIP_SHIFT)) & MC_CGM_MUX_7_CSS_SWIP_MASK) 852 853 #define MC_CGM_MUX_7_CSS_SWTRG_MASK (0xE0000U) 854 #define MC_CGM_MUX_7_CSS_SWTRG_SHIFT (17U) 855 #define MC_CGM_MUX_7_CSS_SWTRG_WIDTH (3U) 856 #define MC_CGM_MUX_7_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_7_CSS_SWTRG_MASK) 857 858 #define MC_CGM_MUX_7_CSS_SELSTAT_MASK (0x1F000000U) 859 #define MC_CGM_MUX_7_CSS_SELSTAT_SHIFT (24U) 860 #define MC_CGM_MUX_7_CSS_SELSTAT_WIDTH (5U) 861 #define MC_CGM_MUX_7_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_7_CSS_SELSTAT_MASK) 862 /*! @} */ 863 864 /*! @name MUX_7_DC_0 - Clock Mux 7 Divider 0 Control Register */ 865 /*! @{ */ 866 867 #define MC_CGM_MUX_7_DC_0_DIV_MASK (0x3F0000U) 868 #define MC_CGM_MUX_7_DC_0_DIV_SHIFT (16U) 869 #define MC_CGM_MUX_7_DC_0_DIV_WIDTH (6U) 870 #define MC_CGM_MUX_7_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DC_0_DIV_SHIFT)) & MC_CGM_MUX_7_DC_0_DIV_MASK) 871 872 #define MC_CGM_MUX_7_DC_0_DE_MASK (0x80000000U) 873 #define MC_CGM_MUX_7_DC_0_DE_SHIFT (31U) 874 #define MC_CGM_MUX_7_DC_0_DE_WIDTH (1U) 875 #define MC_CGM_MUX_7_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DC_0_DE_SHIFT)) & MC_CGM_MUX_7_DC_0_DE_MASK) 876 /*! @} */ 877 878 /*! @name MUX_7_DIV_UPD_STAT - Clock Mux 7 Divider Update Status Register */ 879 /*! @{ */ 880 881 #define MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 882 #define MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 883 #define MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 884 #define MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_7_DIV_UPD_STAT_DIV_STAT_MASK) 885 /*! @} */ 886 887 /*! @name MUX_8_CSC - Clock Mux 8 Select Control Register */ 888 /*! @{ */ 889 890 #define MC_CGM_MUX_8_CSC_CLK_SW_MASK (0x4U) 891 #define MC_CGM_MUX_8_CSC_CLK_SW_SHIFT (2U) 892 #define MC_CGM_MUX_8_CSC_CLK_SW_WIDTH (1U) 893 #define MC_CGM_MUX_8_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_8_CSC_CLK_SW_MASK) 894 895 #define MC_CGM_MUX_8_CSC_SAFE_SW_MASK (0x8U) 896 #define MC_CGM_MUX_8_CSC_SAFE_SW_SHIFT (3U) 897 #define MC_CGM_MUX_8_CSC_SAFE_SW_WIDTH (1U) 898 #define MC_CGM_MUX_8_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_8_CSC_SAFE_SW_MASK) 899 900 #define MC_CGM_MUX_8_CSC_SELCTL_MASK (0x1F000000U) 901 #define MC_CGM_MUX_8_CSC_SELCTL_SHIFT (24U) 902 #define MC_CGM_MUX_8_CSC_SELCTL_WIDTH (5U) 903 #define MC_CGM_MUX_8_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_8_CSC_SELCTL_MASK) 904 /*! @} */ 905 906 /*! @name MUX_8_CSS - Clock Mux 8 Select Status Register */ 907 /*! @{ */ 908 909 #define MC_CGM_MUX_8_CSS_CLK_SW_MASK (0x4U) 910 #define MC_CGM_MUX_8_CSS_CLK_SW_SHIFT (2U) 911 #define MC_CGM_MUX_8_CSS_CLK_SW_WIDTH (1U) 912 #define MC_CGM_MUX_8_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_8_CSS_CLK_SW_MASK) 913 914 #define MC_CGM_MUX_8_CSS_SAFE_SW_MASK (0x8U) 915 #define MC_CGM_MUX_8_CSS_SAFE_SW_SHIFT (3U) 916 #define MC_CGM_MUX_8_CSS_SAFE_SW_WIDTH (1U) 917 #define MC_CGM_MUX_8_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_8_CSS_SAFE_SW_MASK) 918 919 #define MC_CGM_MUX_8_CSS_SWIP_MASK (0x10000U) 920 #define MC_CGM_MUX_8_CSS_SWIP_SHIFT (16U) 921 #define MC_CGM_MUX_8_CSS_SWIP_WIDTH (1U) 922 #define MC_CGM_MUX_8_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_SWIP_SHIFT)) & MC_CGM_MUX_8_CSS_SWIP_MASK) 923 924 #define MC_CGM_MUX_8_CSS_SWTRG_MASK (0xE0000U) 925 #define MC_CGM_MUX_8_CSS_SWTRG_SHIFT (17U) 926 #define MC_CGM_MUX_8_CSS_SWTRG_WIDTH (3U) 927 #define MC_CGM_MUX_8_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_8_CSS_SWTRG_MASK) 928 929 #define MC_CGM_MUX_8_CSS_SELSTAT_MASK (0x1F000000U) 930 #define MC_CGM_MUX_8_CSS_SELSTAT_SHIFT (24U) 931 #define MC_CGM_MUX_8_CSS_SELSTAT_WIDTH (5U) 932 #define MC_CGM_MUX_8_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_8_CSS_SELSTAT_MASK) 933 /*! @} */ 934 935 /*! @name MUX_8_DC_0 - Clock Mux 8 Divider 0 Control Register */ 936 /*! @{ */ 937 938 #define MC_CGM_MUX_8_DC_0_DIV_MASK (0x3F0000U) 939 #define MC_CGM_MUX_8_DC_0_DIV_SHIFT (16U) 940 #define MC_CGM_MUX_8_DC_0_DIV_WIDTH (6U) 941 #define MC_CGM_MUX_8_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_DC_0_DIV_SHIFT)) & MC_CGM_MUX_8_DC_0_DIV_MASK) 942 943 #define MC_CGM_MUX_8_DC_0_DE_MASK (0x80000000U) 944 #define MC_CGM_MUX_8_DC_0_DE_SHIFT (31U) 945 #define MC_CGM_MUX_8_DC_0_DE_WIDTH (1U) 946 #define MC_CGM_MUX_8_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_DC_0_DE_SHIFT)) & MC_CGM_MUX_8_DC_0_DE_MASK) 947 /*! @} */ 948 949 /*! @name MUX_8_DIV_UPD_STAT - Clock Mux 8 Divider Update Status Register */ 950 /*! @{ */ 951 952 #define MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 953 #define MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 954 #define MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 955 #define MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_8_DIV_UPD_STAT_DIV_STAT_MASK) 956 /*! @} */ 957 958 /*! @name MUX_9_CSC - Clock Mux 9 Select Control Register */ 959 /*! @{ */ 960 961 #define MC_CGM_MUX_9_CSC_CLK_SW_MASK (0x4U) 962 #define MC_CGM_MUX_9_CSC_CLK_SW_SHIFT (2U) 963 #define MC_CGM_MUX_9_CSC_CLK_SW_WIDTH (1U) 964 #define MC_CGM_MUX_9_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_9_CSC_CLK_SW_MASK) 965 966 #define MC_CGM_MUX_9_CSC_SAFE_SW_MASK (0x8U) 967 #define MC_CGM_MUX_9_CSC_SAFE_SW_SHIFT (3U) 968 #define MC_CGM_MUX_9_CSC_SAFE_SW_WIDTH (1U) 969 #define MC_CGM_MUX_9_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_9_CSC_SAFE_SW_MASK) 970 971 #define MC_CGM_MUX_9_CSC_SELCTL_MASK (0x1F000000U) 972 #define MC_CGM_MUX_9_CSC_SELCTL_SHIFT (24U) 973 #define MC_CGM_MUX_9_CSC_SELCTL_WIDTH (5U) 974 #define MC_CGM_MUX_9_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_9_CSC_SELCTL_MASK) 975 /*! @} */ 976 977 /*! @name MUX_9_CSS - Clock Mux 9 Select Status Register */ 978 /*! @{ */ 979 980 #define MC_CGM_MUX_9_CSS_CLK_SW_MASK (0x4U) 981 #define MC_CGM_MUX_9_CSS_CLK_SW_SHIFT (2U) 982 #define MC_CGM_MUX_9_CSS_CLK_SW_WIDTH (1U) 983 #define MC_CGM_MUX_9_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_9_CSS_CLK_SW_MASK) 984 985 #define MC_CGM_MUX_9_CSS_SAFE_SW_MASK (0x8U) 986 #define MC_CGM_MUX_9_CSS_SAFE_SW_SHIFT (3U) 987 #define MC_CGM_MUX_9_CSS_SAFE_SW_WIDTH (1U) 988 #define MC_CGM_MUX_9_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_9_CSS_SAFE_SW_MASK) 989 990 #define MC_CGM_MUX_9_CSS_SWIP_MASK (0x10000U) 991 #define MC_CGM_MUX_9_CSS_SWIP_SHIFT (16U) 992 #define MC_CGM_MUX_9_CSS_SWIP_WIDTH (1U) 993 #define MC_CGM_MUX_9_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_SWIP_SHIFT)) & MC_CGM_MUX_9_CSS_SWIP_MASK) 994 995 #define MC_CGM_MUX_9_CSS_SWTRG_MASK (0xE0000U) 996 #define MC_CGM_MUX_9_CSS_SWTRG_SHIFT (17U) 997 #define MC_CGM_MUX_9_CSS_SWTRG_WIDTH (3U) 998 #define MC_CGM_MUX_9_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_9_CSS_SWTRG_MASK) 999 1000 #define MC_CGM_MUX_9_CSS_SELSTAT_MASK (0x1F000000U) 1001 #define MC_CGM_MUX_9_CSS_SELSTAT_SHIFT (24U) 1002 #define MC_CGM_MUX_9_CSS_SELSTAT_WIDTH (5U) 1003 #define MC_CGM_MUX_9_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_9_CSS_SELSTAT_MASK) 1004 /*! @} */ 1005 1006 /*! @name MUX_9_DC_0 - Clock Mux 9 Divider 0 Control Register */ 1007 /*! @{ */ 1008 1009 #define MC_CGM_MUX_9_DC_0_DIV_MASK (0x3F0000U) 1010 #define MC_CGM_MUX_9_DC_0_DIV_SHIFT (16U) 1011 #define MC_CGM_MUX_9_DC_0_DIV_WIDTH (6U) 1012 #define MC_CGM_MUX_9_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DC_0_DIV_SHIFT)) & MC_CGM_MUX_9_DC_0_DIV_MASK) 1013 1014 #define MC_CGM_MUX_9_DC_0_DE_MASK (0x80000000U) 1015 #define MC_CGM_MUX_9_DC_0_DE_SHIFT (31U) 1016 #define MC_CGM_MUX_9_DC_0_DE_WIDTH (1U) 1017 #define MC_CGM_MUX_9_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DC_0_DE_SHIFT)) & MC_CGM_MUX_9_DC_0_DE_MASK) 1018 /*! @} */ 1019 1020 /*! @name MUX_9_DIV_UPD_STAT - Clock Mux 9 Divider Update Status Register */ 1021 /*! @{ */ 1022 1023 #define MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1024 #define MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1025 #define MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1026 #define MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_9_DIV_UPD_STAT_DIV_STAT_MASK) 1027 /*! @} */ 1028 1029 /*! @name MUX_10_CSC - Clock Mux 10 Select Control Register */ 1030 /*! @{ */ 1031 1032 #define MC_CGM_MUX_10_CSC_CLK_SW_MASK (0x4U) 1033 #define MC_CGM_MUX_10_CSC_CLK_SW_SHIFT (2U) 1034 #define MC_CGM_MUX_10_CSC_CLK_SW_WIDTH (1U) 1035 #define MC_CGM_MUX_10_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSC_CLK_SW_SHIFT)) & MC_CGM_MUX_10_CSC_CLK_SW_MASK) 1036 1037 #define MC_CGM_MUX_10_CSC_SAFE_SW_MASK (0x8U) 1038 #define MC_CGM_MUX_10_CSC_SAFE_SW_SHIFT (3U) 1039 #define MC_CGM_MUX_10_CSC_SAFE_SW_WIDTH (1U) 1040 #define MC_CGM_MUX_10_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSC_SAFE_SW_SHIFT)) & MC_CGM_MUX_10_CSC_SAFE_SW_MASK) 1041 1042 #define MC_CGM_MUX_10_CSC_SELCTL_MASK (0xF000000U) 1043 #define MC_CGM_MUX_10_CSC_SELCTL_SHIFT (24U) 1044 #define MC_CGM_MUX_10_CSC_SELCTL_WIDTH (4U) 1045 #define MC_CGM_MUX_10_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_10_CSC_SELCTL_MASK) 1046 /*! @} */ 1047 1048 /*! @name MUX_10_CSS - Clock Mux 10 Select Status Register */ 1049 /*! @{ */ 1050 1051 #define MC_CGM_MUX_10_CSS_CLK_SW_MASK (0x4U) 1052 #define MC_CGM_MUX_10_CSS_CLK_SW_SHIFT (2U) 1053 #define MC_CGM_MUX_10_CSS_CLK_SW_WIDTH (1U) 1054 #define MC_CGM_MUX_10_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_CLK_SW_SHIFT)) & MC_CGM_MUX_10_CSS_CLK_SW_MASK) 1055 1056 #define MC_CGM_MUX_10_CSS_SAFE_SW_MASK (0x8U) 1057 #define MC_CGM_MUX_10_CSS_SAFE_SW_SHIFT (3U) 1058 #define MC_CGM_MUX_10_CSS_SAFE_SW_WIDTH (1U) 1059 #define MC_CGM_MUX_10_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_SAFE_SW_SHIFT)) & MC_CGM_MUX_10_CSS_SAFE_SW_MASK) 1060 1061 #define MC_CGM_MUX_10_CSS_SWIP_MASK (0x10000U) 1062 #define MC_CGM_MUX_10_CSS_SWIP_SHIFT (16U) 1063 #define MC_CGM_MUX_10_CSS_SWIP_WIDTH (1U) 1064 #define MC_CGM_MUX_10_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_SWIP_SHIFT)) & MC_CGM_MUX_10_CSS_SWIP_MASK) 1065 1066 #define MC_CGM_MUX_10_CSS_SWTRG_MASK (0xE0000U) 1067 #define MC_CGM_MUX_10_CSS_SWTRG_SHIFT (17U) 1068 #define MC_CGM_MUX_10_CSS_SWTRG_WIDTH (3U) 1069 #define MC_CGM_MUX_10_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_SWTRG_SHIFT)) & MC_CGM_MUX_10_CSS_SWTRG_MASK) 1070 1071 #define MC_CGM_MUX_10_CSS_SELSTAT_MASK (0xF000000U) 1072 #define MC_CGM_MUX_10_CSS_SELSTAT_SHIFT (24U) 1073 #define MC_CGM_MUX_10_CSS_SELSTAT_WIDTH (4U) 1074 #define MC_CGM_MUX_10_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_10_CSS_SELSTAT_MASK) 1075 /*! @} */ 1076 1077 /*! @name MUX_10_DC_0 - Clock Mux 10 Divider 0 Control Register */ 1078 /*! @{ */ 1079 1080 #define MC_CGM_MUX_10_DC_0_DIV_MASK (0x70000U) 1081 #define MC_CGM_MUX_10_DC_0_DIV_SHIFT (16U) 1082 #define MC_CGM_MUX_10_DC_0_DIV_WIDTH (3U) 1083 #define MC_CGM_MUX_10_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_DC_0_DIV_SHIFT)) & MC_CGM_MUX_10_DC_0_DIV_MASK) 1084 1085 #define MC_CGM_MUX_10_DC_0_DE_MASK (0x80000000U) 1086 #define MC_CGM_MUX_10_DC_0_DE_SHIFT (31U) 1087 #define MC_CGM_MUX_10_DC_0_DE_WIDTH (1U) 1088 #define MC_CGM_MUX_10_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_DC_0_DE_SHIFT)) & MC_CGM_MUX_10_DC_0_DE_MASK) 1089 /*! @} */ 1090 1091 /*! @name MUX_10_DIV_UPD_STAT - Clock Mux 10 Divider Update Status Register */ 1092 /*! @{ */ 1093 1094 #define MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1095 #define MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1096 #define MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1097 #define MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_10_DIV_UPD_STAT_DIV_STAT_MASK) 1098 /*! @} */ 1099 1100 /*! @name MUX_11_CSC - Clock Mux 11 Select Control Register */ 1101 /*! @{ */ 1102 1103 #define MC_CGM_MUX_11_CSC_CG_MASK (0x4U) 1104 #define MC_CGM_MUX_11_CSC_CG_SHIFT (2U) 1105 #define MC_CGM_MUX_11_CSC_CG_WIDTH (1U) 1106 #define MC_CGM_MUX_11_CSC_CG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSC_CG_SHIFT)) & MC_CGM_MUX_11_CSC_CG_MASK) 1107 1108 #define MC_CGM_MUX_11_CSC_FCG_MASK (0x8U) 1109 #define MC_CGM_MUX_11_CSC_FCG_SHIFT (3U) 1110 #define MC_CGM_MUX_11_CSC_FCG_WIDTH (1U) 1111 #define MC_CGM_MUX_11_CSC_FCG(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSC_FCG_SHIFT)) & MC_CGM_MUX_11_CSC_FCG_MASK) 1112 1113 #define MC_CGM_MUX_11_CSC_SELCTL_MASK (0xF000000U) 1114 #define MC_CGM_MUX_11_CSC_SELCTL_SHIFT (24U) 1115 #define MC_CGM_MUX_11_CSC_SELCTL_WIDTH (4U) 1116 #define MC_CGM_MUX_11_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSC_SELCTL_SHIFT)) & MC_CGM_MUX_11_CSC_SELCTL_MASK) 1117 /*! @} */ 1118 1119 /*! @name MUX_11_CSS - Clock Mux 11 Select Status Register */ 1120 /*! @{ */ 1121 1122 #define MC_CGM_MUX_11_CSS_GRIP_MASK (0x10000U) 1123 #define MC_CGM_MUX_11_CSS_GRIP_SHIFT (16U) 1124 #define MC_CGM_MUX_11_CSS_GRIP_WIDTH (1U) 1125 #define MC_CGM_MUX_11_CSS_GRIP(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSS_GRIP_SHIFT)) & MC_CGM_MUX_11_CSS_GRIP_MASK) 1126 1127 #define MC_CGM_MUX_11_CSS_CS_MASK (0x20000U) 1128 #define MC_CGM_MUX_11_CSS_CS_SHIFT (17U) 1129 #define MC_CGM_MUX_11_CSS_CS_WIDTH (1U) 1130 #define MC_CGM_MUX_11_CSS_CS(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSS_CS_SHIFT)) & MC_CGM_MUX_11_CSS_CS_MASK) 1131 1132 #define MC_CGM_MUX_11_CSS_SELSTAT_MASK (0xF000000U) 1133 #define MC_CGM_MUX_11_CSS_SELSTAT_SHIFT (24U) 1134 #define MC_CGM_MUX_11_CSS_SELSTAT_WIDTH (4U) 1135 #define MC_CGM_MUX_11_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_CSS_SELSTAT_SHIFT)) & MC_CGM_MUX_11_CSS_SELSTAT_MASK) 1136 /*! @} */ 1137 1138 /*! @name MUX_11_DC_0 - Clock Mux 11 Divider 0 Control Register */ 1139 /*! @{ */ 1140 1141 #define MC_CGM_MUX_11_DC_0_DIV_MASK (0x70000U) 1142 #define MC_CGM_MUX_11_DC_0_DIV_SHIFT (16U) 1143 #define MC_CGM_MUX_11_DC_0_DIV_WIDTH (3U) 1144 #define MC_CGM_MUX_11_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_DC_0_DIV_SHIFT)) & MC_CGM_MUX_11_DC_0_DIV_MASK) 1145 1146 #define MC_CGM_MUX_11_DC_0_DE_MASK (0x80000000U) 1147 #define MC_CGM_MUX_11_DC_0_DE_SHIFT (31U) 1148 #define MC_CGM_MUX_11_DC_0_DE_WIDTH (1U) 1149 #define MC_CGM_MUX_11_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_DC_0_DE_SHIFT)) & MC_CGM_MUX_11_DC_0_DE_MASK) 1150 /*! @} */ 1151 1152 /*! @name MUX_11_DIV_UPD_STAT - Clock Mux 11 Divider Update Status Register */ 1153 /*! @{ */ 1154 1155 #define MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 1156 #define MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 1157 #define MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 1158 #define MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_SHIFT)) & MC_CGM_MUX_11_DIV_UPD_STAT_DIV_STAT_MASK) 1159 /*! @} */ 1160 1161 /*! 1162 * @} 1163 */ /* end of group MC_CGM_Register_Masks */ 1164 1165 /*! 1166 * @} 1167 */ /* end of group MC_CGM_Peripheral_Access_Layer */ 1168 1169 #endif /* #if !defined(S32K344_MC_CGM_H_) */ 1170
