Home
last modified time | relevance | path

Searched refs:MCTRL (Results 1 – 25 of 42) sorted by relevance

12

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/pwm/
Dfsl_pwm.c145 base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); in PWM_Init()
148 base->MCTRL |= ((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); in PWM_Init()
209 base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_RUN_SHIFT + (uint16_t)subModule)); in PWM_Deinit()
530 if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) in PWM_SetupPwmPhaseShift()
532 base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); in PWM_SetupPwmPhaseShift()
571 base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); in PWM_SetupPwmPhaseShift()
1087 if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) in PWM_SetOutputToIdle()
1089 base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); in PWM_SetOutputToIdle()
1153 base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); in PWM_SetOutputToIdle()
1189 if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) in PWM_SetClockMode()
[all …]
Dfsl_pwm.h807 base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); in PWM_StartTimer()
822 base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); in PWM_StopTimer()
1010 base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); in PWM_SetPwmLdok()
1014 base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); in PWM_SetPwmLdok()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/i3c/
Dfsl_i3c.c701 …base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK… in I3C_MasterEmitStop()
1230 mctrlVal = base->MCTRL; in I3C_MasterRepeatedStartWithRxSize()
1236 base->MCTRL = mctrlVal; in I3C_MasterRepeatedStartWithRxSize()
1266 uint32_t mctrlReg = base->MCTRL; in I3C_MasterEmitRequest()
1277 base->MCTRL = mctrlReg; in I3C_MasterEmitRequest()
1414 base->MCTRL |= I3C_MCTRL_RDTERM(1U); in I3C_MasterReceive()
1645 …base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK… in I3C_MasterProcessDAASpecifiedBaudrate()
2129 base->MCTRL |= I3C_MCTRL_RDTERM(1UL); in I3C_TransferStateMachineTransferDataState()
2330 base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes); in I3C_InitTransferStateMachine()
2375 base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; in I3C_MasterTransferNonBlocking()
[all …]
Dfsl_i3c.h1217 uint32_t ctrlVal = base->MCTRL; in I3C_MasterEmitIBIResponse()
1220 base->MCTRL = ctrlVal; in I3C_MasterEmitIBIResponse()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_I3C.h106 __IO uint32_t MCTRL; /**< Master Control, offset: 0x84 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h20822 __IO uint32_t MCTRL; /**< Master Main Control, offset: 0x84 */ member
33565 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h20822 __IO uint32_t MCTRL; /**< Master Main Control, offset: 0x84 */ member
33565 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV56F24/
DMKV56F24.h19954 __IO uint16_t MCTRL; /**< Master Control Register 0, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV58F24/
DMKV58F24.h21720 __IO uint16_t MCTRL; /**< Master Control Register 0, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h25623 __IO uint32_t MCTRL; /**< Master Main Control, offset: 0x84 */ member
41755 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h10493 …__IO uint32_t MCTRL; /**< Master Main Control Register, offset: 0x84 */ member
DMIMXRT685S_cm33.h17377 …__IO uint32_t MCTRL; /**< Master Main Control Register, offset: 0x84 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h27773 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h25082 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h17377 …__IO uint32_t MCTRL; /**< Master Main Control Register, offset: 0x84 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h19793 …__IO uint32_t MCTRL; /**< Master Main Control Register, offset: 0x84 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h31960 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h31943 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h34912 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h33334 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h26748 …__IO uint32_t MCTRL; /**< Master Main Control Register, offset: 0x84 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h36041 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h35665 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h36763 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h38300 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member

12