MCG_C5_PLLREFSEL0_VAL (reference) in projects: hal_nxp-3.5.0

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Searched refs:MCG_C5_PLLREFSEL0_VAL (Results 1 – 25 of 33) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV11Z7/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV10Z1287/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV10Z7/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKW41Z4/drivers/
D	fsl_clock.c	`108 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM33ZA5/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro 401 return *pllExtClkFreq[MCG_C5_PLLREFSEL0_VAL]; in CLOCK_GetPll0RefFreq()`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM14ZA5/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro 401 return *pllExtClkFreq[MCG_C5_PLLREFSEL0_VAL]; in CLOCK_GetPll0RefFreq()`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV31F12810/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV30F12810/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK02F12810/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK22F12810/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKL25Z4/drivers/
D	fsl_clock.c	`80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKW22D5/drivers/
D	fsl_clock.c	`80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKW24D5/drivers/
D	fsl_clock.c	`80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV56F24/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV58F24/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV31F51212/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKV31F25612/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM34Z7/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM35Z7/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM34ZA5/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK22F25612/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK24F12/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK22F12/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK80F25615/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK82F25615/drivers/
D	fsl_clock.c	`62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) macro`

TraceRecorderSource-2.7.6
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Zephyr-Core-3.5.0
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