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Searched refs:LPCG_TUPLE_RSRC (Results 1 – 25 of 30) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
Dfsl_clock.h255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
Dfsl_clock.c63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt()
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock()
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_clock.c77 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExtMapped()
117 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClockMapped()
143 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq()
167 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()

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