1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_LINFLEXD.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_LINFLEXD 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_LINFLEXD_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_LINFLEXD_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LINFLEXD Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LINFLEXD_Peripheral_Access_Layer LINFLEXD Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LINFLEXD - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t LINCR1; /**< LIN Control Register 1, offset: 0x0 */ 74 __IO uint32_t LINIER; /**< LIN Interrupt Enable Register, offset: 0x4 */ 75 __IO uint32_t LINSR; /**< LIN Status Register, offset: 0x8 */ 76 __IO uint32_t LINESR; /**< LIN Error Status Register, offset: 0xC */ 77 __IO uint32_t UARTCR; /**< UART Mode Control Register, offset: 0x10 */ 78 __IO uint32_t UARTSR; /**< UART Mode Status Register, offset: 0x14 */ 79 __IO uint32_t LINTCSR; /**< LIN Time-Out Control Status Register, offset: 0x18 */ 80 __IO uint32_t LINOCR; /**< LIN Output Compare Register, offset: 0x1C */ 81 __IO uint32_t LINTOCR; /**< LIN Time-Out Control Register, offset: 0x20 */ 82 __IO uint32_t LINFBRR; /**< LIN Fractional Baud Rate Register, offset: 0x24 */ 83 __IO uint32_t LINIBRR; /**< LIN Integer Baud Rate Register, offset: 0x28 */ 84 __IO uint32_t LINCFR; /**< LIN Checksum Field Register, offset: 0x2C */ 85 __IO uint32_t LINCR2; /**< LIN Control Register 2, offset: 0x30 */ 86 __IO uint32_t BIDR; /**< Buffer Identifier Register, offset: 0x34 */ 87 __IO uint32_t BDRL; /**< Buffer Data Register Least Significant, offset: 0x38 */ 88 __IO uint32_t BDRM; /**< Buffer Data Register Most Significant, offset: 0x3C */ 89 uint8_t RESERVED_0[12]; 90 __IO uint32_t GCR; /**< Global Control Register, offset: 0x4C */ 91 __IO uint32_t UARTPTO; /**< UART Preset Timeout Register, offset: 0x50 */ 92 __I uint32_t UARTCTO; /**< UART Current Timeout Register, offset: 0x54 */ 93 __IO uint32_t DMATXE; /**< DMA Tx Enable Register, offset: 0x58 */ 94 __IO uint32_t DMARXE; /**< DMA Rx Enable Register, offset: 0x5C */ 95 } LINFLEXD_Type, *LINFLEXD_MemMapPtr; 96 97 /** Number of instances of the LINFLEXD module. */ 98 #define LINFLEXD_INSTANCE_COUNT (13u) 99 100 /* LINFLEXD - Peripheral instance base addresses */ 101 /** Peripheral LINFLEX_0 base address */ 102 #define IP_LINFLEX_0_BASE (0x40170000u) 103 /** Peripheral LINFLEX_0 base pointer */ 104 #define IP_LINFLEX_0 ((LINFLEXD_Type *)IP_LINFLEX_0_BASE) 105 /** Peripheral LINFLEX_1 base address */ 106 #define IP_LINFLEX_1_BASE (0x40180000u) 107 /** Peripheral LINFLEX_1 base pointer */ 108 #define IP_LINFLEX_1 ((LINFLEXD_Type *)IP_LINFLEX_1_BASE) 109 /** Peripheral LINFLEX_2 base address */ 110 #define IP_LINFLEX_2_BASE (0x40190000u) 111 /** Peripheral LINFLEX_2 base pointer */ 112 #define IP_LINFLEX_2 ((LINFLEXD_Type *)IP_LINFLEX_2_BASE) 113 /** Peripheral LINFLEX_3 base address */ 114 #define IP_LINFLEX_3_BASE (0x40970000u) 115 /** Peripheral LINFLEX_3 base pointer */ 116 #define IP_LINFLEX_3 ((LINFLEXD_Type *)IP_LINFLEX_3_BASE) 117 /** Peripheral LINFLEX_4 base address */ 118 #define IP_LINFLEX_4_BASE (0x40980000u) 119 /** Peripheral LINFLEX_4 base pointer */ 120 #define IP_LINFLEX_4 ((LINFLEXD_Type *)IP_LINFLEX_4_BASE) 121 /** Peripheral LINFLEX_5 base address */ 122 #define IP_LINFLEX_5_BASE (0x40990000u) 123 /** Peripheral LINFLEX_5 base pointer */ 124 #define IP_LINFLEX_5 ((LINFLEXD_Type *)IP_LINFLEX_5_BASE) 125 /** Peripheral LINFLEX_6 base address */ 126 #define IP_LINFLEX_6_BASE (0x42170000u) 127 /** Peripheral LINFLEX_6 base pointer */ 128 #define IP_LINFLEX_6 ((LINFLEXD_Type *)IP_LINFLEX_6_BASE) 129 /** Peripheral LINFLEX_7 base address */ 130 #define IP_LINFLEX_7_BASE (0x42180000u) 131 /** Peripheral LINFLEX_7 base pointer */ 132 #define IP_LINFLEX_7 ((LINFLEXD_Type *)IP_LINFLEX_7_BASE) 133 /** Peripheral LINFLEX_8 base address */ 134 #define IP_LINFLEX_8_BASE (0x42190000u) 135 /** Peripheral LINFLEX_8 base pointer */ 136 #define IP_LINFLEX_8 ((LINFLEXD_Type *)IP_LINFLEX_8_BASE) 137 /** Peripheral LINFLEX_9 base address */ 138 #define IP_LINFLEX_9_BASE (0x42980000u) 139 /** Peripheral LINFLEX_9 base pointer */ 140 #define IP_LINFLEX_9 ((LINFLEXD_Type *)IP_LINFLEX_9_BASE) 141 /** Peripheral LINFLEX_10 base address */ 142 #define IP_LINFLEX_10_BASE (0x42990000u) 143 /** Peripheral LINFLEX_10 base pointer */ 144 #define IP_LINFLEX_10 ((LINFLEXD_Type *)IP_LINFLEX_10_BASE) 145 /** Peripheral LINFLEX_11 base address */ 146 #define IP_LINFLEX_11_BASE (0x429A0000u) 147 /** Peripheral LINFLEX_11 base pointer */ 148 #define IP_LINFLEX_11 ((LINFLEXD_Type *)IP_LINFLEX_11_BASE) 149 /** Peripheral MSC_0_LIN base address */ 150 #define IP_MSC_0_LIN_BASE (0x40330000u) 151 /** Peripheral MSC_0_LIN base pointer */ 152 #define IP_MSC_0_LIN ((LINFLEXD_Type *)IP_MSC_0_LIN_BASE) 153 /** Array initializer of LINFLEXD peripheral base addresses */ 154 #define IP_LINFLEXD_BASE_ADDRS { IP_LINFLEX_0_BASE, IP_LINFLEX_1_BASE, IP_LINFLEX_2_BASE, IP_LINFLEX_3_BASE, IP_LINFLEX_4_BASE, IP_LINFLEX_5_BASE, IP_LINFLEX_6_BASE, IP_LINFLEX_7_BASE, IP_LINFLEX_8_BASE, IP_LINFLEX_9_BASE, IP_LINFLEX_10_BASE, IP_LINFLEX_11_BASE, IP_MSC_0_LIN_BASE } 155 /** Array initializer of LINFLEXD peripheral base pointers */ 156 #define IP_LINFLEXD_BASE_PTRS { IP_LINFLEX_0, IP_LINFLEX_1, IP_LINFLEX_2, IP_LINFLEX_3, IP_LINFLEX_4, IP_LINFLEX_5, IP_LINFLEX_6, IP_LINFLEX_7, IP_LINFLEX_8, IP_LINFLEX_9, IP_LINFLEX_10, IP_LINFLEX_11, IP_MSC_0_LIN } 157 158 /* ---------------------------------------------------------------------------- 159 -- LINFLEXD Register Masks 160 ---------------------------------------------------------------------------- */ 161 162 /*! 163 * @addtogroup LINFLEXD_Register_Masks LINFLEXD Register Masks 164 * @{ 165 */ 166 167 /*! @name LINCR1 - LIN Control Register 1 */ 168 /*! @{ */ 169 170 #define LINFLEXD_LINCR1_INIT_MASK (0x1U) 171 #define LINFLEXD_LINCR1_INIT_SHIFT (0U) 172 #define LINFLEXD_LINCR1_INIT_WIDTH (1U) 173 #define LINFLEXD_LINCR1_INIT(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_INIT_SHIFT)) & LINFLEXD_LINCR1_INIT_MASK) 174 175 #define LINFLEXD_LINCR1_SLEEP_MASK (0x2U) 176 #define LINFLEXD_LINCR1_SLEEP_SHIFT (1U) 177 #define LINFLEXD_LINCR1_SLEEP_WIDTH (1U) 178 #define LINFLEXD_LINCR1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_SLEEP_SHIFT)) & LINFLEXD_LINCR1_SLEEP_MASK) 179 180 #define LINFLEXD_LINCR1_RBLM_MASK (0x4U) 181 #define LINFLEXD_LINCR1_RBLM_SHIFT (2U) 182 #define LINFLEXD_LINCR1_RBLM_WIDTH (1U) 183 #define LINFLEXD_LINCR1_RBLM(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_RBLM_SHIFT)) & LINFLEXD_LINCR1_RBLM_MASK) 184 185 #define LINFLEXD_LINCR1_SSBL_MASK (0x8U) 186 #define LINFLEXD_LINCR1_SSBL_SHIFT (3U) 187 #define LINFLEXD_LINCR1_SSBL_WIDTH (1U) 188 #define LINFLEXD_LINCR1_SSBL(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_SSBL_SHIFT)) & LINFLEXD_LINCR1_SSBL_MASK) 189 190 #define LINFLEXD_LINCR1_MME_MASK (0x10U) 191 #define LINFLEXD_LINCR1_MME_SHIFT (4U) 192 #define LINFLEXD_LINCR1_MME_WIDTH (1U) 193 #define LINFLEXD_LINCR1_MME(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_MME_SHIFT)) & LINFLEXD_LINCR1_MME_MASK) 194 195 #define LINFLEXD_LINCR1_LBKM_MASK (0x20U) 196 #define LINFLEXD_LINCR1_LBKM_SHIFT (5U) 197 #define LINFLEXD_LINCR1_LBKM_WIDTH (1U) 198 #define LINFLEXD_LINCR1_LBKM(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_LBKM_SHIFT)) & LINFLEXD_LINCR1_LBKM_MASK) 199 200 #define LINFLEXD_LINCR1_MBL_MASK (0xF00U) 201 #define LINFLEXD_LINCR1_MBL_SHIFT (8U) 202 #define LINFLEXD_LINCR1_MBL_WIDTH (4U) 203 #define LINFLEXD_LINCR1_MBL(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_MBL_SHIFT)) & LINFLEXD_LINCR1_MBL_MASK) 204 205 #define LINFLEXD_LINCR1_AUTOWU_MASK (0x1000U) 206 #define LINFLEXD_LINCR1_AUTOWU_SHIFT (12U) 207 #define LINFLEXD_LINCR1_AUTOWU_WIDTH (1U) 208 #define LINFLEXD_LINCR1_AUTOWU(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_AUTOWU_SHIFT)) & LINFLEXD_LINCR1_AUTOWU_MASK) 209 210 #define LINFLEXD_LINCR1_CFD_MASK (0x4000U) 211 #define LINFLEXD_LINCR1_CFD_SHIFT (14U) 212 #define LINFLEXD_LINCR1_CFD_WIDTH (1U) 213 #define LINFLEXD_LINCR1_CFD(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_CFD_SHIFT)) & LINFLEXD_LINCR1_CFD_MASK) 214 215 #define LINFLEXD_LINCR1_CCD_MASK (0x8000U) 216 #define LINFLEXD_LINCR1_CCD_SHIFT (15U) 217 #define LINFLEXD_LINCR1_CCD_WIDTH (1U) 218 #define LINFLEXD_LINCR1_CCD(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_CCD_SHIFT)) & LINFLEXD_LINCR1_CCD_MASK) 219 220 #define LINFLEXD_LINCR1_NLSE_MASK (0x10000U) 221 #define LINFLEXD_LINCR1_NLSE_SHIFT (16U) 222 #define LINFLEXD_LINCR1_NLSE_WIDTH (1U) 223 #define LINFLEXD_LINCR1_NLSE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR1_NLSE_SHIFT)) & LINFLEXD_LINCR1_NLSE_MASK) 224 /*! @} */ 225 226 /*! @name LINIER - LIN Interrupt Enable Register */ 227 /*! @{ */ 228 229 #define LINFLEXD_LINIER_HRIE_MASK (0x1U) 230 #define LINFLEXD_LINIER_HRIE_SHIFT (0U) 231 #define LINFLEXD_LINIER_HRIE_WIDTH (1U) 232 #define LINFLEXD_LINIER_HRIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_HRIE_SHIFT)) & LINFLEXD_LINIER_HRIE_MASK) 233 234 #define LINFLEXD_LINIER_DTIE_MASK (0x2U) 235 #define LINFLEXD_LINIER_DTIE_SHIFT (1U) 236 #define LINFLEXD_LINIER_DTIE_WIDTH (1U) 237 #define LINFLEXD_LINIER_DTIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_DTIE_SHIFT)) & LINFLEXD_LINIER_DTIE_MASK) 238 239 #define LINFLEXD_LINIER_DRIE_MASK (0x4U) 240 #define LINFLEXD_LINIER_DRIE_SHIFT (2U) 241 #define LINFLEXD_LINIER_DRIE_WIDTH (1U) 242 #define LINFLEXD_LINIER_DRIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_DRIE_SHIFT)) & LINFLEXD_LINIER_DRIE_MASK) 243 244 #define LINFLEXD_LINIER_TOIE_MASK (0x8U) 245 #define LINFLEXD_LINIER_TOIE_SHIFT (3U) 246 #define LINFLEXD_LINIER_TOIE_WIDTH (1U) 247 #define LINFLEXD_LINIER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_TOIE_SHIFT)) & LINFLEXD_LINIER_TOIE_MASK) 248 249 #define LINFLEXD_LINIER_WUIE_MASK (0x20U) 250 #define LINFLEXD_LINIER_WUIE_SHIFT (5U) 251 #define LINFLEXD_LINIER_WUIE_WIDTH (1U) 252 #define LINFLEXD_LINIER_WUIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_WUIE_SHIFT)) & LINFLEXD_LINIER_WUIE_MASK) 253 254 #define LINFLEXD_LINIER_LSIE_MASK (0x40U) 255 #define LINFLEXD_LINIER_LSIE_SHIFT (6U) 256 #define LINFLEXD_LINIER_LSIE_WIDTH (1U) 257 #define LINFLEXD_LINIER_LSIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_LSIE_SHIFT)) & LINFLEXD_LINIER_LSIE_MASK) 258 259 #define LINFLEXD_LINIER_BOIE_MASK (0x80U) 260 #define LINFLEXD_LINIER_BOIE_SHIFT (7U) 261 #define LINFLEXD_LINIER_BOIE_WIDTH (1U) 262 #define LINFLEXD_LINIER_BOIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_BOIE_SHIFT)) & LINFLEXD_LINIER_BOIE_MASK) 263 264 #define LINFLEXD_LINIER_FEIE_MASK (0x100U) 265 #define LINFLEXD_LINIER_FEIE_SHIFT (8U) 266 #define LINFLEXD_LINIER_FEIE_WIDTH (1U) 267 #define LINFLEXD_LINIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_FEIE_SHIFT)) & LINFLEXD_LINIER_FEIE_MASK) 268 269 #define LINFLEXD_LINIER_HEIE_MASK (0x800U) 270 #define LINFLEXD_LINIER_HEIE_SHIFT (11U) 271 #define LINFLEXD_LINIER_HEIE_WIDTH (1U) 272 #define LINFLEXD_LINIER_HEIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_HEIE_SHIFT)) & LINFLEXD_LINIER_HEIE_MASK) 273 274 #define LINFLEXD_LINIER_CEIE_MASK (0x1000U) 275 #define LINFLEXD_LINIER_CEIE_SHIFT (12U) 276 #define LINFLEXD_LINIER_CEIE_WIDTH (1U) 277 #define LINFLEXD_LINIER_CEIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_CEIE_SHIFT)) & LINFLEXD_LINIER_CEIE_MASK) 278 279 #define LINFLEXD_LINIER_BEIE_MASK (0x2000U) 280 #define LINFLEXD_LINIER_BEIE_SHIFT (13U) 281 #define LINFLEXD_LINIER_BEIE_WIDTH (1U) 282 #define LINFLEXD_LINIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_BEIE_SHIFT)) & LINFLEXD_LINIER_BEIE_MASK) 283 284 #define LINFLEXD_LINIER_OCIE_MASK (0x4000U) 285 #define LINFLEXD_LINIER_OCIE_SHIFT (14U) 286 #define LINFLEXD_LINIER_OCIE_WIDTH (1U) 287 #define LINFLEXD_LINIER_OCIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_OCIE_SHIFT)) & LINFLEXD_LINIER_OCIE_MASK) 288 289 #define LINFLEXD_LINIER_SZIE_MASK (0x8000U) 290 #define LINFLEXD_LINIER_SZIE_SHIFT (15U) 291 #define LINFLEXD_LINIER_SZIE_WIDTH (1U) 292 #define LINFLEXD_LINIER_SZIE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIER_SZIE_SHIFT)) & LINFLEXD_LINIER_SZIE_MASK) 293 /*! @} */ 294 295 /*! @name LINSR - LIN Status Register */ 296 /*! @{ */ 297 298 #define LINFLEXD_LINSR_HRF_MASK (0x1U) 299 #define LINFLEXD_LINSR_HRF_SHIFT (0U) 300 #define LINFLEXD_LINSR_HRF_WIDTH (1U) 301 #define LINFLEXD_LINSR_HRF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_HRF_SHIFT)) & LINFLEXD_LINSR_HRF_MASK) 302 303 #define LINFLEXD_LINSR_DTF_MASK (0x2U) 304 #define LINFLEXD_LINSR_DTF_SHIFT (1U) 305 #define LINFLEXD_LINSR_DTF_WIDTH (1U) 306 #define LINFLEXD_LINSR_DTF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_DTF_SHIFT)) & LINFLEXD_LINSR_DTF_MASK) 307 308 #define LINFLEXD_LINSR_DRF_MASK (0x4U) 309 #define LINFLEXD_LINSR_DRF_SHIFT (2U) 310 #define LINFLEXD_LINSR_DRF_WIDTH (1U) 311 #define LINFLEXD_LINSR_DRF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_DRF_SHIFT)) & LINFLEXD_LINSR_DRF_MASK) 312 313 #define LINFLEXD_LINSR_WUF_MASK (0x20U) 314 #define LINFLEXD_LINSR_WUF_SHIFT (5U) 315 #define LINFLEXD_LINSR_WUF_WIDTH (1U) 316 #define LINFLEXD_LINSR_WUF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_WUF_SHIFT)) & LINFLEXD_LINSR_WUF_MASK) 317 318 #define LINFLEXD_LINSR_RDI_MASK (0x40U) 319 #define LINFLEXD_LINSR_RDI_SHIFT (6U) 320 #define LINFLEXD_LINSR_RDI_WIDTH (1U) 321 #define LINFLEXD_LINSR_RDI(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_RDI_SHIFT)) & LINFLEXD_LINSR_RDI_MASK) 322 323 #define LINFLEXD_LINSR_RXBUSY_MASK (0x80U) 324 #define LINFLEXD_LINSR_RXBUSY_SHIFT (7U) 325 #define LINFLEXD_LINSR_RXBUSY_WIDTH (1U) 326 #define LINFLEXD_LINSR_RXBUSY(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_RXBUSY_SHIFT)) & LINFLEXD_LINSR_RXBUSY_MASK) 327 328 #define LINFLEXD_LINSR_DRBNE_MASK (0x100U) 329 #define LINFLEXD_LINSR_DRBNE_SHIFT (8U) 330 #define LINFLEXD_LINSR_DRBNE_WIDTH (1U) 331 #define LINFLEXD_LINSR_DRBNE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_DRBNE_SHIFT)) & LINFLEXD_LINSR_DRBNE_MASK) 332 333 #define LINFLEXD_LINSR_RMB_MASK (0x200U) 334 #define LINFLEXD_LINSR_RMB_SHIFT (9U) 335 #define LINFLEXD_LINSR_RMB_WIDTH (1U) 336 #define LINFLEXD_LINSR_RMB(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_RMB_SHIFT)) & LINFLEXD_LINSR_RMB_MASK) 337 338 #define LINFLEXD_LINSR_LINS_MASK (0xF000U) 339 #define LINFLEXD_LINSR_LINS_SHIFT (12U) 340 #define LINFLEXD_LINSR_LINS_WIDTH (4U) 341 #define LINFLEXD_LINSR_LINS(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_LINS_SHIFT)) & LINFLEXD_LINSR_LINS_MASK) 342 343 #define LINFLEXD_LINSR_RDC_MASK (0x70000U) 344 #define LINFLEXD_LINSR_RDC_SHIFT (16U) 345 #define LINFLEXD_LINSR_RDC_WIDTH (3U) 346 #define LINFLEXD_LINSR_RDC(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINSR_RDC_SHIFT)) & LINFLEXD_LINSR_RDC_MASK) 347 /*! @} */ 348 349 /*! @name LINESR - LIN Error Status Register */ 350 /*! @{ */ 351 352 #define LINFLEXD_LINESR_NF_MASK (0x1U) 353 #define LINFLEXD_LINESR_NF_SHIFT (0U) 354 #define LINFLEXD_LINESR_NF_WIDTH (1U) 355 #define LINFLEXD_LINESR_NF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_NF_SHIFT)) & LINFLEXD_LINESR_NF_MASK) 356 357 #define LINFLEXD_LINESR_BOF_MASK (0x80U) 358 #define LINFLEXD_LINESR_BOF_SHIFT (7U) 359 #define LINFLEXD_LINESR_BOF_WIDTH (1U) 360 #define LINFLEXD_LINESR_BOF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_BOF_SHIFT)) & LINFLEXD_LINESR_BOF_MASK) 361 362 #define LINFLEXD_LINESR_FEF_MASK (0x100U) 363 #define LINFLEXD_LINESR_FEF_SHIFT (8U) 364 #define LINFLEXD_LINESR_FEF_WIDTH (1U) 365 #define LINFLEXD_LINESR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_FEF_SHIFT)) & LINFLEXD_LINESR_FEF_MASK) 366 367 #define LINFLEXD_LINESR_IDPEF_MASK (0x200U) 368 #define LINFLEXD_LINESR_IDPEF_SHIFT (9U) 369 #define LINFLEXD_LINESR_IDPEF_WIDTH (1U) 370 #define LINFLEXD_LINESR_IDPEF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_IDPEF_SHIFT)) & LINFLEXD_LINESR_IDPEF_MASK) 371 372 #define LINFLEXD_LINESR_SDEF_MASK (0x400U) 373 #define LINFLEXD_LINESR_SDEF_SHIFT (10U) 374 #define LINFLEXD_LINESR_SDEF_WIDTH (1U) 375 #define LINFLEXD_LINESR_SDEF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_SDEF_SHIFT)) & LINFLEXD_LINESR_SDEF_MASK) 376 377 #define LINFLEXD_LINESR_SFEF_MASK (0x800U) 378 #define LINFLEXD_LINESR_SFEF_SHIFT (11U) 379 #define LINFLEXD_LINESR_SFEF_WIDTH (1U) 380 #define LINFLEXD_LINESR_SFEF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_SFEF_SHIFT)) & LINFLEXD_LINESR_SFEF_MASK) 381 382 #define LINFLEXD_LINESR_CEF_MASK (0x1000U) 383 #define LINFLEXD_LINESR_CEF_SHIFT (12U) 384 #define LINFLEXD_LINESR_CEF_WIDTH (1U) 385 #define LINFLEXD_LINESR_CEF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_CEF_SHIFT)) & LINFLEXD_LINESR_CEF_MASK) 386 387 #define LINFLEXD_LINESR_BEF_MASK (0x2000U) 388 #define LINFLEXD_LINESR_BEF_SHIFT (13U) 389 #define LINFLEXD_LINESR_BEF_WIDTH (1U) 390 #define LINFLEXD_LINESR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_BEF_SHIFT)) & LINFLEXD_LINESR_BEF_MASK) 391 392 #define LINFLEXD_LINESR_OCF_MASK (0x4000U) 393 #define LINFLEXD_LINESR_OCF_SHIFT (14U) 394 #define LINFLEXD_LINESR_OCF_WIDTH (1U) 395 #define LINFLEXD_LINESR_OCF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_OCF_SHIFT)) & LINFLEXD_LINESR_OCF_MASK) 396 397 #define LINFLEXD_LINESR_SZF_MASK (0x8000U) 398 #define LINFLEXD_LINESR_SZF_SHIFT (15U) 399 #define LINFLEXD_LINESR_SZF_WIDTH (1U) 400 #define LINFLEXD_LINESR_SZF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINESR_SZF_SHIFT)) & LINFLEXD_LINESR_SZF_MASK) 401 /*! @} */ 402 403 /*! @name UARTCR - UART Mode Control Register */ 404 /*! @{ */ 405 406 #define LINFLEXD_UARTCR_UART_MASK (0x1U) 407 #define LINFLEXD_UARTCR_UART_SHIFT (0U) 408 #define LINFLEXD_UARTCR_UART_WIDTH (1U) 409 #define LINFLEXD_UARTCR_UART(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_UART_SHIFT)) & LINFLEXD_UARTCR_UART_MASK) 410 411 #define LINFLEXD_UARTCR_WL0_MASK (0x2U) 412 #define LINFLEXD_UARTCR_WL0_SHIFT (1U) 413 #define LINFLEXD_UARTCR_WL0_WIDTH (1U) 414 #define LINFLEXD_UARTCR_WL0(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_WL0_SHIFT)) & LINFLEXD_UARTCR_WL0_MASK) 415 416 #define LINFLEXD_UARTCR_PCE_MASK (0x4U) 417 #define LINFLEXD_UARTCR_PCE_SHIFT (2U) 418 #define LINFLEXD_UARTCR_PCE_WIDTH (1U) 419 #define LINFLEXD_UARTCR_PCE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_PCE_SHIFT)) & LINFLEXD_UARTCR_PCE_MASK) 420 421 #define LINFLEXD_UARTCR_PC0_MASK (0x8U) 422 #define LINFLEXD_UARTCR_PC0_SHIFT (3U) 423 #define LINFLEXD_UARTCR_PC0_WIDTH (1U) 424 #define LINFLEXD_UARTCR_PC0(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_PC0_SHIFT)) & LINFLEXD_UARTCR_PC0_MASK) 425 426 #define LINFLEXD_UARTCR_TxEn_MASK (0x10U) 427 #define LINFLEXD_UARTCR_TxEn_SHIFT (4U) 428 #define LINFLEXD_UARTCR_TxEn_WIDTH (1U) 429 #define LINFLEXD_UARTCR_TxEn(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_TxEn_SHIFT)) & LINFLEXD_UARTCR_TxEn_MASK) 430 431 #define LINFLEXD_UARTCR_RxEn_MASK (0x20U) 432 #define LINFLEXD_UARTCR_RxEn_SHIFT (5U) 433 #define LINFLEXD_UARTCR_RxEn_WIDTH (1U) 434 #define LINFLEXD_UARTCR_RxEn(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_RxEn_SHIFT)) & LINFLEXD_UARTCR_RxEn_MASK) 435 436 #define LINFLEXD_UARTCR_PC1_MASK (0x40U) 437 #define LINFLEXD_UARTCR_PC1_SHIFT (6U) 438 #define LINFLEXD_UARTCR_PC1_WIDTH (1U) 439 #define LINFLEXD_UARTCR_PC1(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_PC1_SHIFT)) & LINFLEXD_UARTCR_PC1_MASK) 440 441 #define LINFLEXD_UARTCR_WL1_MASK (0x80U) 442 #define LINFLEXD_UARTCR_WL1_SHIFT (7U) 443 #define LINFLEXD_UARTCR_WL1_WIDTH (1U) 444 #define LINFLEXD_UARTCR_WL1(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_WL1_SHIFT)) & LINFLEXD_UARTCR_WL1_MASK) 445 446 #define LINFLEXD_UARTCR_TFBM_MASK (0x100U) 447 #define LINFLEXD_UARTCR_TFBM_SHIFT (8U) 448 #define LINFLEXD_UARTCR_TFBM_WIDTH (1U) 449 #define LINFLEXD_UARTCR_TFBM(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_TFBM_SHIFT)) & LINFLEXD_UARTCR_TFBM_MASK) 450 451 #define LINFLEXD_UARTCR_RFBM_MASK (0x200U) 452 #define LINFLEXD_UARTCR_RFBM_SHIFT (9U) 453 #define LINFLEXD_UARTCR_RFBM_WIDTH (1U) 454 #define LINFLEXD_UARTCR_RFBM(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_RFBM_SHIFT)) & LINFLEXD_UARTCR_RFBM_MASK) 455 456 #define LINFLEXD_UARTCR_RDFL_RFC_MASK (0x1C00U) 457 #define LINFLEXD_UARTCR_RDFL_RFC_SHIFT (10U) 458 #define LINFLEXD_UARTCR_RDFL_RFC_WIDTH (3U) 459 #define LINFLEXD_UARTCR_RDFL_RFC(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_RDFL_RFC_SHIFT)) & LINFLEXD_UARTCR_RDFL_RFC_MASK) 460 461 #define LINFLEXD_UARTCR_TDFL_TFC_MASK (0xE000U) 462 #define LINFLEXD_UARTCR_TDFL_TFC_SHIFT (13U) 463 #define LINFLEXD_UARTCR_TDFL_TFC_WIDTH (3U) 464 #define LINFLEXD_UARTCR_TDFL_TFC(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_TDFL_TFC_SHIFT)) & LINFLEXD_UARTCR_TDFL_TFC_MASK) 465 466 #define LINFLEXD_UARTCR_WLS_MASK (0x10000U) 467 #define LINFLEXD_UARTCR_WLS_SHIFT (16U) 468 #define LINFLEXD_UARTCR_WLS_WIDTH (1U) 469 #define LINFLEXD_UARTCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_WLS_SHIFT)) & LINFLEXD_UARTCR_WLS_MASK) 470 471 #define LINFLEXD_UARTCR_SBUR_MASK (0x60000U) 472 #define LINFLEXD_UARTCR_SBUR_SHIFT (17U) 473 #define LINFLEXD_UARTCR_SBUR_WIDTH (2U) 474 #define LINFLEXD_UARTCR_SBUR(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_SBUR_SHIFT)) & LINFLEXD_UARTCR_SBUR_MASK) 475 476 #define LINFLEXD_UARTCR_DTU_PCETX_MASK (0x80000U) 477 #define LINFLEXD_UARTCR_DTU_PCETX_SHIFT (19U) 478 #define LINFLEXD_UARTCR_DTU_PCETX_WIDTH (1U) 479 #define LINFLEXD_UARTCR_DTU_PCETX(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_DTU_PCETX_SHIFT)) & LINFLEXD_UARTCR_DTU_PCETX_MASK) 480 481 #define LINFLEXD_UARTCR_NEF_MASK (0x700000U) 482 #define LINFLEXD_UARTCR_NEF_SHIFT (20U) 483 #define LINFLEXD_UARTCR_NEF_WIDTH (3U) 484 #define LINFLEXD_UARTCR_NEF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_NEF_SHIFT)) & LINFLEXD_UARTCR_NEF_MASK) 485 486 #define LINFLEXD_UARTCR_ROSE_MASK (0x800000U) 487 #define LINFLEXD_UARTCR_ROSE_SHIFT (23U) 488 #define LINFLEXD_UARTCR_ROSE_WIDTH (1U) 489 #define LINFLEXD_UARTCR_ROSE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_ROSE_SHIFT)) & LINFLEXD_UARTCR_ROSE_MASK) 490 491 #define LINFLEXD_UARTCR_OSR_MASK (0xF000000U) 492 #define LINFLEXD_UARTCR_OSR_SHIFT (24U) 493 #define LINFLEXD_UARTCR_OSR_WIDTH (4U) 494 #define LINFLEXD_UARTCR_OSR(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_OSR_SHIFT)) & LINFLEXD_UARTCR_OSR_MASK) 495 496 #define LINFLEXD_UARTCR_CSP_MASK (0x70000000U) 497 #define LINFLEXD_UARTCR_CSP_SHIFT (28U) 498 #define LINFLEXD_UARTCR_CSP_WIDTH (3U) 499 #define LINFLEXD_UARTCR_CSP(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_CSP_SHIFT)) & LINFLEXD_UARTCR_CSP_MASK) 500 501 #define LINFLEXD_UARTCR_MIS_MASK (0x80000000U) 502 #define LINFLEXD_UARTCR_MIS_SHIFT (31U) 503 #define LINFLEXD_UARTCR_MIS_WIDTH (1U) 504 #define LINFLEXD_UARTCR_MIS(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCR_MIS_SHIFT)) & LINFLEXD_UARTCR_MIS_MASK) 505 /*! @} */ 506 507 /*! @name UARTSR - UART Mode Status Register */ 508 /*! @{ */ 509 510 #define LINFLEXD_UARTSR_NF_MASK (0x1U) 511 #define LINFLEXD_UARTSR_NF_SHIFT (0U) 512 #define LINFLEXD_UARTSR_NF_WIDTH (1U) 513 #define LINFLEXD_UARTSR_NF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_NF_SHIFT)) & LINFLEXD_UARTSR_NF_MASK) 514 515 #define LINFLEXD_UARTSR_DTFTFF_MASK (0x2U) 516 #define LINFLEXD_UARTSR_DTFTFF_SHIFT (1U) 517 #define LINFLEXD_UARTSR_DTFTFF_WIDTH (1U) 518 #define LINFLEXD_UARTSR_DTFTFF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_DTFTFF_SHIFT)) & LINFLEXD_UARTSR_DTFTFF_MASK) 519 520 #define LINFLEXD_UARTSR_DRFRFE_MASK (0x4U) 521 #define LINFLEXD_UARTSR_DRFRFE_SHIFT (2U) 522 #define LINFLEXD_UARTSR_DRFRFE_WIDTH (1U) 523 #define LINFLEXD_UARTSR_DRFRFE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_DRFRFE_SHIFT)) & LINFLEXD_UARTSR_DRFRFE_MASK) 524 525 #define LINFLEXD_UARTSR_TO_MASK (0x8U) 526 #define LINFLEXD_UARTSR_TO_SHIFT (3U) 527 #define LINFLEXD_UARTSR_TO_WIDTH (1U) 528 #define LINFLEXD_UARTSR_TO(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_TO_SHIFT)) & LINFLEXD_UARTSR_TO_MASK) 529 530 #define LINFLEXD_UARTSR_RFNE_MASK (0x10U) 531 #define LINFLEXD_UARTSR_RFNE_SHIFT (4U) 532 #define LINFLEXD_UARTSR_RFNE_WIDTH (1U) 533 #define LINFLEXD_UARTSR_RFNE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_RFNE_SHIFT)) & LINFLEXD_UARTSR_RFNE_MASK) 534 535 #define LINFLEXD_UARTSR_WUF_MASK (0x20U) 536 #define LINFLEXD_UARTSR_WUF_SHIFT (5U) 537 #define LINFLEXD_UARTSR_WUF_WIDTH (1U) 538 #define LINFLEXD_UARTSR_WUF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_WUF_SHIFT)) & LINFLEXD_UARTSR_WUF_MASK) 539 540 #define LINFLEXD_UARTSR_RDI_MASK (0x40U) 541 #define LINFLEXD_UARTSR_RDI_SHIFT (6U) 542 #define LINFLEXD_UARTSR_RDI_WIDTH (1U) 543 #define LINFLEXD_UARTSR_RDI(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_RDI_SHIFT)) & LINFLEXD_UARTSR_RDI_MASK) 544 545 #define LINFLEXD_UARTSR_BOF_MASK (0x80U) 546 #define LINFLEXD_UARTSR_BOF_SHIFT (7U) 547 #define LINFLEXD_UARTSR_BOF_WIDTH (1U) 548 #define LINFLEXD_UARTSR_BOF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_BOF_SHIFT)) & LINFLEXD_UARTSR_BOF_MASK) 549 550 #define LINFLEXD_UARTSR_FEF_MASK (0x100U) 551 #define LINFLEXD_UARTSR_FEF_SHIFT (8U) 552 #define LINFLEXD_UARTSR_FEF_WIDTH (1U) 553 #define LINFLEXD_UARTSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_FEF_SHIFT)) & LINFLEXD_UARTSR_FEF_MASK) 554 555 #define LINFLEXD_UARTSR_RMB_MASK (0x200U) 556 #define LINFLEXD_UARTSR_RMB_SHIFT (9U) 557 #define LINFLEXD_UARTSR_RMB_WIDTH (1U) 558 #define LINFLEXD_UARTSR_RMB(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_RMB_SHIFT)) & LINFLEXD_UARTSR_RMB_MASK) 559 560 #define LINFLEXD_UARTSR_PE_MASK (0x3C00U) 561 #define LINFLEXD_UARTSR_PE_SHIFT (10U) 562 #define LINFLEXD_UARTSR_PE_WIDTH (4U) 563 #define LINFLEXD_UARTSR_PE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_PE_SHIFT)) & LINFLEXD_UARTSR_PE_MASK) 564 565 #define LINFLEXD_UARTSR_OCF_MASK (0x4000U) 566 #define LINFLEXD_UARTSR_OCF_SHIFT (14U) 567 #define LINFLEXD_UARTSR_OCF_WIDTH (1U) 568 #define LINFLEXD_UARTSR_OCF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_OCF_SHIFT)) & LINFLEXD_UARTSR_OCF_MASK) 569 570 #define LINFLEXD_UARTSR_SZF_MASK (0x8000U) 571 #define LINFLEXD_UARTSR_SZF_SHIFT (15U) 572 #define LINFLEXD_UARTSR_SZF_WIDTH (1U) 573 #define LINFLEXD_UARTSR_SZF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTSR_SZF_SHIFT)) & LINFLEXD_UARTSR_SZF_MASK) 574 /*! @} */ 575 576 /*! @name LINTCSR - LIN Time-Out Control Status Register */ 577 /*! @{ */ 578 579 #define LINFLEXD_LINTCSR_CNT_MASK (0xFFU) 580 #define LINFLEXD_LINTCSR_CNT_SHIFT (0U) 581 #define LINFLEXD_LINTCSR_CNT_WIDTH (8U) 582 #define LINFLEXD_LINTCSR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINTCSR_CNT_SHIFT)) & LINFLEXD_LINTCSR_CNT_MASK) 583 584 #define LINFLEXD_LINTCSR_TOCE_MASK (0x100U) 585 #define LINFLEXD_LINTCSR_TOCE_SHIFT (8U) 586 #define LINFLEXD_LINTCSR_TOCE_WIDTH (1U) 587 #define LINFLEXD_LINTCSR_TOCE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINTCSR_TOCE_SHIFT)) & LINFLEXD_LINTCSR_TOCE_MASK) 588 589 #define LINFLEXD_LINTCSR_IOT_MASK (0x200U) 590 #define LINFLEXD_LINTCSR_IOT_SHIFT (9U) 591 #define LINFLEXD_LINTCSR_IOT_WIDTH (1U) 592 #define LINFLEXD_LINTCSR_IOT(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINTCSR_IOT_SHIFT)) & LINFLEXD_LINTCSR_IOT_MASK) 593 594 #define LINFLEXD_LINTCSR_MODE_MASK (0x400U) 595 #define LINFLEXD_LINTCSR_MODE_SHIFT (10U) 596 #define LINFLEXD_LINTCSR_MODE_WIDTH (1U) 597 #define LINFLEXD_LINTCSR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINTCSR_MODE_SHIFT)) & LINFLEXD_LINTCSR_MODE_MASK) 598 /*! @} */ 599 600 /*! @name LINOCR - LIN Output Compare Register */ 601 /*! @{ */ 602 603 #define LINFLEXD_LINOCR_OC1_MASK (0xFFU) 604 #define LINFLEXD_LINOCR_OC1_SHIFT (0U) 605 #define LINFLEXD_LINOCR_OC1_WIDTH (8U) 606 #define LINFLEXD_LINOCR_OC1(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINOCR_OC1_SHIFT)) & LINFLEXD_LINOCR_OC1_MASK) 607 608 #define LINFLEXD_LINOCR_OC2_MASK (0xFF00U) 609 #define LINFLEXD_LINOCR_OC2_SHIFT (8U) 610 #define LINFLEXD_LINOCR_OC2_WIDTH (8U) 611 #define LINFLEXD_LINOCR_OC2(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINOCR_OC2_SHIFT)) & LINFLEXD_LINOCR_OC2_MASK) 612 /*! @} */ 613 614 /*! @name LINTOCR - LIN Time-Out Control Register */ 615 /*! @{ */ 616 617 #define LINFLEXD_LINTOCR_HTO_MASK (0x7FU) 618 #define LINFLEXD_LINTOCR_HTO_SHIFT (0U) 619 #define LINFLEXD_LINTOCR_HTO_WIDTH (7U) 620 #define LINFLEXD_LINTOCR_HTO(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINTOCR_HTO_SHIFT)) & LINFLEXD_LINTOCR_HTO_MASK) 621 622 #define LINFLEXD_LINTOCR_RTO_MASK (0xF00U) 623 #define LINFLEXD_LINTOCR_RTO_SHIFT (8U) 624 #define LINFLEXD_LINTOCR_RTO_WIDTH (4U) 625 #define LINFLEXD_LINTOCR_RTO(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINTOCR_RTO_SHIFT)) & LINFLEXD_LINTOCR_RTO_MASK) 626 /*! @} */ 627 628 /*! @name LINFBRR - LIN Fractional Baud Rate Register */ 629 /*! @{ */ 630 631 #define LINFLEXD_LINFBRR_FBR_MASK (0xFU) 632 #define LINFLEXD_LINFBRR_FBR_SHIFT (0U) 633 #define LINFLEXD_LINFBRR_FBR_WIDTH (4U) 634 #define LINFLEXD_LINFBRR_FBR(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINFBRR_FBR_SHIFT)) & LINFLEXD_LINFBRR_FBR_MASK) 635 /*! @} */ 636 637 /*! @name LINIBRR - LIN Integer Baud Rate Register */ 638 /*! @{ */ 639 640 #define LINFLEXD_LINIBRR_IBR_MASK (0xFFFFFU) 641 #define LINFLEXD_LINIBRR_IBR_SHIFT (0U) 642 #define LINFLEXD_LINIBRR_IBR_WIDTH (20U) 643 #define LINFLEXD_LINIBRR_IBR(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINIBRR_IBR_SHIFT)) & LINFLEXD_LINIBRR_IBR_MASK) 644 /*! @} */ 645 646 /*! @name LINCFR - LIN Checksum Field Register */ 647 /*! @{ */ 648 649 #define LINFLEXD_LINCFR_CF_MASK (0xFFU) 650 #define LINFLEXD_LINCFR_CF_SHIFT (0U) 651 #define LINFLEXD_LINCFR_CF_WIDTH (8U) 652 #define LINFLEXD_LINCFR_CF(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCFR_CF_SHIFT)) & LINFLEXD_LINCFR_CF_MASK) 653 /*! @} */ 654 655 /*! @name LINCR2 - LIN Control Register 2 */ 656 /*! @{ */ 657 658 #define LINFLEXD_LINCR2_HTRQ_MASK (0x100U) 659 #define LINFLEXD_LINCR2_HTRQ_SHIFT (8U) 660 #define LINFLEXD_LINCR2_HTRQ_WIDTH (1U) 661 #define LINFLEXD_LINCR2_HTRQ(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR2_HTRQ_SHIFT)) & LINFLEXD_LINCR2_HTRQ_MASK) 662 663 #define LINFLEXD_LINCR2_ABRQ_MASK (0x200U) 664 #define LINFLEXD_LINCR2_ABRQ_SHIFT (9U) 665 #define LINFLEXD_LINCR2_ABRQ_WIDTH (1U) 666 #define LINFLEXD_LINCR2_ABRQ(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR2_ABRQ_SHIFT)) & LINFLEXD_LINCR2_ABRQ_MASK) 667 668 #define LINFLEXD_LINCR2_DTRQ_MASK (0x400U) 669 #define LINFLEXD_LINCR2_DTRQ_SHIFT (10U) 670 #define LINFLEXD_LINCR2_DTRQ_WIDTH (1U) 671 #define LINFLEXD_LINCR2_DTRQ(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR2_DTRQ_SHIFT)) & LINFLEXD_LINCR2_DTRQ_MASK) 672 673 #define LINFLEXD_LINCR2_DDRQ_MASK (0x800U) 674 #define LINFLEXD_LINCR2_DDRQ_SHIFT (11U) 675 #define LINFLEXD_LINCR2_DDRQ_WIDTH (1U) 676 #define LINFLEXD_LINCR2_DDRQ(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR2_DDRQ_SHIFT)) & LINFLEXD_LINCR2_DDRQ_MASK) 677 678 #define LINFLEXD_LINCR2_WURQ_MASK (0x1000U) 679 #define LINFLEXD_LINCR2_WURQ_SHIFT (12U) 680 #define LINFLEXD_LINCR2_WURQ_WIDTH (1U) 681 #define LINFLEXD_LINCR2_WURQ(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR2_WURQ_SHIFT)) & LINFLEXD_LINCR2_WURQ_MASK) 682 683 #define LINFLEXD_LINCR2_IOPE_MASK (0x2000U) 684 #define LINFLEXD_LINCR2_IOPE_SHIFT (13U) 685 #define LINFLEXD_LINCR2_IOPE_WIDTH (1U) 686 #define LINFLEXD_LINCR2_IOPE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR2_IOPE_SHIFT)) & LINFLEXD_LINCR2_IOPE_MASK) 687 688 #define LINFLEXD_LINCR2_IOBE_MASK (0x4000U) 689 #define LINFLEXD_LINCR2_IOBE_SHIFT (14U) 690 #define LINFLEXD_LINCR2_IOBE_WIDTH (1U) 691 #define LINFLEXD_LINCR2_IOBE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR2_IOBE_SHIFT)) & LINFLEXD_LINCR2_IOBE_MASK) 692 693 #define LINFLEXD_LINCR2_TBDE_MASK (0x8000U) 694 #define LINFLEXD_LINCR2_TBDE_SHIFT (15U) 695 #define LINFLEXD_LINCR2_TBDE_WIDTH (1U) 696 #define LINFLEXD_LINCR2_TBDE(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_LINCR2_TBDE_SHIFT)) & LINFLEXD_LINCR2_TBDE_MASK) 697 /*! @} */ 698 699 /*! @name BIDR - Buffer Identifier Register */ 700 /*! @{ */ 701 702 #define LINFLEXD_BIDR_ID_MASK (0x3FU) 703 #define LINFLEXD_BIDR_ID_SHIFT (0U) 704 #define LINFLEXD_BIDR_ID_WIDTH (6U) 705 #define LINFLEXD_BIDR_ID(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BIDR_ID_SHIFT)) & LINFLEXD_BIDR_ID_MASK) 706 707 #define LINFLEXD_BIDR_CCS_MASK (0x100U) 708 #define LINFLEXD_BIDR_CCS_SHIFT (8U) 709 #define LINFLEXD_BIDR_CCS_WIDTH (1U) 710 #define LINFLEXD_BIDR_CCS(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BIDR_CCS_SHIFT)) & LINFLEXD_BIDR_CCS_MASK) 711 712 #define LINFLEXD_BIDR_DIR_MASK (0x200U) 713 #define LINFLEXD_BIDR_DIR_SHIFT (9U) 714 #define LINFLEXD_BIDR_DIR_WIDTH (1U) 715 #define LINFLEXD_BIDR_DIR(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BIDR_DIR_SHIFT)) & LINFLEXD_BIDR_DIR_MASK) 716 717 #define LINFLEXD_BIDR_DFL_MASK (0x1C00U) 718 #define LINFLEXD_BIDR_DFL_SHIFT (10U) 719 #define LINFLEXD_BIDR_DFL_WIDTH (3U) 720 #define LINFLEXD_BIDR_DFL(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BIDR_DFL_SHIFT)) & LINFLEXD_BIDR_DFL_MASK) 721 /*! @} */ 722 723 /*! @name BDRL - Buffer Data Register Least Significant */ 724 /*! @{ */ 725 726 #define LINFLEXD_BDRL_DATA0_MASK (0xFFU) 727 #define LINFLEXD_BDRL_DATA0_SHIFT (0U) 728 #define LINFLEXD_BDRL_DATA0_WIDTH (8U) 729 #define LINFLEXD_BDRL_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BDRL_DATA0_SHIFT)) & LINFLEXD_BDRL_DATA0_MASK) 730 731 #define LINFLEXD_BDRL_DATA1_MASK (0xFF00U) 732 #define LINFLEXD_BDRL_DATA1_SHIFT (8U) 733 #define LINFLEXD_BDRL_DATA1_WIDTH (8U) 734 #define LINFLEXD_BDRL_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BDRL_DATA1_SHIFT)) & LINFLEXD_BDRL_DATA1_MASK) 735 736 #define LINFLEXD_BDRL_DATA2_MASK (0xFF0000U) 737 #define LINFLEXD_BDRL_DATA2_SHIFT (16U) 738 #define LINFLEXD_BDRL_DATA2_WIDTH (8U) 739 #define LINFLEXD_BDRL_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BDRL_DATA2_SHIFT)) & LINFLEXD_BDRL_DATA2_MASK) 740 741 #define LINFLEXD_BDRL_DATA3_MASK (0xFF000000U) 742 #define LINFLEXD_BDRL_DATA3_SHIFT (24U) 743 #define LINFLEXD_BDRL_DATA3_WIDTH (8U) 744 #define LINFLEXD_BDRL_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BDRL_DATA3_SHIFT)) & LINFLEXD_BDRL_DATA3_MASK) 745 /*! @} */ 746 747 /*! @name BDRM - Buffer Data Register Most Significant */ 748 /*! @{ */ 749 750 #define LINFLEXD_BDRM_DATA4_MASK (0xFFU) 751 #define LINFLEXD_BDRM_DATA4_SHIFT (0U) 752 #define LINFLEXD_BDRM_DATA4_WIDTH (8U) 753 #define LINFLEXD_BDRM_DATA4(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BDRM_DATA4_SHIFT)) & LINFLEXD_BDRM_DATA4_MASK) 754 755 #define LINFLEXD_BDRM_DATA5_MASK (0xFF00U) 756 #define LINFLEXD_BDRM_DATA5_SHIFT (8U) 757 #define LINFLEXD_BDRM_DATA5_WIDTH (8U) 758 #define LINFLEXD_BDRM_DATA5(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BDRM_DATA5_SHIFT)) & LINFLEXD_BDRM_DATA5_MASK) 759 760 #define LINFLEXD_BDRM_DATA6_MASK (0xFF0000U) 761 #define LINFLEXD_BDRM_DATA6_SHIFT (16U) 762 #define LINFLEXD_BDRM_DATA6_WIDTH (8U) 763 #define LINFLEXD_BDRM_DATA6(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BDRM_DATA6_SHIFT)) & LINFLEXD_BDRM_DATA6_MASK) 764 765 #define LINFLEXD_BDRM_DATA7_MASK (0xFF000000U) 766 #define LINFLEXD_BDRM_DATA7_SHIFT (24U) 767 #define LINFLEXD_BDRM_DATA7_WIDTH (8U) 768 #define LINFLEXD_BDRM_DATA7(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_BDRM_DATA7_SHIFT)) & LINFLEXD_BDRM_DATA7_MASK) 769 /*! @} */ 770 771 /*! @name GCR - Global Control Register */ 772 /*! @{ */ 773 774 #define LINFLEXD_GCR_SR_MASK (0x1U) 775 #define LINFLEXD_GCR_SR_SHIFT (0U) 776 #define LINFLEXD_GCR_SR_WIDTH (1U) 777 #define LINFLEXD_GCR_SR(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_GCR_SR_SHIFT)) & LINFLEXD_GCR_SR_MASK) 778 779 #define LINFLEXD_GCR_STOP_MASK (0x2U) 780 #define LINFLEXD_GCR_STOP_SHIFT (1U) 781 #define LINFLEXD_GCR_STOP_WIDTH (1U) 782 #define LINFLEXD_GCR_STOP(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_GCR_STOP_SHIFT)) & LINFLEXD_GCR_STOP_MASK) 783 784 #define LINFLEXD_GCR_RDLIS_MASK (0x4U) 785 #define LINFLEXD_GCR_RDLIS_SHIFT (2U) 786 #define LINFLEXD_GCR_RDLIS_WIDTH (1U) 787 #define LINFLEXD_GCR_RDLIS(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_GCR_RDLIS_SHIFT)) & LINFLEXD_GCR_RDLIS_MASK) 788 789 #define LINFLEXD_GCR_TDLIS_MASK (0x8U) 790 #define LINFLEXD_GCR_TDLIS_SHIFT (3U) 791 #define LINFLEXD_GCR_TDLIS_WIDTH (1U) 792 #define LINFLEXD_GCR_TDLIS(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_GCR_TDLIS_SHIFT)) & LINFLEXD_GCR_TDLIS_MASK) 793 794 #define LINFLEXD_GCR_RDFBM_MASK (0x10U) 795 #define LINFLEXD_GCR_RDFBM_SHIFT (4U) 796 #define LINFLEXD_GCR_RDFBM_WIDTH (1U) 797 #define LINFLEXD_GCR_RDFBM(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_GCR_RDFBM_SHIFT)) & LINFLEXD_GCR_RDFBM_MASK) 798 799 #define LINFLEXD_GCR_TDFBM_MASK (0x20U) 800 #define LINFLEXD_GCR_TDFBM_SHIFT (5U) 801 #define LINFLEXD_GCR_TDFBM_WIDTH (1U) 802 #define LINFLEXD_GCR_TDFBM(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_GCR_TDFBM_SHIFT)) & LINFLEXD_GCR_TDFBM_MASK) 803 /*! @} */ 804 805 /*! @name UARTPTO - UART Preset Timeout Register */ 806 /*! @{ */ 807 808 #define LINFLEXD_UARTPTO_PTO_MASK (0xFFFU) 809 #define LINFLEXD_UARTPTO_PTO_SHIFT (0U) 810 #define LINFLEXD_UARTPTO_PTO_WIDTH (12U) 811 #define LINFLEXD_UARTPTO_PTO(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTPTO_PTO_SHIFT)) & LINFLEXD_UARTPTO_PTO_MASK) 812 /*! @} */ 813 814 /*! @name UARTCTO - UART Current Timeout Register */ 815 /*! @{ */ 816 817 #define LINFLEXD_UARTCTO_CTO_MASK (0xFFFU) 818 #define LINFLEXD_UARTCTO_CTO_SHIFT (0U) 819 #define LINFLEXD_UARTCTO_CTO_WIDTH (12U) 820 #define LINFLEXD_UARTCTO_CTO(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_UARTCTO_CTO_SHIFT)) & LINFLEXD_UARTCTO_CTO_MASK) 821 /*! @} */ 822 823 /*! @name DMATXE - DMA Tx Enable Register */ 824 /*! @{ */ 825 826 #define LINFLEXD_DMATXE_DTE0_MASK (0x1U) 827 #define LINFLEXD_DMATXE_DTE0_SHIFT (0U) 828 #define LINFLEXD_DMATXE_DTE0_WIDTH (1U) 829 #define LINFLEXD_DMATXE_DTE0(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_DMATXE_DTE0_SHIFT)) & LINFLEXD_DMATXE_DTE0_MASK) 830 /*! @} */ 831 832 /*! @name DMARXE - DMA Rx Enable Register */ 833 /*! @{ */ 834 835 #define LINFLEXD_DMARXE_DRE0_MASK (0x1U) 836 #define LINFLEXD_DMARXE_DRE0_SHIFT (0U) 837 #define LINFLEXD_DMARXE_DRE0_WIDTH (1U) 838 #define LINFLEXD_DMARXE_DRE0(x) (((uint32_t)(((uint32_t)(x)) << LINFLEXD_DMARXE_DRE0_SHIFT)) & LINFLEXD_DMARXE_DRE0_MASK) 839 /*! @} */ 840 841 /*! 842 * @} 843 */ /* end of group LINFLEXD_Register_Masks */ 844 845 /*! 846 * @} 847 */ /* end of group LINFLEXD_Peripheral_Access_Layer */ 848 849 #endif /* #if !defined(S32Z2_LINFLEXD_H_) */ 850
