1 /* 2 * Copyright 2018 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef ISL29023_H_ 8 #define ISL29023_H_ 9 10 /** 11 ** 12 ** ISL29023 Ambient Light Sensor Internal Registers 13 */ 14 enum { 15 ISL29023_CMD_I = 0x00, 16 ISL29023_CMD_II = 0x01, 17 ISL29023_DATA_LSB = 0x02, 18 ISL29023_DATA_MSB = 0x03, 19 ISL29023_INT_LT_LSB = 0x04, 20 ISL29023_INT_LT_MSB = 0x05, 21 ISL29023_INT_HT_LSB = 0x06, 22 ISL29023_INT_HT_MSB = 0x07, 23 ISL29023_TEST = 0x08, 24 }; 25 26 #define ISL29023_I2C_ADDRESS (0x44) /*ISL29023 I2C Address */ 27 #define ISL29023_I2C_TEST_VALUE (0x00) /*ISL29023 test register value */ 28 29 /*-------------------------------- 30 ** Register: COMMAND-I 31 ** Enum: ISL29023_CMD_I 32 ** -- 33 ** Offset : 0x00 - Control & Status bits 34 ** ------------------------------*/ 35 typedef union { 36 struct { 37 uint8_t prst: 2; /* IRQ persist bits. */ 38 39 uint8_t flag: 1; /* IRQ flag bit. */ 40 41 uint8_t _reserved_ : 2; 42 uint8_t op : 3; /* Operation mode bits. */ 43 44 } b; 45 uint8_t w; 46 } ISL29023_CMD_I_t; 47 48 49 /* 50 ** COMMAND-I - Bit field mask definitions 51 */ 52 #define ISL29023_CMD_I_PRST_MASK ((uint8_t) 0x03) 53 #define ISL29023_CMD_I_PRST_SHIFT ((uint8_t) 0) 54 55 #define ISL29023_CMD_I_FLAG_MASK ((uint8_t) 0x04) 56 #define ISL29023_CMD_I_FLAG_SHIFT ((uint8_t) 2) 57 58 #define ISL29023_CMD_I_OP_MASK ((uint8_t) 0xe0) 59 #define ISL29023_CMD_I_OP_SHIFT ((uint8_t) 5) 60 61 62 /* 63 ** COMMAND-I - Bit field value definitions 64 */ 65 #define ISL29023_CMD_I_PRST_1 ((uint8_t) 0x00) /* Number of Integration Samples = 1 */ 66 #define ISL29023_CMD_I_PRST_4 ((uint8_t) 0x01) /* Number of Integration Samples = 4 */ 67 #define ISL29023_CMD_I_PRST_8 ((uint8_t) 0x02) /* Number of Integration Samples = 8 */ 68 #define ISL29023_CMD_I_PRST_16 ((uint8_t) 0x03) /* Number of Integration Samples = 16 */ 69 #define ISL29023_CMD_I_FLAG_CLEARED ((uint8_t) 0x00) /* IRQ flag is cleared or not triggered yet */ 70 #define ISL29023_CMD_I_FLAG_TRIGGERED ((uint8_t) 0x04) /* IRQ flag is triggered */ 71 #define ISL29023_CMD_I_OP_POWER_DOWN ((uint8_t) 0x00) /* Power-down the device (default) */ 72 #define ISL29023_CMD_I_OP_ALS_ONCE ((uint8_t) 0x20) /* IC measures ALS only once */ 73 #define ISL29023_CMD_I_OP_IR_ONCE ((uint8_t) 0x40) /* IC meausres IR only once */ 74 #define ISL29023_CMD_I_OP_ALS_CONT ((uint8_t) 0xA0) /* IC meausres ALS continuously */ 75 #define ISL29023_CMD_I_OP_IR_CONT ((uint8_t) 0xC0) /* IC meausres IR continuous */ 76 77 /*------------------------------*/ 78 79 80 81 /*-------------------------------- 82 ** Register: COMMAND-II 83 ** Enum: ISL29023_CMD_II 84 ** -- 85 ** Offset : 0x01 - Control bits 86 ** ------------------------------*/ 87 typedef union { 88 struct { 89 uint8_t range: 2; /* Full scale range bits */ 90 91 uint8_t res : 2; /* ADC resolution bits */ 92 93 uint8_t _reserved_ : 4; 94 95 } b; 96 uint8_t w; 97 } ISL29023_CMD_II_t; 98 99 100 /* 101 ** COMMAND-II - Bit field mask definitions 102 */ 103 #define ISL29023_CMD_II_RANGE_MASK ((uint8_t) 0x03) 104 #define ISL29023_CMD_II_RANGE_SHIFT ((uint8_t) 0) 105 106 #define ISL29023_CMD_II_RES_MASK ((uint8_t) 0x0C) 107 #define ISL29023_CMD_II_RES_SHIFT ((uint8_t) 2) 108 109 110 /* 111 ** COMMAND-II - Bit field value definitions 112 */ 113 #define ISL29023_CMD_II_RANGE_1 ((uint8_t) 0x00) /* FSR @ALS Sensing = 1.000 */ 114 #define ISL29023_CMD_II_RANGE_2 ((uint8_t) 0x01) /* FSR @ALS Sensing = 4.000 */ 115 #define ISL29023_CMD_II_RANGE_3 ((uint8_t) 0x02) /* FSR @ALS Sensing = 16.000 */ 116 #define ISL29023_CMD_II_RANGE_4 ((uint8_t) 0x03) /* FSR @ALS Sensing = 64.000 */ 117 #define ISL29023_CMD_II_RES_16 ((uint8_t) 0x00) /* 2^16 ADC resolution */ 118 #define ISL29023_CMD_II_RES_12 ((uint8_t) 0x04) /* 2^12 ADC resolution */ 119 #define ISL29023_CMD_II_RES_8 ((uint8_t) 0x08) /* 2^8 ADC resolution */ 120 #define ISL29023_CMD_II_RES_4 ((uint8_t) 0x0C) /* 2^4 ADC resolution */ 121 122 /*------------------------------*/ 123 124 125 /*-------------------------------- 126 ** Register: DATA_LSB 127 ** Enum: ISL29023_DATA_LSB 128 ** -- 129 ** Offset : 0x02 - Bits 7-0 of the 16-bit data register. 130 ** ------------------------------*/ 131 typedef uint8_t ISL29023_DATA_LSB_t; 132 133 134 /*-------------------------------- 135 ** Register: DATA_MSB 136 ** Enum: ISL29023_DATA_MSB 137 ** -- 138 ** Offset : 0x03 - Bits 15-8 of the 16-bit data register. 139 ** ------------------------------*/ 140 typedef uint8_t ISL29023_DATA_MSB_t; 141 142 143 /*-------------------------------- 144 ** Register: INT_LT_LSB 145 ** Enum: ISL29023_INT_LT_LSB 146 ** -- 147 ** Offset : 0x04 - Bits 7-0 of the 16-bit lower IRQ treshold register. 148 ** ------------------------------*/ 149 typedef uint8_t ISL29023_INT_LT_LSB_t; 150 151 152 /*-------------------------------- 153 ** Register: INT_LT_MSB 154 ** Enum: ISL29023_INT_LT_MSB 155 ** -- 156 ** Offset : 0x05 - Bits 15-8 of the 16-bit lower IRQ treshold register. 157 ** ------------------------------*/ 158 typedef uint8_t ISL29023_INT_LT_MSB_t; 159 160 161 /*-------------------------------- 162 ** Register: INT_HT_LSB 163 ** Enum: ISL29023_INT_HT_LSB 164 ** -- 165 ** Offset : 0x06 - Bits 7-0 of the 16-bit upper IRQ treshold register. 166 ** ------------------------------*/ 167 typedef uint8_t ISL29023_INT_HT_LSB_t; 168 169 170 /*-------------------------------- 171 ** Register: INT_HT_MSB 172 ** Enum: ISL29023_INT_HT_MSB 173 ** -- 174 ** Offset : 0x07 - Bits 15-8 of the 16-bit upper IRQ treshold register. 175 ** ------------------------------*/ 176 typedef uint8_t ISL29023_INT_HT_MSB_t; 177 178 179 /*-------------------------------- 180 ** Register: TEST 181 ** Enum: ISL29023_TEST 182 ** -- 183 ** Offset : 0x08 - Test register (hold 00h during normal operation). 184 ** ------------------------------*/ 185 typedef uint8_t ISL29023_TEST_t; 186 187 #endif /* ISL29023_H_ */ 188
