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Searched refs:IP_GMAC_0_BASE (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/soc/s32k344/include/
DGmac_Ip_Device_Registers.h129 (Gmac_Ip_ChannelType *)(IP_GMAC_0_BASE + (uint32)DMA_CH0_CONTROL_ADDR16), \
130 (Gmac_Ip_ChannelType *)(IP_GMAC_0_BASE + (uint32)DMA_CH1_CONTROL_ADDR16) \
159 (Gmac_Ip_QueueType *)(IP_GMAC_0_BASE + (uint32)MTL_TXQ0_OPERATION_MODE_ADDR16), \
160 (Gmac_Ip_QueueType *)(IP_GMAC_0_BASE + (uint32)MTL_TXQ1_OPERATION_MODE_ADDR16) \
/hal_nxp-3.5.0/s32/drivers/s32k3/Eth_GMAC/include/
DEmac_Ip_Wrapper.h40 #define IP_GMAC_0_BASE IP_EMAC_BASE macro