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Searched refs:IPTXFCR (Results 1 – 25 of 76) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi_edma.c193 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferEDMA()
209 …handle->count = (uint8_t)((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_… in FLEXSPI_TransferEDMA()
319 if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferAbortEDMA()
353 else if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferGetTransferCountEDMA()
Dfsl_flexspi.h500 base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK; in FLEXSPI_EnableTxDMA()
504 base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK; in FLEXSPI_EnableTxDMA()
563 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_ResetFifos()
Dfsl_flexspi_dma.c175 …8U * ((uint8_t)(((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + … in FLEXSPI_WriteDataDMA()
544 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferDMA()
601 if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferAbortDMA()
634 else if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferGetTransferCountDMA()
Dfsl_flexspi.c343 base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; in FLEXSPI_Init()
344 base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK((uint32_t)config->txWatermark / 8U - 1U); in FLEXSPI_Init()
651 …uint32_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SH… in FLEXSPI_WriteBlocking()
849 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferBlocking()
973 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferNonBlocking()
1151 …txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U; in FLEXSPI_TransferHandleIRQ()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h7266 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
DMIMXRT685S_cm33.h13368 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h16123 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h13524 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h13368 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h12320 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h13004 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
DMIMXRT595S_cm33.h19602 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h12320 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h19585 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h19569 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h21869 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h20537 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h19598 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h21322 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h22247 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h21871 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h23033 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h17121 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h23102 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h26871 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member

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