| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexspi/ |
| D | fsl_flexspi.h | 714 base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK; in FLEXSPI_EnableIPParallelMode()
718 base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; in FLEXSPI_EnableIPParallelMode()
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| D | fsl_flexspi_edma.c | 204 base->IPCR1 = configValue; in FLEXSPI_TransferEDMA()
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| D | fsl_flexspi.c | 861 base->IPCR1 = configValue; in FLEXSPI_TransferBlocking()
985 base->IPCR1 = configValue; in FLEXSPI_TransferNonBlocking()
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| D | fsl_flexspi_dma.c | 555 base->IPCR1 = configValue; in FLEXSPI_TransferDMA()
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| /hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimxrt1170/ |
| D | evkmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 315 MEM_WriteU32(0x400d4094, 0x00000002); // IPCR1
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| /hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkbmimxrt1170/ |
| D | evkbmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 315 MEM_WriteU32(0x400d4094, 0x00000002); // IPCR1
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| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/semc/ |
| D | fsl_semc.c | 241 base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes); in SEMC_ConfigureIPCommand()
516 SEMC->IPCR1 = 0x2U; in SEMC_ConfigureSDRAM()
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 19580 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
33943 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 19564 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
33926 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 21864 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
36903 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 20532 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
35501 …__IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 21317 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
39767 …__IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 22242 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
37790 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 21866 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
40313 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 23028 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
41984 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 23097 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
41978 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 7261 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
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| D | MIMXRT685S_cm33.h | 13363 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 16118 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 13519 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm4.h | 37706 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
67771 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| D | MIMXRT1165_cm7.h | 37709 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
66838 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/ |
| D | MIMXRT633S.h | 13363 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm7.h | 48833 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
78022 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 48833 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
78022 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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