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Searched refs:IOFLT (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE04Z4/drivers/
Dfsl_port.h191 fltReg = base->IOFLT & ~((uint32_t)FSL_PORT_FILTER_SELECT_BITMASK << (uint32_t)port); in PORT_SetFilterSelect()
193 base->IOFLT = ((uint32_t)filter << (uint32_t)port) | fltReg; in PORT_SetFilterSelect()
214 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV1_MASK; in PORT_SetFilterDIV1WidthThreshold()
215 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV1(threshold); in PORT_SetFilterDIV1WidthThreshold()
236 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV2_MASK; in PORT_SetFilterDIV2WidthThreshold()
237 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV2(threshold); in PORT_SetFilterDIV2WidthThreshold()
254 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV3_MASK; in PORT_SetFilterDIV3WidthThreshold()
255 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV3(threshold); in PORT_SetFilterDIV3WidthThreshold()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE02Z4/drivers/
Dfsl_port.h200 fltReg = base->IOFLT & ~((uint32_t)FSL_PORT_FILTER_SELECT_BITMASK << (uint32_t)port); in PORT_SetFilterSelect()
202 base->IOFLT = ((uint32_t)filter << (uint32_t)port) | fltReg; in PORT_SetFilterSelect()
223 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV1_MASK; in PORT_SetFilterDIV1WidthThreshold()
224 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV1(threshold); in PORT_SetFilterDIV1WidthThreshold()
245 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV2_MASK; in PORT_SetFilterDIV2WidthThreshold()
246 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV2(threshold); in PORT_SetFilterDIV2WidthThreshold()
263 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV3_MASK; in PORT_SetFilterDIV3WidthThreshold()
264 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV3(threshold); in PORT_SetFilterDIV3WidthThreshold()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE04Z4/
DMKE04Z4.h3918 __IO uint32_t IOFLT; /**< Port Filter Register, offset: 0x0 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE02Z4/
DMKE02Z4.h3990 __IO uint32_t IOFLT; /**< Port Filter Register, offset: 0x0 */ member