1 /* 2 * Copyright (c) 2022, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SOC_ARM_NXP_LPC_55xxx_PINCTRL_SOC_H_ 8 #define ZEPHYR_SOC_ARM_NXP_LPC_55xxx_PINCTRL_SOC_H_ 9 10 #include <zephyr/devicetree.h> 11 #include <zephyr/types.h> 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /** @cond INTERNAL_HIDDEN */ 18 19 typedef uint32_t pinctrl_soc_pin_t; 20 21 #ifdef CONFIG_SOC_LPC55S36 22 /* LPC55S36 has two analog switches, and no IOCON_PIO_ASW definitions */ 23 #define IOCON_PIO_ASW(x) IOCON_PIO_ASW0(x) 24 #define IOCON_PIO_ASW_MASK IOCON_PIO_ASW0_MASK 25 #else 26 /* Other LPC55sxx parts have one analog switch */ 27 #define IOCON_PIO_ASW1(x) 0 28 #define IOCON_PIO_ASW1_MASK 0x0 29 #endif 30 31 #define Z_PINCTRL_IOCON_PINCFG(node_id) \ 32 (IF_ENABLED(DT_PROP(node_id, bias_pull_down), (IOCON_PIO_MODE(0x1) |)) \ 33 IF_ENABLED(DT_PROP(node_id, bias_pull_up), (IOCON_PIO_MODE(0x2) |)) \ 34 IF_ENABLED(DT_PROP(node_id, drive_push_pull), (IOCON_PIO_MODE(0x3) |)) \ 35 IOCON_PIO_SLEW(DT_ENUM_IDX(node_id, slew_rate)) | \ 36 IOCON_PIO_INVERT(DT_PROP(node_id, nxp_invert)) | \ 37 IOCON_PIO_DIGIMODE(!DT_PROP(node_id, nxp_analog_mode)) | \ 38 IOCON_PIO_OD(DT_PROP(node_id, drive_open_drain)) | \ 39 IOCON_PIO_ASW(DT_PROP(node_id, nxp_analog_mode)) | \ 40 IOCON_PIO_ASW1(DT_PROP(node_id, nxp_analog_alt_mode)) | \ 41 IOCON_PIO_SSEL(DT_ENUM_IDX_OR(node_id, power_source, 0)) | \ 42 IOCON_PIO_FILTEROFF(!DT_NODE_HAS_PROP(node_id, nxp_i2c_filter)) | \ 43 IOCON_PIO_ECS(DT_PROP(node_id, nxp_i2c_pullup)) | \ 44 IOCON_PIO_EGP(!DT_PROP(node_id, nxp_i2c_mode)) | \ 45 IOCON_PIO_I2CFILTER(DT_ENUM_IDX_OR(node_id, nxp_i2c_filter, 0))) 46 47 /* Mask for digital type pin configuration register */ 48 #define Z_PINCTRL_IOCON_D_PIN_MASK (IOCON_PIO_OD_MASK | \ 49 IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_INVERT_MASK | IOCON_PIO_SLEW_MASK | \ 50 IOCON_PIO_MODE_MASK | IOCON_PIO_FUNC_MASK) 51 52 /* Mask for analog type pin configuration register */ 53 #define Z_PINCTRL_IOCON_A_PIN_MASK \ 54 (Z_PINCTRL_IOCON_D_PIN_MASK | IOCON_PIO_ASW_MASK | IOCON_PIO_ASW1_MASK) 55 56 /* Mask for i2c type pin configuration register */ 57 #define Z_PINCTRL_IOCON_I_PIN_MASK (Z_PINCTRL_IOCON_D_PIN_MASK | \ 58 IOCON_PIO_SSEL_MASK | IOCON_PIO_FILTEROFF_MASK | IOCON_PIO_ECS_MASK | \ 59 IOCON_PIO_EGP_MASK | IOCON_PIO_I2CFILTER_MASK) 60 61 #define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ 62 DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOCON_PINCFG(group), 63 64 /** 65 * @brief Utility macro to initialize state pins contained in a given property. 66 * 67 * @param node_id Node identifier. 68 * @param prop Property name describing state pins. 69 */ 70 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ 71 {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ 72 DT_FOREACH_PROP_ELEM, pinmux, \ 73 Z_PINCTRL_STATE_PIN_INIT)} 74 75 #ifdef __cplusplus 76 } 77 #endif 78 79 #endif /* ZEPHYR_SOC_ARM_NXP_LPC_55xxx_PINCTRL_SOC_H_ */ 80
