I3C_SCONFIG_SLVENA_MASK (reference) in projects: hal_nxp-3.5.0

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Searched refs:I3C_SCONFIG_SLVENA_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/i3c/
D	fsl_i3c.c	`847 …CONFIG_S0IGNORE_MASK \| I3C_SCONFIG_MATCHSS_MASK \| I3C_SCONFIG_NACK_MASK \| I3C_SCONFIG_SLVENA_MASK); in I3C_Init() 2636 …CONFIG_S0IGNORE_MASK \| I3C_SCONFIG_MATCHSS_MASK \| I3C_SCONFIG_NACK_MASK \| I3C_SCONFIG_SLVENA_MASK); in I3C_SlaveInit() 3346 …if ((I3C_SCONFIG_SLVENA_MASK == (base->SCONFIG & I3C_SCONFIG_SLVENA_MASK)) && (NULL != s_i3cSlaveI… in I3C_CommonIRQHandler()`
D	fsl_i3c.h	`1458 base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) \| I3C_SCONFIG_SLVENA(isEnable); in I3C_SlaveEnable()`
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
D	S32Z2_I3C.h	`249 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 252 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
D	MIMXRT685S_dsp.h	`10617 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 10621 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
D	MIMXRT685S_cm33.h	`17501 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 17505 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
D	MIMXRT633S.h	`17501 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 17505 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
D	LPC5536.h	`20945 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 20949 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
D	MIMXRT595S_dsp.h	`19903 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 19906 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
D	MIMXRT595S_cm33.h	`26862 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 26865 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
D	LPC5534.h	`20945 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 20949 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
D	MIMXRT533S.h	`26858 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 26861 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
D	LPC55S36.h	`25746 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 25750 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/
D	MIMXRT555S.h	`26861 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 26864 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
D	MIMX9352_cm33.h	`41021 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 41025 …FIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`
D	MIMX9352_ca55.h	`36309 #define I3C_SCONFIG_SLVENA_MASK (0x1U) macro 36313 … (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)`

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