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Searched refs:I3C_MCTRL_ADDR_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_I3C.h1184 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
1187 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/i3c/
Dfsl_i3c.c1231 …lVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | in I3C_MasterRepeatedStartWithRxSize()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h11659 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
11663 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
DMIMXRT685S_cm33.h18543 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
18547 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h18543 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
18547 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h22056 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
22060 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h20799 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
20802 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
DMIMXRT595S_cm33.h27758 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
27761 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h22056 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
22060 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h27754 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
27757 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h26857 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
26861 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h27757 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
27760 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h42244 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
42248 …ine I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
DMIMX9352_ca55.h37460 #define I3C_MCTRL_ADDR_MASK (0xFE00U) macro
37464 … (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)