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Searched refs:I3C_MCONFIG_PPLOW_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_I3C.h220 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
223 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/i3c/
Dfsl_i3c.c1122 …base->MCONFIG = (base->MCONFIG & ~(I3C_MCONFIG_PPBAUD_MASK | I3C_MCONFIG_PPLOW_MASK | I3C_MCONFIG_… in I3C_MasterSetBaudRate()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h10583 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
10587 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
DMIMXRT685S_cm33.h17467 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
17471 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h17467 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
17471 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h20911 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
20915 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h19874 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
19877 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
DMIMXRT595S_cm33.h26833 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
26836 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h20911 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
20915 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h26829 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
26832 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h25712 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
25716 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h26832 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
26835 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h40987 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
40991 …CONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
DMIMX9352_ca55.h36275 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) macro
36279 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)