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Searched refs:GMAC_DMA_CH0_STATUS_RI_MASK (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip_Irq.c224 if ((IP_GMAC_0->DMA_CH0_STATUS & GMAC_DMA_CH0_STATUS_RI_MASK) != 0U) in ISR()
365 if ((IP_GMAC_1->DMA_CH0_STATUS & GMAC_DMA_CH0_STATUS_RI_MASK) != 0U) in ISR()
DGmac_Ip_Hw_Access.c79 | GMAC_DMA_CH0_STATUS_RBU_MASK | GMAC_DMA_CH0_STATUS_RI_MASK)
483 ((StatusFlags & GMAC_DMA_CH0_STATUS_RI_MASK) != 0U)) in GMAC_RxIRQHandler()
486 ChBase->DMA_STATUS = GMAC_DMA_CH0_STATUS_RI_MASK; in GMAC_RxIRQHandler()
498 ChBase->DMA_STATUS = GMAC_DMA_CH0_STATUS_RI_MASK; in GMAC_RxIRQHandler()
DGmac_Ip.c191 …CH0_STATUS_TI_MASK | (uint32)GMAC_DMA_CH0_STATUS_TBU_MASK | (uint32)GMAC_DMA_CH0_STATUS_RI_MASK | \
/hal_nxp-3.5.0/s32/drivers/s32k3/Eth_GMAC/include/
DGmac_Ip_Types.h138 GMAC_CH_INTERRUPT_RI = GMAC_DMA_CH0_STATUS_RI_MASK,
DEmac_Ip_Wrapper.h4697 #define GMAC_DMA_CH0_STATUS_RI_MASK EMAC_DMA_CH0_STATUS_RI_MASK macro