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Searched refs:Finput (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_ProgFreqSwitch.c173 uint32 Finput = 0U; in Clock_Ip_CgmXPcfsSdurDivcDiveDivs() local
202 Finput = Config->ClockSourceFrequency / CLOCK_IP_DIVIDE_BY_1000000; in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
210 CLOCK_IP_DEV_ASSERT(Finput != 0U); in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
217 …AllowableIDDchange * Config->StepDuration * CLOCK_IP_DIVIDE_BY_100000 / (Finput * CLOCK_IP_DYNAMIC… in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
242 …Var1 = 256U + ((CLOCK_IP_CONSTANT_2048000 * Finput) / (Fsafe * Rate)) - (CLOCK_IP_CONSTANT_2048000… in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
273 DivEndValue = (Finput * 1000U / Fsafe) - 1U; in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
287 (void)Finput; in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_ProgFreqSwitch.c165 uint32 Finput = 0U; in Clock_Ip_CgmXPcfsSdurDivcDiveDivs() local
189 Finput = Config->ClockSourceFrequency / CLOCK_IP_DIVIDE_BY_1000000; in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
197 CLOCK_IP_DEV_ASSERT(Finput != 0U); in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
204 …AllowableIDDchange * Config->StepDuration * CLOCK_IP_DIVIDE_BY_100000 / (Finput * CLOCK_IP_DYNAMIC… in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
229 …Var1 = 256U + ((CLOCK_IP_CONSTANT_2048000 * Finput) / (Fsafe * Rate)) - (CLOCK_IP_CONSTANT_2048000… in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
260 DivEndValue = (Finput * 1000U / Fsafe) - 1U; in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()