1  /*
2   * Copyright (c) 2016, Freescale Semiconductor, Inc.
3   * Copyright 2016-2017 NXP
4   * All rights reserved.
5   *
6   * SPDX-License-Identifier: BSD-3-Clause
7   */
8  
9  /**
10   * @file fxos8700.h
11   * @brief The fxos8700.h file contains the register definitions for FXOS8700 sensor driver.
12   */
13  
14  #ifndef FXOS8700_H_
15  #define FXOS8700_H_
16  /**
17   * @brief FXOS8700 internal register addresses explained in the FXOS8700 data sheet.
18   */
19  enum {
20      FXOS8700_STATUS           = 0x00, /*!< Alias for ::FXOS8700_DR_STATUS or ::FXOS8700_F_STATUS. */
21      FXOS8700_OUT_X_MSB        = 0x01, /*!< 14-bit X-axis measurement data bits 13:6. */
22      FXOS8700_OUT_X_LSB        = 0x02, /*!< 14-bit X-axis measurement data bits 5:0. */
23      FXOS8700_OUT_Y_MSB        = 0x03, /*!< 14-bit Y-axis measurement data bits 13:6. */
24      FXOS8700_OUT_Y_LSB        = 0x04, /*!< 14-bit Y-axis measurement data bits 5:0. */
25      FXOS8700_OUT_Z_MSB        = 0x05, /*!< 14-bit Z-axis measurement data bits 13:6. */
26      FXOS8700_OUT_Z_LSB        = 0x06, /*!< 14-bit Z-axis measurement data bits 5:0. */
27      FXOS8700_F_SETUP          = 0x09, /*!< FIFO setup. */
28      FXOS8700_TRIG_CFG         = 0x0A, /*!< FIFO event trigger configuration register. */
29      FXOS8700_SYSMOD           = 0x0B, /*!< Current system mode. */
30      FXOS8700_INT_SOURCE       = 0x0C, /*!< Interrupt status. */
31      FXOS8700_WHO_AM_I         = 0x0D, /*!< Device ID. */
32      FXOS8700_XYZ_DATA_CFG     = 0x0E, /*!< Acceleration dynamic range and filter enable settings. */
33      FXOS8700_HP_FILTER_CUTOFF = 0x0F, /*!< Pulse detection highpass and lowpass filter enabling bits. */
34      FXOS8700_PL_STATUS        = 0x10, /*!< Landscape/portrait orientation status. */
35      FXOS8700_PL_CFG           = 0x11, /*!< Landscape/portrait configuration. */
36      FXOS8700_PL_COUNT         = 0x12, /*!< Landscape/portrait debounce counter. */
37      FXOS8700_PL_BF_ZCOMP      = 0x13, /*!< Back/front trip angle threshold. */
38      FXOS8700_PL_THS_REG       = 0x14, /*!< Portrait to landscape trip threshold angle and hysteresis settings. */
39      FXOS8700_A_FFMT_CFG       = 0x15, /*!< Freefall/motion function configuration. */
40      FXOS8700_A_FFMT_SRC       = 0x16, /*!< Freefall/motion event source register. */
41      FXOS8700_A_FFMT_THS       = 0x17, /*!< Freefall/motion threshold register. */
42      FXOS8700_A_FFMT_COUNT     = 0x18, /*!< Freefall/motion debounce counter. */
43      FXOS8700_TRANSIENT_CFG    = 0x1D, /*!< Transient function configuration. */
44      FXOS8700_TRANSIENT_SRC    = 0x1E, /*!< Transient event status register. */
45      FXOS8700_TRANSIENT_THS    = 0x1F, /*!< Transient event threshold. */
46      FXOS8700_TRANSIENT_COUNT  = 0x20, /*!< Transient debounce counter. */
47      FXOS8700_PULSE_CFG        = 0x21, /*!< Pulse function configuration. */
48      FXOS8700_PULSE_SRC        = 0x22, /*!< Pulse function source register. */
49      FXOS8700_PULSE_THSX       = 0x23, /*!< X-axis pulse threshold. */
50      FXOS8700_PULSE_THSY       = 0x24, /*!< Y-axis pulse threshold. */
51      FXOS8700_PULSE_THSZ       = 0x25, /*!< Z-axis pulse threshold. */
52      FXOS8700_PULSE_TMLT       = 0x26, /*!< Time limit for pulse detection. */
53      FXOS8700_PULSE_LTCY       = 0x27, /*!< Latency time for second pulse detection. */
54      FXOS8700_PULSE_WIND       = 0x28, /*!< Window time for second pulse detection. */
55      FXOS8700_ASLP_COUNT       = 0x29, /*!< The counter setting for auto-sleep period. */
56      FXOS8700_CTRL_REG1        = 0x2A, /*!< System ODR, accelerometer OSR (Output sample rate), operating mode. */
57      FXOS8700_CTRL_REG2        = 0x2B, /*!< Self-test, reset, accelerometer OSR, and sleep mode settings. */
58      FXOS8700_CTRL_REG3        = 0x2C, /*!< Sleep mode interrupt wake enable, interrupt polarity, push-pull/open drain configuration. */
59      FXOS8700_CTRL_REG4        = 0x2D, /*!< Interrupt enable register. */
60      FXOS8700_CTRL_REG5        = 0x2E, /*!< Interrupt pin (INT1/INT2) map. */
61      FXOS8700_OFF_X            = 0x2F, /*!< X-axis accelerometer offset adjust. */
62      FXOS8700_OFF_Y            = 0x30, /*!< Y-axis accelerometer offset adjust. */
63      FXOS8700_OFF_Z            = 0x31, /*!< Z-axis accelerometer offset adjust. */
64      FXOS8700_M_DR_STATUS      = 0x32, /*!< The magnetometer data ready status. */
65      FXOS8700_M_OUT_X_MSB      = 0x33, /*!< MSB of the 16-bit magnetometer data for X-axis. */
66      FXOS8700_M_OUT_X_LSB      = 0x34, /*!< LSB of the 16-bit magnetometer data for X-axis. */
67      FXOS8700_M_OUT_Y_MSB      = 0x35, /*!< MSB of the 16-bit magnetometer data for Y-axis. */
68      FXOS8700_M_OUT_Y_LSB      = 0x36, /*!< LSB of the 16-bit magnetometer data for Y-axis. */
69      FXOS8700_M_OUT_Z_MSB      = 0x37, /*!< MSB of the 16-bit magnetometer data for Z-axis. */
70      FXOS8700_M_OUT_Z_LSB      = 0x38, /*!< LSB of the 16-bit magnetometer data for Z-axis. */
71      FXOS8700_CMP_X_MSB        = 0x39, /*!< Bits [13:8] of integrated X-axis acceleration data. */
72      FXOS8700_CMP_X_LSB        = 0x3A, /*!< Bits [7:0] of integrated X-axis acceleration data. */
73      FXOS8700_CMP_Y_MSB        = 0x3B, /*!< Bits [13:8] of integrated Y-axis acceleration data. */
74      FXOS8700_CMP_Y_LSB        = 0x3C, /*!< Bits [7:0] of integrated Y-axis acceleration data. */
75      FXOS8700_CMP_Z_MSB        = 0x3D, /*!< Bits [13:8] of integrated Z-axis acceleration data. */
76      FXOS8700_CMP_Z_LSB        = 0x3E, /*!< Bits [7:0] of integrated Z-axis acceleration data. */
77      FXOS8700_M_OFF_X_MSB      = 0x3F, /*!< MSB of magnetometer X-axis offset. */
78      FXOS8700_M_OFF_X_LSB      = 0x40, /*!< LSB of magnetometer X-axis offset. */
79      FXOS8700_M_OFF_Y_MSB      = 0x41, /*!< MSB of magnetometer Y-axis offset. */
80      FXOS8700_M_OFF_Y_LSB      = 0x42, /*!< LSB of magnetometer Y-axis offset. */
81      FXOS8700_M_OFF_Z_MSB      = 0x43, /*!< MSB of magnetometer Z-axis offset. */
82      FXOS8700_M_OFF_Z_LSB      = 0x44, /*!< LSB of magnetometer Z-axis offset. */
83      FXOS8700_MAX_X_MSB        = 0x45, /*!< Magnetometer X-axis maximum value MSB. */
84      FXOS8700_MAX_X_LSB        = 0x46, /*!< Magnetometer X-axis maximum value LSB. */
85      FXOS8700_MAX_Y_MSB        = 0x47, /*!< Magnetometer Y-axis maximum value MSB. */
86      FXOS8700_MAX_Y_LSB        = 0x48, /*!< Magnetometer Y-axis maximum value LSB. */
87      FXOS8700_MAX_Z_MSB        = 0x49, /*!< Magnetometer Z-axis maximum value MSB. */
88      FXOS8700_MAX_Z_LSB        = 0x4A, /*!< Magnetometer Z-axis maximum value LSB. */
89      FXOS8700_MIN_X_MSB        = 0x4B, /*!< Magnetometer X-axis minimum value MSB. */
90      FXOS8700_MIN_X_LSB        = 0x4C, /*!< Magnetometer X-axis minimum value LSB. */
91      FXOS8700_MIN_Y_MSB        = 0x4D, /*!< Magnetometer Y-axis minimum value MSB. */
92      FXOS8700_MIN_Y_LSB        = 0x4E, /*!< Magnetometer Y-axis minimum value LSB. */
93      FXOS8700_MIN_Z_MSB        = 0x4F, /*!< Magnetometer Z-axis minimum value MSB. */
94      FXOS8700_MIN_Z_LSB        = 0x50, /*!< Magnetometer Z-axis minimum value LSB. */
95      FXOS8700_TEMP             = 0x51, /*!< Device temperature with a valid range of -128 to 127 degrees C. */
96      FXOS8700_M_THS_CFG        = 0x52, /*!< Magnetic threshold detection function configuration. */
97      FXOS8700_M_THS_SRC        = 0x53, /*!< Magnetic threshold event source register. */
98      FXOS8700_M_THS_X_MSB      = 0x54, /*!< X-axis magnetic threshold MSB. */
99      FXOS8700_M_THS_X_LSB      = 0x55, /*!< X-axis magnetic threshold LSB. */
100      FXOS8700_M_THS_Y_MSB      = 0x56, /*!< Y-axis magnetic threshold MSB. */
101      FXOS8700_M_THS_Y_LSB      = 0x57, /*!< Y-axis magnetic threshold LSB. */
102      FXOS8700_M_THS_Z_MSB      = 0x58, /*!< Z-axis magnetic threshold MSB. */
103      FXOS8700_M_THS_Z_LSB      = 0x59, /*!< Z-axis magnetic threshold LSB. */
104      FXOS8700_M_THS_COUNT      = 0x5A, /*!< Magnetic threshold debounce counter. */
105      FXOS8700_M_CTRL_REG1      = 0x5B, /*!< Control for magnetometer sensor functions. */
106      FXOS8700_M_CTRL_REG2      = 0x5C, /*!< Control for magnetometer sensor functions. */
107      FXOS8700_M_CTRL_REG3      = 0x5D, /*!< Control for magnetometer sensor functions. */
108      FXOS8700_M_INT_SRC        = 0x5E, /*!< Magnetometer interrupt source. */
109      FXOS8700_A_VECM_CFG       = 0x5F, /*!< Acceleration vector magnitude configuration register. */
110      FXOS8700_A_VECM_THS_MSB   = 0x60, /*!< Acceleration vector magnitude threshold MSB. */
111      FXOS8700_A_VECM_THS_LSB   = 0x61, /*!< Acceleration vector magnitude threshold LSB. */
112      FXOS8700_A_VECM_CNT       = 0x62, /*!< Acceleration vector magnitude debounce count. */
113      FXOS8700_A_VECM_INITX_MSB = 0x63, /*!< Acceleration vector magnitude X-axis reference value MSB. */
114      FXOS8700_A_VECM_INITX_LSB = 0x64, /*!< Acceleration vector magnitude X-axis reference value LSB. */
115      FXOS8700_A_VECM_INITY_MSB = 0x65, /*!< Acceleration vector magnitude Y-axis reference value MSB. */
116      FXOS8700_A_VECM_INITY_LSB = 0x66, /*!< Acceleration vector magnitude Y-axis reference value LSB. */
117      FXOS8700_A_VECM_INITZ_MSB = 0x67, /*!< Acceleration vector magnitude Z-axis reference value MSB. */
118      FXOS8700_A_VECM_INITZ_LSB = 0x68, /*!< Acceleration vector magnitude Z-axis reference value LSB. */
119      FXOS8700_M_VECM_CFG       = 0x69, /*!< Magnetic vector magnitude configuration register. */
120      FXOS8700_M_VECM_THS_MSB   = 0x6A, /*!< Magnetic vector magnitude threshold MSB. */
121      FXOS8700_M_VECM_THS_LSB   = 0x6B, /*!< Magnetic vector magnitude threshold LSB. */
122      FXOS8700_M_VECM_CNT       = 0x6C, /*!< Magnetic vector magnitude debounce count. */
123      FXOS8700_M_VECM_INITX_MSB = 0x6D, /*!< Magnetic vector magnitude X-axis reference value MSB. */
124      FXOS8700_M_VECM_INITX_LSB = 0x6E, /*!< Magnetic vector magnitude X-axis reference value LSB. */
125      FXOS8700_M_VECM_INITY_MSB = 0x6F, /*!< Magnetic vector magnitude Y-axis reference value MSB. */
126      FXOS8700_M_VECM_INITY_LSB = 0x70, /*!< Magnetic vector magnitude Y-axis reference value LSB. */
127      FXOS8700_M_VECM_INITZ_MSB = 0x71, /*!< Magnetic vector magnitude Z-axis reference value MSB. */
128      FXOS8700_M_VECM_INITZ_LSB = 0x72, /*!< Magnetic vector magnitude Z-axis reference value LSB. */
129      FXOS8700_A_FFMT_THS_X_MSB = 0x73, /*!< X-axis FFMT threshold MSB. */
130      FXOS8700_A_FFMT_THS_X_LSB = 0x74, /*!< X-axis FFMT threshold LSB. */
131      FXOS8700_A_FFMT_THS_Y_MSB = 0x75, /*!< Y-axis FFMT threshold MSB. */
132      FXOS8700_A_FFMT_THS_Y_LSB = 0x76, /*!< Y-axis FFMT threshold LSB. */
133      FXOS8700_A_FFMT_THS_Z_MSB = 0x77, /*!< Z-axis FFMT threshold MSB. */
134      FXOS8700_A_FFMT_THS_Z_LSB = 0x78, /*!< Z-axis FFMT threshold LSB. */
135  };
136  
137  #define FXOS8700_DEVICE_ADDR_SA_00           (0x1E)
138  
139  #define FXOS8700_DEVICE_ADDR_SA_01           (0x1D)
140  
141  #define FXOS8700_DEVICE_ADDR_SA_10           (0x1C)
142  
143  #define FXOS8700_DEVICE_ADDR_SA_11           (0x1F)
144  
145  
146  #define FXOS8700_WHO_AM_I_PROD_VALUE (0xC7)
147  
148  
149  /**
150   * The following are the macro definitions to address each bit and its value in the hardware registers.
151   */
152  
153  /*--------------------------------
154  ** Register: DR_STATUS
155  ** Enum: FXOS8700_DR_STATUS
156  ** --
157  ** Offset : 0x00 - Alias for ::FXOS8700_DR_STATUS or ::FXOS8700_F_STATUS.
158  ** ------------------------------*/
159  typedef union {
160      struct {
161          uint8_t                   xdr : 1;
162          uint8_t                   ydr : 1;
163          uint8_t                   zdr : 1;
164          uint8_t                 zyxdr : 1;
165          uint8_t                   xow : 1;
166          uint8_t                   yow : 1;
167          uint8_t                   zow : 1;
168          uint8_t                 zyxow : 1;
169      } b;
170      uint8_t w;
171  } FXOS8700_DR_STATUS_t;
172  
173  
174  /*
175  ** DR_STATUS - Bit field mask definitions
176  */
177  #define FXOS8700_DR_STATUS_XDR_MASK     ((uint8_t) 0x01)
178  #define FXOS8700_DR_STATUS_XDR_SHIFT    ((uint8_t)    0)
179  
180  #define FXOS8700_DR_STATUS_YDR_MASK     ((uint8_t) 0x02)
181  #define FXOS8700_DR_STATUS_YDR_SHIFT    ((uint8_t)    1)
182  
183  #define FXOS8700_DR_STATUS_ZDR_MASK     ((uint8_t) 0x04)
184  #define FXOS8700_DR_STATUS_ZDR_SHIFT    ((uint8_t)    2)
185  
186  #define FXOS8700_DR_STATUS_ZYXDR_MASK   ((uint8_t) 0x08)
187  #define FXOS8700_DR_STATUS_ZYXDR_SHIFT  ((uint8_t)    3)
188  
189  #define FXOS8700_DR_STATUS_XOW_MASK     ((uint8_t) 0x10)
190  #define FXOS8700_DR_STATUS_XOW_SHIFT    ((uint8_t)    4)
191  
192  #define FXOS8700_DR_STATUS_YOW_MASK     ((uint8_t) 0x20)
193  #define FXOS8700_DR_STATUS_YOW_SHIFT    ((uint8_t)    5)
194  
195  #define FXOS8700_DR_STATUS_ZOW_MASK     ((uint8_t) 0x40)
196  #define FXOS8700_DR_STATUS_ZOW_SHIFT    ((uint8_t)    6)
197  
198  #define FXOS8700_DR_STATUS_ZYXOW_MASK   ((uint8_t) 0x80)
199  #define FXOS8700_DR_STATUS_ZYXOW_SHIFT  ((uint8_t)    7)
200  
201  
202  /*
203  ** DR_STATUS - Bit field value definitions
204  */
205  #define FXOS8700_DR_STATUS_XDR_DRDY              ((uint8_t) 0x01)  /*  xdr is set to 1 whenever a new X-axis data         */
206                                                                     /*  acquisition is completed. xdr is cleared anytime   */
207                                                                     /*  the OUT_X_MSB register is read.                    */
208  #define FXOS8700_DR_STATUS_YDR_DRDY              ((uint8_t) 0x02)  /*  ydr is set to 1 whenever a new Y-axis data         */
209                                                                     /*  acquisition is completed. xdr is cleared anytime   */
210                                                                     /*  the OUT_Y_MSB register is read.                    */
211  #define FXOS8700_DR_STATUS_ZDR_DRDY              ((uint8_t) 0x04)  /*  zdr is set to 1 whenever a new Z-axis data         */
212                                                                     /*  acquisition is completed. xdr is cleared anytime   */
213                                                                     /*  the OUT_Z_MSB register is read.                    */
214  #define FXOS8700_DR_STATUS_ZYXDR_DRDY            ((uint8_t) 0x08)  /*  zyxdr signals that a new acquisition for any of    */
215                                                                     /*  the enabled channels is available. zyxdr is        */
216                                                                     /*  cleared when the high-bytes of the acceleration    */
217                                                                     /*  data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) are read.   */
218  #define FXOS8700_DR_STATUS_XOW_OWR               ((uint8_t) 0x10)
219  #define FXOS8700_DR_STATUS_YOW_OWR               ((uint8_t) 0x20)
220  #define FXOS8700_DR_STATUS_ZOW_OWR               ((uint8_t) 0x40)
221  #define FXOS8700_DR_STATUS_ZYXOW_OWR             ((uint8_t) 0x80)
222  /*------------------------------*/
223  
224  
225  
226  /*--------------------------------
227  ** Register: F_STATUS
228  ** Enum: FXOS8700_F_STATUS
229  ** --
230  ** Offset : 0x00 - Fifo Status register
231  ** ------------------------------*/
232  typedef union {
233      struct {
234          uint8_t                 f_cnt : 6; /*  These bits indicate the number of acceleration samples currently stored in */
235                                             /*  the FIFO buffer. Count 0b00_0000 indicates that the FIFO is empty          */
236  
237          uint8_t           f_wmrk_flag : 1;
238          uint8_t                 f_ovf : 1;
239      } b;
240      uint8_t w;
241  } FXOS8700_F_STATUS_t;
242  
243  
244  /*
245  ** F_STATUS - Bit field mask definitions
246  */
247  #define FXOS8700_F_STATUS_F_CNT_MASK         ((uint8_t) 0x3F)
248  #define FXOS8700_F_STATUS_F_CNT_SHIFT        ((uint8_t)    0)
249  
250  #define FXOS8700_F_STATUS_F_WMRK_FLAG_MASK   ((uint8_t) 0x40)
251  #define FXOS8700_F_STATUS_F_WMRK_FLAG_SHIFT  ((uint8_t)    6)
252  
253  #define FXOS8700_F_STATUS_F_OVF_MASK         ((uint8_t) 0x80)
254  #define FXOS8700_F_STATUS_F_OVF_SHIFT        ((uint8_t)    7)
255  
256  
257  /*
258  ** F_STATUS - Bit field value definitions
259  */
260  #define FXOS8700_F_STATUS_F_WMRK_FLAG_NOEVT     ((uint8_t) 0x00)  /*  No FIFO watermark event detected                    */
261  #define FXOS8700_F_STATUS_F_WMRK_FLAG_EVTDET    ((uint8_t) 0x40)
262  #define FXOS8700_F_STATUS_F_OVF_NOOVFL          ((uint8_t) 0x00)  /*  No FIFO overflow events detected                    */
263  #define FXOS8700_F_STATUS_F_OVF_OVFLDET         ((uint8_t) 0x80)  /*  FIFO overflow event detected                        */
264  /*------------------------------*/
265  
266  
267  
268  /*--------------------------------
269  ** Register: OUT_X_MSB
270  ** Enum: FXOS8700_OUT_X_MSB
271  ** --
272  ** Offset : 0x01 - MSB of Accelerometer X value
273  ** ------------------------------*/
274  typedef union {
275      struct {
276          uint8_t                    xd; /*  - 14-bit X-axis measurement data bits 13:6.                                    */
277  
278      } b;
279      uint8_t w;
280  } FXOS8700_OUT_X_MSB_t;
281  
282  
283  /*
284  ** OUT_X_MSB - Bit field mask definitions
285  */
286  #define FXOS8700_OUT_X_MSB_XD_MASK   ((uint8_t) 0xFF)
287  #define FXOS8700_OUT_X_MSB_XD_SHIFT  ((uint8_t)    0)
288  
289  
290  /*------------------------------*/
291  
292  
293  
294  /*--------------------------------
295  ** Register: OUT_X_LSB
296  ** Enum: FXOS8700_OUT_X_LSB
297  ** --
298  ** Offset : 0x02 - LSB of Accelerometer X value
299  ** ------------------------------*/
300  typedef union {
301      struct {
302          uint8_t _reserved_            : 2;
303          uint8_t                    xd : 6; /*  - 14-bit X-axis measurement data bits 5:0.                                 */
304  
305      } b;
306      uint8_t w;
307  } FXOS8700_OUT_X_LSB_t;
308  
309  
310  /*
311  ** OUT_X_LSB - Bit field mask definitions
312  */
313  #define FXOS8700_OUT_X_LSB_XD_MASK   ((uint8_t) 0xFC)
314  #define FXOS8700_OUT_X_LSB_XD_SHIFT  ((uint8_t)    2)
315  
316  
317  /*------------------------------*/
318  
319  
320  
321  /*--------------------------------
322  ** Register: OUT_Y_MSB
323  ** Enum: FXOS8700_OUT_Y_MSB
324  ** --
325  ** Offset : 0x03 - 14-bit Y-axis measurement data bits 13:6.
326  ** ------------------------------*/
327  typedef union {
328      struct {
329          uint8_t                    yd; /*  - 14-bit Y-axis measurement data bits 13:6.                                    */
330  
331      } b;
332      uint8_t w;
333  } FXOS8700_OUT_Y_MSB_t;
334  
335  
336  /*
337  ** OUT_Y_MSB - Bit field mask definitions
338  */
339  #define FXOS8700_OUT_Y_MSB_YD_MASK   ((uint8_t) 0xFF)
340  #define FXOS8700_OUT_Y_MSB_YD_SHIFT  ((uint8_t)    0)
341  
342  
343  /*------------------------------*/
344  
345  
346  
347  /*--------------------------------
348  ** Register: OUT_Y_LSB
349  ** Enum: FXOS8700_OUT_Y_LSB
350  ** --
351  ** Offset : 0x04 - 14-bit Y-axis measurement data bits 5:0.
352  ** ------------------------------*/
353  typedef union {
354      struct {
355          uint8_t _reserved_            : 2;
356          uint8_t                    yd : 6; /*  - 14-bit Y-axis measurement data bits 5:0.                                 */
357  
358      } b;
359      uint8_t w;
360  } FXOS8700_OUT_Y_LSB_t;
361  
362  
363  /*
364  ** OUT_Y_LSB - Bit field mask definitions
365  */
366  #define FXOS8700_OUT_Y_LSB_YD_MASK   ((uint8_t) 0xFC)
367  #define FXOS8700_OUT_Y_LSB_YD_SHIFT  ((uint8_t)    2)
368  
369  
370  /*------------------------------*/
371  
372  
373  
374  /*--------------------------------
375  ** Register: OUT_Z_MSB
376  ** Enum: FXOS8700_OUT_Z_MSB
377  ** --
378  ** Offset : 0x05 - 14-bit Z-axis measurement data bits 13:6.
379  ** ------------------------------*/
380  typedef union {
381      struct {
382          uint8_t                    zd; /*  - 14-bit Z-axis measurement data bits 13:6.                                    */
383  
384      } b;
385      uint8_t w;
386  } FXOS8700_OUT_Z_MSB_t;
387  
388  
389  /*
390  ** OUT_Z_MSB - Bit field mask definitions
391  */
392  #define FXOS8700_OUT_Z_MSB_ZD_MASK   ((uint8_t) 0xFF)
393  #define FXOS8700_OUT_Z_MSB_ZD_SHIFT  ((uint8_t)    0)
394  
395  
396  /*------------------------------*/
397  
398  
399  
400  /*--------------------------------
401  ** Register: OUT_Z_LSB
402  ** Enum: FXOS8700_OUT_Z_LSB
403  ** --
404  ** Offset : 0x06 - 14-bit Z-axis measurement data bits 5:0.
405  ** ------------------------------*/
406  typedef union {
407      struct {
408          uint8_t _reserved_            : 2;
409          uint8_t                    zd : 6; /*  - 14-bit Z-axis measurement data bits 5:0.                                 */
410  
411      } b;
412      uint8_t w;
413  } FXOS8700_OUT_Z_LSB_t;
414  
415  
416  /*
417  ** OUT_Z_LSB - Bit field mask definitions
418  */
419  #define FXOS8700_OUT_Z_LSB_ZD_MASK   ((uint8_t) 0xFC)
420  #define FXOS8700_OUT_Z_LSB_ZD_SHIFT  ((uint8_t)    2)
421  
422  
423  /*------------------------------*/
424  
425  
426  
427  /*--------------------------------
428  ** Register: F_SETUP
429  ** Enum: FXOS8700_F_SETUP
430  ** --
431  ** Offset : 0x09 - FIFO setup.
432  ** ------------------------------*/
433  typedef union {
434      struct {
435          uint8_t                f_wmrk : 6; /*  FIFO sample count watermark                                                */
436  
437          uint8_t                f_mode : 2; /*  - FIFO Buffer operating mode                                               */
438  
439      } b;
440      uint8_t w;
441  } FXOS8700_F_SETUP_t;
442  
443  
444  /*
445  ** F_SETUP - Bit field mask definitions
446  */
447  #define FXOS8700_F_SETUP_F_WMRK_MASK   ((uint8_t) 0x3F)
448  #define FXOS8700_F_SETUP_F_WMRK_SHIFT  ((uint8_t)    0)
449  
450  #define FXOS8700_F_SETUP_F_MODE_MASK   ((uint8_t) 0xC0)
451  #define FXOS8700_F_SETUP_F_MODE_SHIFT  ((uint8_t)    6)
452  
453  
454  /*
455  ** F_SETUP - Bit field value definitions
456  */
457  #define FXOS8700_F_SETUP_F_MODE_FIFO_DISABLE   ((uint8_t) 0x00)  /*  FIFO is disabled                                     */
458  #define FXOS8700_F_SETUP_F_MODE_FIFO_CIRC      ((uint8_t) 0x40)  /*  FIFO contains the most recent samples when           */
459                                                                   /*  overflowed (circular buffer). Oldest sample is       */
460                                                                   /*  discarded to be replaced by new sample               */
461  #define FXOS8700_F_SETUP_F_MODE_FIFO_STOP_OVF  ((uint8_t) 0x80)  /*  FIFO stops accepting new samples when overflowed     */
462  #define FXOS8700_F_SETUP_F_MODE_FIFO_TRIGGER   ((uint8_t) 0xc0)  /*  FIFO trigger mode                                    */
463  /*------------------------------*/
464  
465  
466  
467  /*--------------------------------
468  ** Register: TRIG_CFG
469  ** Enum: FXOS8700_TRIG_CFG
470  ** --
471  ** Offset : 0x0A - FIFO event trigger configuration register.
472  ** ------------------------------*/
473  typedef union {
474      struct {
475          uint8_t _reserved_            : 1;
476          uint8_t           trig_a_vecm : 1;
477          uint8_t           trig_a_ffmt : 1;
478          uint8_t            trig_pulse : 1;
479          uint8_t           trig_lndprt : 1;
480          uint8_t            trig_trans : 1;
481      } b;
482      uint8_t w;
483  } FXOS8700_TRIG_CFG_t;
484  
485  
486  /*
487  ** TRIG_CFG - Bit field mask definitions
488  */
489  #define FXOS8700_TRIG_CFG_TRIG_A_VECM_MASK   ((uint8_t) 0x02)
490  #define FXOS8700_TRIG_CFG_TRIG_A_VECM_SHIFT  ((uint8_t)    1)
491  
492  #define FXOS8700_TRIG_CFG_TRIG_A_FFMT_MASK   ((uint8_t) 0x04)
493  #define FXOS8700_TRIG_CFG_TRIG_A_FFMT_SHIFT  ((uint8_t)    2)
494  
495  #define FXOS8700_TRIG_CFG_TRIG_PULSE_MASK    ((uint8_t) 0x08)
496  #define FXOS8700_TRIG_CFG_TRIG_PULSE_SHIFT   ((uint8_t)    3)
497  
498  #define FXOS8700_TRIG_CFG_TRIG_LNDPRT_MASK   ((uint8_t) 0x10)
499  #define FXOS8700_TRIG_CFG_TRIG_LNDPRT_SHIFT  ((uint8_t)    4)
500  
501  #define FXOS8700_TRIG_CFG_TRIG_TRANS_MASK    ((uint8_t) 0x20)
502  #define FXOS8700_TRIG_CFG_TRIG_TRANS_SHIFT   ((uint8_t)    5)
503  
504  
505  /*
506  ** TRIG_CFG - Bit field value definitions
507  */
508  #define FXOS8700_TRIG_CFG_TRIG_A_VECM_EN        ((uint8_t) 0x02)  /*  Acceleration vector-magnitude FIFO trigger enable   */
509  #define FXOS8700_TRIG_CFG_TRIG_A_VECM_DIS       ((uint8_t) 0x00)  /*  Acceleration vector-magnitude FIFO trigger disable  */
510  #define FXOS8700_TRIG_CFG_TRIG_A_FFMT_EN        ((uint8_t) 0x04)  /*  Freefall/motion interrupt FIFO trigger enable       */
511  #define FXOS8700_TRIG_CFG_TRIG_A_FFMT_DIS       ((uint8_t) 0x00)  /*  Freefall/motion interrupt FIFO trigger disable      */
512  #define FXOS8700_TRIG_CFG_TRIG_PULSE_EN         ((uint8_t) 0x08)  /*  Pluse interrupt FIFO trigger enable                 */
513  #define FXOS8700_TRIG_CFG_TRIG_PULSE_DIS        ((uint8_t) 0x00)  /*  Pluse FIFO trigger enable                           */
514  #define FXOS8700_TRIG_CFG_TRIG_LNDPRT_EN        ((uint8_t) 0x10)  /*  Landscape/portrait orientation interrupt FIFO       */
515                                                                    /*  trigger enable                                      */
516  #define FXOS8700_TRIG_CFG_TRIG_LNDPRT_DIS       ((uint8_t) 0x00)  /*  Landscape/portrait orientation interrupt FIFO       */
517                                                                    /*  trigger disable                                     */
518  #define FXOS8700_TRIG_CFG_TRIG_TRANS_EN         ((uint8_t) 0x20)  /*  Transient interrupt FIFO trigger enable             */
519  #define FXOS8700_TRIG_CFG_TRIG_TRANS_DIS        ((uint8_t) 0x00)  /*  Transient interrupt FIFO trigger disable            */
520  /*------------------------------*/
521  
522  
523  
524  /*--------------------------------
525  ** Register: SYSMOD
526  ** Enum: FXOS8700_SYSMOD
527  ** --
528  ** Offset : 0x0B - Current system mode.
529  ** ------------------------------*/
530  typedef union {
531      struct {
532          uint8_t                sysmod : 2;
533          uint8_t                   fgt : 5;
534          uint8_t                 fgerr : 1;
535      } b;
536      uint8_t w;
537  } FXOS8700_SYSMOD_t;
538  
539  
540  /*
541  ** SYSMOD - Bit field mask definitions
542  */
543  #define FXOS8700_SYSMOD_SYSMOD_MASK   ((uint8_t) 0x03)
544  #define FXOS8700_SYSMOD_SYSMOD_SHIFT  ((uint8_t)    0)
545  
546  #define FXOS8700_SYSMOD_FGT_MASK      ((uint8_t) 0x7C)
547  #define FXOS8700_SYSMOD_FGT_SHIFT     ((uint8_t)    2)
548  
549  #define FXOS8700_SYSMOD_FGERR_MASK    ((uint8_t) 0x80)
550  #define FXOS8700_SYSMOD_FGERR_SHIFT   ((uint8_t)    7)
551  
552  
553  /*
554  ** SYSMOD - Bit field value definitions
555  */
556  #define FXOS8700_SYSMOD_SYSMOD_STANDBY        ((uint8_t) 0x00)  /*  Standby mode                                          */
557  #define FXOS8700_SYSMOD_SYSMOD_WAKE           ((uint8_t) 0x01)  /*  Wake mode                                             */
558  #define FXOS8700_SYSMOD_SYSMOD_SLEEP          ((uint8_t) 0x02)  /*  Sleep mode                                            */
559  /*------------------------------*/
560  
561  
562  
563  
564  /*--------------------------------
565  ** Register: INT_SOURCE
566  ** Enum: FXOS8700_INT_SOURCE
567  ** --
568  ** Offset : 0x0C - Interrupt status.
569  ** ------------------------------*/
570  typedef union {
571      struct {
572          uint8_t              src_drdy : 1;
573          uint8_t            src_a_vecm : 1;
574          uint8_t              src_ffmt : 1;
575          uint8_t             src_pulse : 1;
576          uint8_t            src_lndprt : 1;
577          uint8_t             src_trans : 1;
578          uint8_t              src_fifo : 1;
579          uint8_t              src_aslp : 1;
580      } b;
581      uint8_t w;
582  } FXOS8700_INT_SOURCE_t;
583  
584  
585  /*
586  ** INT_SOURCE - Bit field mask definitions
587  */
588  #define FXOS8700_INT_SOURCE_SRC_DRDY_MASK     ((uint8_t) 0x01)
589  #define FXOS8700_INT_SOURCE_SRC_DRDY_SHIFT    ((uint8_t)    0)
590  
591  #define FXOS8700_INT_SOURCE_SRC_A_VECM_MASK   ((uint8_t) 0x02)
592  #define FXOS8700_INT_SOURCE_SRC_A_VECM_SHIFT  ((uint8_t)    1)
593  
594  #define FXOS8700_INT_SOURCE_SRC_FFMT_MASK     ((uint8_t) 0x04)
595  #define FXOS8700_INT_SOURCE_SRC_FFMT_SHIFT    ((uint8_t)    2)
596  
597  #define FXOS8700_INT_SOURCE_SRC_PULSE_MASK    ((uint8_t) 0x08)
598  #define FXOS8700_INT_SOURCE_SRC_PULSE_SHIFT   ((uint8_t)    3)
599  
600  #define FXOS8700_INT_SOURCE_SRC_LNDPRT_MASK   ((uint8_t) 0x10)
601  #define FXOS8700_INT_SOURCE_SRC_LNDPRT_SHIFT  ((uint8_t)    4)
602  
603  #define FXOS8700_INT_SOURCE_SRC_TRANS_MASK    ((uint8_t) 0x20)
604  #define FXOS8700_INT_SOURCE_SRC_TRANS_SHIFT   ((uint8_t)    5)
605  
606  #define FXOS8700_INT_SOURCE_SRC_FIFO_MASK     ((uint8_t) 0x40)
607  #define FXOS8700_INT_SOURCE_SRC_FIFO_SHIFT    ((uint8_t)    6)
608  
609  #define FXOS8700_INT_SOURCE_SRC_ASLP_MASK     ((uint8_t) 0x80)
610  #define FXOS8700_INT_SOURCE_SRC_ASLP_SHIFT    ((uint8_t)    7)
611  
612  
613  /*------------------------------*/
614  
615  
616  
617  /*--------------------------------
618  ** Register: WHO_AM_I
619  ** Enum: FXOS8700_WHO_AM_I
620  ** --
621  ** Offset : 0x0D - Device ID.
622  ** ------------------------------*/
623  typedef uint8_t FXOS8700_WHO_AM_I_t;
624  
625  
626  
627  /*--------------------------------
628  ** Register: XYZ_DATA_CFG
629  ** Enum: FXOS8700_XYZ_DATA_CFG
630  ** --
631  ** Offset : 0x0E - Acceleration dynamic range and filter enable settings.
632  ** ------------------------------*/
633  typedef union {
634      struct {
635          uint8_t                    fs : 2;
636          uint8_t _reserved_            : 2;
637          uint8_t               hpf_out : 1; /*  - Enable high-pass filter on acceleration output data                      */
638  
639      } b;
640      uint8_t w;
641  } FXOS8700_XYZ_DATA_CFG_t;
642  
643  
644  /*
645  ** XYZ_DATA_CFG - Bit field mask definitions
646  */
647  #define FXOS8700_XYZ_DATA_CFG_FS_MASK        ((uint8_t) 0x03)
648  #define FXOS8700_XYZ_DATA_CFG_FS_SHIFT       ((uint8_t)    0)
649  
650  #define FXOS8700_XYZ_DATA_CFG_HPF_OUT_MASK   ((uint8_t) 0x10)
651  #define FXOS8700_XYZ_DATA_CFG_HPF_OUT_SHIFT  ((uint8_t)    4)
652  
653  
654  /*
655  ** XYZ_DATA_CFG - Bit field value definitions
656  */
657  #define FXOS8700_XYZ_DATA_CFG_HPF_OUT_EN            ((uint8_t) 0x10)  /*  Enable high-pass filter on acceleration output  */
658                                                                        /*  data                                            */
659  #define FXOS8700_XYZ_DATA_CFG_HPF_OUT_DISABLE       ((uint8_t) 0x00)  /*  High-pass filter is disabled                    */
660  #define FXOS8700_XYZ_DATA_CFG_FS_2G_0P244           ((uint8_t) 0x00)  /*  0.244 mg/LSB                                    */
661  #define FXOS8700_XYZ_DATA_CFG_FS_4G_0P488           ((uint8_t) 0x01)  /*  0.488 mg/LSB                                    */
662  #define FXOS8700_XYZ_DATA_CFG_FS_8G_0P976           ((uint8_t) 0x02)  /*  0.976 mg/LSB                                    */
663  /*------------------------------*/
664  
665  
666  
667  /*--------------------------------
668  ** Register: HP_FILTER_CUTOFF
669  ** Enum: FXOS8700_HP_FILTER_CUTOFF
670  ** --
671  ** Offset : 0x0F - Pulse detection highpass and lowpass filter enabling bits.
672  ** ------------------------------*/
673  typedef union {
674      struct {
675          uint8_t                   sel : 2;
676          uint8_t _reserved_            : 2;
677          uint8_t          pulse_lpf_en : 1;
678          uint8_t         pulse_hpf_byp : 1;
679      } b;
680      uint8_t w;
681  } FXOS8700_HP_FILTER_CUTOFF_t;
682  
683  
684  /*
685  ** HP_FILTER_CUTOFF - Bit field mask definitions
686  */
687  #define FXOS8700_HP_FILTER_CUTOFF_SEL_MASK             ((uint8_t) 0x03)
688  #define FXOS8700_HP_FILTER_CUTOFF_SEL_SHIFT            ((uint8_t)    0)
689  
690  #define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK    ((uint8_t) 0x10)
691  #define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT   ((uint8_t)    4)
692  
693  #define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK   ((uint8_t) 0x20)
694  #define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT  ((uint8_t)    5)
695  
696  
697  /*
698  ** HP_FILTER_CUTOFF - Bit field value definitions
699  */
700  #define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_EN      ((uint8_t) 0x00)  /*  HPF enabled for pulse processing            */
701  #define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_BYPASS  ((uint8_t) 0x20)  /*  HPF bypassed for pulse processing           */
702  #define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_EN       ((uint8_t) 0x10)  /*  LPF enabled for pulse processing            */
703  #define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLE  ((uint8_t) 0x00)  /*  LPF bypassed for pulse processing           */
704  #define FXOS8700_HP_FILTER_CUTOFF_SEL_EN                ((uint8_t) 0x01)  /*  HPF cutoff frequency selection Enabled      */
705  #define FXOS8700_HP_FILTER_CUTOFF_SEL_DISABLE           ((uint8_t) 0x00)  /*  HPF cutoff frequency selection Disabled     */
706  /*------------------------------*/
707  
708  
709  
710  /*--------------------------------
711  ** Register: PL_STATUS
712  ** Enum: FXOS8700_PL_STATUS
713  ** --
714  ** Offset : 0x10 - Landscape/portrait orientation status.
715  ** ------------------------------*/
716  typedef union {
717      struct {
718          uint8_t                 bafro : 1;
719          uint8_t                  lapo : 2;
720          uint8_t _reserved_            : 3;
721          uint8_t                    lo : 1;
722          uint8_t                 newlp : 1;
723      } b;
724      uint8_t w;
725  } FXOS8700_PL_STATUS_t;
726  
727  
728  /*
729  ** PL_STATUS - Bit field mask definitions
730  */
731  #define FXOS8700_PL_STATUS_BAFRO_MASK   ((uint8_t) 0x01)
732  #define FXOS8700_PL_STATUS_BAFRO_SHIFT  ((uint8_t)    0)
733  
734  #define FXOS8700_PL_STATUS_LAPO_MASK    ((uint8_t) 0x06)
735  #define FXOS8700_PL_STATUS_LAPO_SHIFT   ((uint8_t)    1)
736  
737  #define FXOS8700_PL_STATUS_LO_MASK      ((uint8_t) 0x40)
738  #define FXOS8700_PL_STATUS_LO_SHIFT     ((uint8_t)    6)
739  
740  #define FXOS8700_PL_STATUS_NEWLP_MASK   ((uint8_t) 0x80)
741  #define FXOS8700_PL_STATUS_NEWLP_SHIFT  ((uint8_t)    7)
742  
743  
744  /*------------------------------*/
745  
746  
747  
748  /*--------------------------------
749  ** Register: PL_CFG
750  ** Enum: FXOS8700_PL_CFG
751  ** --
752  ** Offset : 0x11 - Landscape/portrait configuration.
753  ** ------------------------------*/
754  typedef union {
755      struct {
756          uint8_t _reserved_            : 6;
757          uint8_t                 pl_en : 1;
758          uint8_t                dbcntm : 1;
759      } b;
760      uint8_t w;
761  } FXOS8700_PL_CFG_t;
762  
763  
764  /*
765  ** PL_CFG - Bit field mask definitions
766  */
767  #define FXOS8700_PL_CFG_PL_EN_MASK    ((uint8_t) 0x40)
768  #define FXOS8700_PL_CFG_PL_EN_SHIFT   ((uint8_t)    6)
769  
770  #define FXOS8700_PL_CFG_DBCNTM_MASK   ((uint8_t) 0x80)
771  #define FXOS8700_PL_CFG_DBCNTM_SHIFT  ((uint8_t)    7)
772  
773  
774  /*
775  ** PL_CFG - Bit field value definitions
776  */
777  #define FXOS8700_PL_CFG_DBCNTM_DECREMENT_MODE ((uint8_t) 0x00)  /*  Decrements debounce whenever condition of interest is */
778                                                                  /*  no longer valid                                       */
779  #define FXOS8700_PL_CFG_DBCNTM_CLEAR_MODE     ((uint8_t) 0x80)  /*  Clears counter whenever condition of interest is no   */
780                                                                  /*  longer valid                                          */
781  #define FXOS8700_PL_CFG_PL_EN_DISABLE         ((uint8_t) 0x00)  /*  Portrait/Landscape detection is disabled.             */
782  #define FXOS8700_PL_CFG_PL_EN_ENABLE          ((uint8_t) 0x40)  /*  Portrait/Landscape detection is enabled.              */
783  /*------------------------------*/
784  
785  
786  
787  /*--------------------------------
788  ** Register: PL_COUNT
789  ** Enum: FXOS8700_PL_COUNT
790  ** --
791  ** Offset : 0x12 - Landscape/portrait debounce counter.
792  ** ------------------------------*/
793  typedef union {
794      struct {
795          uint8_t                 dbnce;
796      } b;
797      uint8_t w;
798  } FXOS8700_PL_COUNT_t;
799  
800  
801  /*
802  ** PL_COUNT - Bit field mask definitions
803  */
804  #define FXOS8700_PL_COUNT_DBNCE_MASK   ((uint8_t) 0xFF)
805  #define FXOS8700_PL_COUNT_DBNCE_SHIFT  ((uint8_t)    0)
806  
807  
808  /*------------------------------*/
809  
810  
811  
812  /*--------------------------------
813  ** Register: PL_BF_ZCOMP
814  ** Enum: FXOS8700_PL_BF_ZCOMP
815  ** --
816  ** Offset : 0x13 - Back/front trip angle threshold.
817  ** ------------------------------*/
818  typedef union {
819      struct {
820          uint8_t                 zlock : 3;
821          uint8_t _reserved_            : 3;
822          uint8_t                  bkfr : 2;
823      } b;
824      uint8_t w;
825  } FXOS8700_PL_BF_ZCOMP_t;
826  
827  
828  /*
829  ** PL_BF_ZCOMP - Bit field mask definitions
830  */
831  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_MASK   ((uint8_t) 0x07)
832  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_SHIFT  ((uint8_t)    0)
833  
834  #define FXOS8700_PL_BF_ZCOMP_BKFR_MASK    ((uint8_t) 0xC0)
835  #define FXOS8700_PL_BF_ZCOMP_BKFR_SHIFT   ((uint8_t)    6)
836  
837  
838  /*
839  ** PL_BF_ZCOMP - Bit field value definitions
840  */
841  #define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT80_GT280__FB_LT260_GT100 ((uint8_t) 0x00)
842  #define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT75_GT285__FB_LT255_GT105 ((uint8_t) 0x40)
843  #define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT70_GT290__FB_LT250_GT110 ((uint8_t) 0x80)
844  #define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT65_GT295__FB_LT245_GT115 ((uint8_t) 0xc0)
845  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_13P6MIN_14P5MAX ((uint8_t) 0x00)
846  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_17P1MIN_18P2MAX ((uint8_t) 0x01)
847  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_20P7MIN_22P0MAX ((uint8_t) 0x02)
848  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_24P4MIN_25P9MAX ((uint8_t) 0x04)
849  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_28P1MIN_30P0MAX ((uint8_t) 0x04)
850  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_32P0MIN_34P2MAX ((uint8_t) 0x05)
851  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_36P1MIN_38P7MAX ((uint8_t) 0x06)
852  #define FXOS8700_PL_BF_ZCOMP_ZLOCK_40P4MIN_43P4MAX ((uint8_t) 0x07)
853  /*------------------------------*/
854  
855  
856  
857  /*--------------------------------
858  ** Register: PL_THS_REG
859  ** Enum: FXOS8700_PL_THS_REG
860  ** --
861  ** Offset : 0x14 - Portrait to landscape trip threshold angle and hysteresis settings.
862  ** ------------------------------*/
863  typedef union {
864      struct {
865          uint8_t                   hys : 3;
866          uint8_t                pl_ths : 5;
867      } b;
868      uint8_t w;
869  } FXOS8700_PL_THS_REG_t;
870  
871  
872  /*
873  ** PL_THS_REG - Bit field mask definitions
874  */
875  #define FXOS8700_PL_THS_REG_HYS_MASK      ((uint8_t) 0x07)
876  #define FXOS8700_PL_THS_REG_HYS_SHIFT     ((uint8_t)    0)
877  
878  #define FXOS8700_PL_THS_REG_PL_THS_MASK   ((uint8_t) 0xF8)
879  #define FXOS8700_PL_THS_REG_PL_THS_SHIFT  ((uint8_t)    3)
880  
881  
882  /*
883  ** PL_THS_REG - Bit field value definitions
884  */
885  #define FXOS8700_PL_THS_REG_PL_THS_15DEG          ((uint8_t) 0x38)
886  #define FXOS8700_PL_THS_REG_PL_THS_20DEG          ((uint8_t) 0x48)
887  #define FXOS8700_PL_THS_REG_PL_THS_30DEG          ((uint8_t) 0x60)
888  #define FXOS8700_PL_THS_REG_PL_THS_35DEG          ((uint8_t) 0x68)
889  #define FXOS8700_PL_THS_REG_PL_THS_40DEG          ((uint8_t) 0x78)
890  #define FXOS8700_PL_THS_REG_PL_THS_45DEG          ((uint8_t) 0x80)
891  #define FXOS8700_PL_THS_REG_PL_THS_55DEG          ((uint8_t) 0x98)
892  #define FXOS8700_PL_THS_REG_PL_THS_60DEG          ((uint8_t) 0xa0)
893  #define FXOS8700_PL_THS_REG_PL_THS_70DEG          ((uint8_t) 0xb8)
894  #define FXOS8700_PL_THS_REG_PL_THS_75DEG          ((uint8_t) 0xc8)
895  #define FXOS8700_PL_THS_REG_HYS_LP45_PL45         ((uint8_t) 0x00)
896  #define FXOS8700_PL_THS_REG_HYS_LP49_PL41         ((uint8_t) 0x01)
897  #define FXOS8700_PL_THS_REG_HYS_LP52_PL38         ((uint8_t) 0x02)
898  #define FXOS8700_PL_THS_REG_HYS_LP56_PL34         ((uint8_t) 0x03)
899  #define FXOS8700_PL_THS_REG_HYS_LP59_PL31         ((uint8_t) 0x04)
900  #define FXOS8700_PL_THS_REG_HYS_LP62_PL28         ((uint8_t) 0x05)
901  #define FXOS8700_PL_THS_REG_HYS_LP66_PL24         ((uint8_t) 0x06)
902  #define FXOS8700_PL_THS_REG_HYS_LP69_PL21         ((uint8_t) 0x07)
903  /*------------------------------*/
904  
905  
906  
907  /*--------------------------------
908  ** Register: A_FFMT_CFG
909  ** Enum: FXOS8700_A_FFMT_CFG
910  ** --
911  ** Offset : 0x15 - Freefall/motion function configuration.
912  ** ------------------------------*/
913  typedef union {
914      struct {
915          uint8_t _reserved_            : 3;
916          uint8_t                  xefe : 1;
917          uint8_t                  yefe : 1;
918          uint8_t                  zefe : 1;
919          uint8_t                   oae : 1;
920          uint8_t                   ele : 1;
921      } b;
922      uint8_t w;
923  } FXOS8700_A_FFMT_CFG_t;
924  
925  
926  /*
927  ** A_FFMT_CFG - Bit field mask definitions
928  */
929  #define FXOS8700_A_FFMT_CFG_XEFE_MASK   ((uint8_t) 0x08)
930  #define FXOS8700_A_FFMT_CFG_XEFE_SHIFT  ((uint8_t)    3)
931  
932  #define FXOS8700_A_FFMT_CFG_YEFE_MASK   ((uint8_t) 0x10)
933  #define FXOS8700_A_FFMT_CFG_YEFE_SHIFT  ((uint8_t)    4)
934  
935  #define FXOS8700_A_FFMT_CFG_ZEFE_MASK   ((uint8_t) 0x20)
936  #define FXOS8700_A_FFMT_CFG_ZEFE_SHIFT  ((uint8_t)    5)
937  
938  #define FXOS8700_A_FFMT_CFG_OAE_MASK    ((uint8_t) 0x40)
939  #define FXOS8700_A_FFMT_CFG_OAE_SHIFT   ((uint8_t)    6)
940  
941  #define FXOS8700_A_FFMT_CFG_ELE_MASK    ((uint8_t) 0x80)
942  #define FXOS8700_A_FFMT_CFG_ELE_SHIFT   ((uint8_t)    7)
943  
944  
945  /*
946  ** A_FFMT_CFG - Bit field value definitions
947  */
948  #define FXOS8700_A_FFMT_CFG_ELE_EN                ((uint8_t) 0x80)  /*  Event flag latch enabled                          */
949  #define FXOS8700_A_FFMT_CFG_ELE_DIS               ((uint8_t) 0x00)  /*  Event flag latch disabled                         */
950  #define FXOS8700_A_FFMT_CFG_OAE_FREEFALL          ((uint8_t) 0x00)  /*  Freefall flag                                     */
951  #define FXOS8700_A_FFMT_CFG_OAE_MOTION            ((uint8_t) 0x40)  /*  Motion flag                                       */
952  #define FXOS8700_A_FFMT_CFG_ZEFE_DIS              ((uint8_t) 0x00)  /*  Event detection disabled                          */
953  #define FXOS8700_A_FFMT_CFG_ZEFE_RAISE_EVENT      ((uint8_t) 0x20)  /*  Raise event flag on measured Z-axis acceleration  */
954                                                                      /*  above/below threshold                             */
955  #define FXOS8700_A_FFMT_CFG_YEFE_DIS              ((uint8_t) 0x00)  /*  Event detection disabled                          */
956  #define FXOS8700_A_FFMT_CFG_YEFE_RAISE_EVENT      ((uint8_t) 0x10)  /*  Raise event flag on measured Y-axis acceleration  */
957                                                                      /*  above/below threshold                             */
958  #define FXOS8700_A_FFMT_CFG_XEFE_DIS              ((uint8_t) 0x00)  /*  Event detection disabled                          */
959  #define FXOS8700_A_FFMT_CFG_XEFE_RAISE_EVENT      ((uint8_t) 0x08)  /*  Raise event flag on measured X-axis acceleration  */
960                                                                      /*  above/below threshold                             */
961  /*------------------------------*/
962  
963  
964  
965  /*--------------------------------
966  ** Register: A_FFMT_SRC
967  ** Enum: FXOS8700_A_FFMT_SRC
968  ** --
969  ** Offset : 0x16 - Freefall/motion event source register.
970  ** ------------------------------*/
971  typedef union {
972      struct {
973          uint8_t                   xhp : 1;
974          uint8_t                   xhe : 1;
975          uint8_t                   yhp : 1;
976          uint8_t                   yhe : 1;
977          uint8_t                   zhp : 1;
978          uint8_t                   zhe : 1;
979          uint8_t _reserved_            : 1;
980          uint8_t                    ea : 1;
981      } b;
982      uint8_t w;
983  } FXOS8700_A_FFMT_SRC_t;
984  
985  
986  /*
987  ** A_FFMT_SRC - Bit field mask definitions
988  */
989  #define FXOS8700_A_FFMT_SRC_XHP_MASK   ((uint8_t) 0x01)
990  #define FXOS8700_A_FFMT_SRC_XHP_SHIFT  ((uint8_t)    0)
991  
992  #define FXOS8700_A_FFMT_SRC_XHE_MASK   ((uint8_t) 0x02)
993  #define FXOS8700_A_FFMT_SRC_XHE_SHIFT  ((uint8_t)    1)
994  
995  #define FXOS8700_A_FFMT_SRC_YHP_MASK   ((uint8_t) 0x04)
996  #define FXOS8700_A_FFMT_SRC_YHP_SHIFT  ((uint8_t)    2)
997  
998  #define FXOS8700_A_FFMT_SRC_YHE_MASK   ((uint8_t) 0x08)
999  #define FXOS8700_A_FFMT_SRC_YHE_SHIFT  ((uint8_t)    3)
1000  
1001  #define FXOS8700_A_FFMT_SRC_ZHP_MASK   ((uint8_t) 0x10)
1002  #define FXOS8700_A_FFMT_SRC_ZHP_SHIFT  ((uint8_t)    4)
1003  
1004  #define FXOS8700_A_FFMT_SRC_ZHE_MASK   ((uint8_t) 0x20)
1005  #define FXOS8700_A_FFMT_SRC_ZHE_SHIFT  ((uint8_t)    5)
1006  
1007  #define FXOS8700_A_FFMT_SRC_EA_MASK    ((uint8_t) 0x80)
1008  #define FXOS8700_A_FFMT_SRC_EA_SHIFT   ((uint8_t)    7)
1009  
1010  
1011  /*------------------------------*/
1012  
1013  
1014  
1015  /*--------------------------------
1016  ** Register: A_FFMT_THS
1017  ** Enum: FXOS8700_A_FFMT_THS
1018  ** --
1019  ** Offset : 0x17 - Freefall/motion threshold register.
1020  ** ------------------------------*/
1021  typedef union {
1022      struct {
1023          uint8_t                   ths : 7;
1024          uint8_t                dbcntm : 1;
1025      } b;
1026      uint8_t w;
1027  } FXOS8700_A_FFMT_THS_t;
1028  
1029  
1030  /*
1031  ** A_FFMT_THS - Bit field mask definitions
1032  */
1033  #define FXOS8700_A_FFMT_THS_THS_MASK      ((uint8_t) 0x7F)
1034  #define FXOS8700_A_FFMT_THS_THS_SHIFT     ((uint8_t)    0)
1035  
1036  #define FXOS8700_A_FFMT_THS_DBCNTM_MASK   ((uint8_t) 0x80)
1037  #define FXOS8700_A_FFMT_THS_DBCNTM_SHIFT  ((uint8_t)    7)
1038  
1039  
1040  /*------------------------------*/
1041  
1042  
1043  
1044  /*--------------------------------
1045  ** Register: A_FFMT_COUNT
1046  ** Enum: FXOS8700_A_FFMT_COUNT
1047  ** --
1048  ** Offset : 0x18 - Freefall/motion debounce counter.
1049  ** ------------------------------*/
1050  typedef uint8_t FXOS8700_A_FFMT_COUNT_t;
1051  
1052  
1053  
1054  
1055  /*--------------------------------
1056  ** Register: TRANSIENT_CFG
1057  ** Enum: FXOS8700_TRANSIENT_CFG
1058  ** --
1059  ** Offset : 0x1D - Transient function configuration.
1060  ** ------------------------------*/
1061  typedef union {
1062      struct {
1063          uint8_t               hpf_byp : 1;
1064          uint8_t                 xtefe : 1;
1065          uint8_t                 ytefe : 1;
1066          uint8_t                 ztefe : 1;
1067          uint8_t                  tele : 1;
1068      } b;
1069      uint8_t w;
1070  } FXOS8700_TRANSIENT_CFG_t;
1071  
1072  
1073  /*
1074  ** TRANSIENT_CFG - Bit field mask definitions
1075  */
1076  #define FXOS8700_TRANSIENT_CFG_HPF_BYP_MASK   ((uint8_t) 0x01)
1077  #define FXOS8700_TRANSIENT_CFG_HPF_BYP_SHIFT  ((uint8_t)    0)
1078  
1079  #define FXOS8700_TRANSIENT_CFG_XTEFE_MASK     ((uint8_t) 0x02)
1080  #define FXOS8700_TRANSIENT_CFG_XTEFE_SHIFT    ((uint8_t)    1)
1081  
1082  #define FXOS8700_TRANSIENT_CFG_YTEFE_MASK     ((uint8_t) 0x04)
1083  #define FXOS8700_TRANSIENT_CFG_YTEFE_SHIFT    ((uint8_t)    2)
1084  
1085  #define FXOS8700_TRANSIENT_CFG_ZTEFE_MASK     ((uint8_t) 0x08)
1086  #define FXOS8700_TRANSIENT_CFG_ZTEFE_SHIFT    ((uint8_t)    3)
1087  
1088  #define FXOS8700_TRANSIENT_CFG_TELE_MASK      ((uint8_t) 0x10)
1089  #define FXOS8700_TRANSIENT_CFG_TELE_SHIFT     ((uint8_t)    4)
1090  
1091  
1092  /*
1093  ** TRANSIENT_CFG - Bit field value definitions
1094  */
1095  #define FXOS8700_TRANSIENT_CFG_TELE_EN               ((uint8_t) 0x10)  /*  Event flag latch enabled: the transient        */
1096                                                                         /*  interrupt event flag is latched and a read of  */
1097                                                                         /*  the TRANSIENT_SRC register is required to      */
1098                                                                         /*  clear the event flag                           */
1099  #define FXOS8700_TRANSIENT_CFG_TELE_DIS              ((uint8_t) 0x00)  /*  Event flag latch disabled: the transient       */
1100                                                                         /*  interrupt flag reflects the real-time status   */
1101                                                                         /*  of the function                                */
1102  #define FXOS8700_TRANSIENT_CFG_ZTEFE_EN              ((uint8_t) 0x08)  /*  Z-axis event detection enabled. Raise event    */
1103                                                                         /*  flag on Z-axis acceleration value greater than */
1104                                                                         /*  threshold                                      */
1105  #define FXOS8700_TRANSIENT_CFG_ZTEFE_DIS             ((uint8_t) 0x00)  /*  Z-axis event detection disabled                */
1106  #define FXOS8700_TRANSIENT_CFG_YTEFE_EN              ((uint8_t) 0x04)  /*  Y-axis event detection enabled. Raise event    */
1107                                                                         /*  flag on Y-axis acceleration value greater than */
1108                                                                         /*  threshold                                      */
1109  #define FXOS8700_TRANSIENT_CFG_YTEFE_DIS             ((uint8_t) 0x00)  /*  Y-axis event detection disabled                */
1110  #define FXOS8700_TRANSIENT_CFG_XTEFE_EN              ((uint8_t) 0x02)  /*  X-axis event detection enabled. Raise event    */
1111                                                                         /*  flag on X-axis acceleration value greater than */
1112                                                                         /*  threshold                                      */
1113  #define FXOS8700_TRANSIENT_CFG_XTEFE_DIS             ((uint8_t) 0x00)  /*  X-axis event detection disabled                */
1114  #define FXOS8700_TRANSIENT_CFG_HPF_BYP_EN            ((uint8_t) 0x01)  /*  High-pass filter is not applied to             */
1115                                                                         /*  accelerometer data input to the transient      */
1116                                                                         /*  function                                       */
1117  #define FXOS8700_TRANSIENT_CFG_HPF_BYP_DIS           ((uint8_t) 0x00)  /*  High-pass filter is applied to accelerometer   */
1118                                                                         /*  data input to the transient function           */
1119  /*------------------------------*/
1120  
1121  
1122  
1123  /*--------------------------------
1124  ** Register: TRANSIENT_SRC
1125  ** Enum: FXOS8700_TRANSIENT_SRC
1126  ** --
1127  ** Offset : 0x1E - Transient event status register.
1128  ** ------------------------------*/
1129  typedef union {
1130      struct {
1131          uint8_t            trans_xpol : 1;
1132          uint8_t              tran_xef : 1;
1133          uint8_t             tran_ypol : 1;
1134          uint8_t              tran_yef : 1;
1135          uint8_t             tran_zpol : 1;
1136          uint8_t              tran_zef : 1;
1137          uint8_t               tran_ea : 1;
1138      } b;
1139      uint8_t w;
1140  } FXOS8700_TRANSIENT_SRC_t;
1141  
1142  
1143  /*
1144  ** TRANSIENT_SRC - Bit field mask definitions
1145  */
1146  #define FXOS8700_TRANSIENT_SRC_TRANS_XPOL_MASK   ((uint8_t) 0x01)
1147  #define FXOS8700_TRANSIENT_SRC_TRANS_XPOL_SHIFT  ((uint8_t)    0)
1148  
1149  #define FXOS8700_TRANSIENT_SRC_TRAN_XEF_MASK     ((uint8_t) 0x02)
1150  #define FXOS8700_TRANSIENT_SRC_TRAN_XEF_SHIFT    ((uint8_t)    1)
1151  
1152  #define FXOS8700_TRANSIENT_SRC_TRAN_YPOL_MASK    ((uint8_t) 0x04)
1153  #define FXOS8700_TRANSIENT_SRC_TRAN_YPOL_SHIFT   ((uint8_t)    2)
1154  
1155  #define FXOS8700_TRANSIENT_SRC_TRAN_YEF_MASK     ((uint8_t) 0x08)
1156  #define FXOS8700_TRANSIENT_SRC_TRAN_YEF_SHIFT    ((uint8_t)    3)
1157  
1158  #define FXOS8700_TRANSIENT_SRC_TRAN_ZPOL_MASK    ((uint8_t) 0x10)
1159  #define FXOS8700_TRANSIENT_SRC_TRAN_ZPOL_SHIFT   ((uint8_t)    4)
1160  
1161  #define FXOS8700_TRANSIENT_SRC_TRAN_ZEF_MASK     ((uint8_t) 0x20)
1162  #define FXOS8700_TRANSIENT_SRC_TRAN_ZEF_SHIFT    ((uint8_t)    5)
1163  
1164  #define FXOS8700_TRANSIENT_SRC_TRAN_EA_MASK      ((uint8_t) 0x40)
1165  #define FXOS8700_TRANSIENT_SRC_TRAN_EA_SHIFT     ((uint8_t)    6)
1166  
1167  
1168  /*------------------------------*/
1169  
1170  
1171  
1172  /*--------------------------------
1173  ** Register: TRANSIENT_THS
1174  ** Enum: FXOS8700_TRANSIENT_THS
1175  ** --
1176  ** Offset : 0x1F - Transient event threshold.
1177  ** ------------------------------*/
1178  typedef union {
1179      struct {
1180          uint8_t                tr_ths : 7;
1181          uint8_t             tr_dbcntm : 1;
1182      } b;
1183      uint8_t w;
1184  } FXOS8700_TRANSIENT_THS_t;
1185  
1186  
1187  /*
1188  ** TRANSIENT_THS - Bit field mask definitions
1189  */
1190  #define FXOS8700_TRANSIENT_THS_TR_THS_MASK      ((uint8_t) 0x7F)
1191  #define FXOS8700_TRANSIENT_THS_TR_THS_SHIFT     ((uint8_t)    0)
1192  
1193  #define FXOS8700_TRANSIENT_THS_TR_DBCNTM_MASK   ((uint8_t) 0x80)
1194  #define FXOS8700_TRANSIENT_THS_TR_DBCNTM_SHIFT  ((uint8_t)    7)
1195  
1196  
1197  /*
1198  ** TRANSIENT_THS - Bit field value definitions
1199  */
1200  #define FXOS8700_TRANSIENT_THS_TR_THS_DECREMENTS     ((uint8_t) 0x00)  /*  Decrements debounce counter when the transient */
1201                                                                         /*  event condition is not true during the current */
1202                                                                         /*  ODR period                                     */
1203  #define FXOS8700_TRANSIENT_THS_TR_THS_CLEAR          ((uint8_t) 0x01)  /*  Clears debounce counter when the transient     */
1204                                                                         /*  event condition is not true during the current */
1205                                                                         /*  ODR period                                     */
1206  /*------------------------------*/
1207  
1208  
1209  
1210  /*--------------------------------
1211  ** Register: TRANSIENT_COUNT
1212  ** Enum: FXOS8700_TRANSIENT_COUNT
1213  ** --
1214  ** Offset : 0x20 - Transient debounce counter.
1215  ** ------------------------------*/
1216  typedef uint8_t FXOS8700_TRANSIENT_COUNT_t;
1217  
1218  
1219  
1220  
1221  
1222  /*--------------------------------
1223  ** Register: PULSE_CFG
1224  ** Enum: FXOS8700_PULSE_CFG
1225  ** --
1226  ** Offset : 0x21 - Pulse function configuration.
1227  ** ------------------------------*/
1228  typedef union {
1229      struct {
1230          uint8_t            pls_xspefe : 1;
1231          uint8_t            pls_xdpefe : 1;
1232          uint8_t            pls_yspefe : 1;
1233          uint8_t            pls_ydpefe : 1;
1234          uint8_t            pls_zspefe : 1;
1235          uint8_t            pls_zdpefe : 1;
1236          uint8_t               pls_ele : 1;
1237          uint8_t               pls_dpa : 1;
1238      } b;
1239      uint8_t w;
1240  } FXOS8700_PULSE_CFG_t;
1241  
1242  
1243  /*
1244  ** PULSE_CFG - Bit field mask definitions
1245  */
1246  #define FXOS8700_PULSE_CFG_PLS_XSPEFE_MASK   ((uint8_t) 0x01)
1247  #define FXOS8700_PULSE_CFG_PLS_XSPEFE_SHIFT  ((uint8_t)    0)
1248  
1249  #define FXOS8700_PULSE_CFG_PLS_XDPEFE_MASK   ((uint8_t) 0x02)
1250  #define FXOS8700_PULSE_CFG_PLS_XDPEFE_SHIFT  ((uint8_t)    1)
1251  
1252  #define FXOS8700_PULSE_CFG_PLS_YSPEFE_MASK   ((uint8_t) 0x04)
1253  #define FXOS8700_PULSE_CFG_PLS_YSPEFE_SHIFT  ((uint8_t)    2)
1254  
1255  #define FXOS8700_PULSE_CFG_PLS_YDPEFE_MASK   ((uint8_t) 0x08)
1256  #define FXOS8700_PULSE_CFG_PLS_YDPEFE_SHIFT  ((uint8_t)    3)
1257  
1258  #define FXOS8700_PULSE_CFG_PLS_ZSPEFE_MASK   ((uint8_t) 0x10)
1259  #define FXOS8700_PULSE_CFG_PLS_ZSPEFE_SHIFT  ((uint8_t)    4)
1260  
1261  #define FXOS8700_PULSE_CFG_PLS_ZDPEFE_MASK   ((uint8_t) 0x20)
1262  #define FXOS8700_PULSE_CFG_PLS_ZDPEFE_SHIFT  ((uint8_t)    5)
1263  
1264  #define FXOS8700_PULSE_CFG_PLS_ELE_MASK      ((uint8_t) 0x40)
1265  #define FXOS8700_PULSE_CFG_PLS_ELE_SHIFT     ((uint8_t)    6)
1266  
1267  #define FXOS8700_PULSE_CFG_PLS_DPA_MASK      ((uint8_t) 0x80)
1268  #define FXOS8700_PULSE_CFG_PLS_DPA_SHIFT     ((uint8_t)    7)
1269  
1270  
1271  /*
1272  ** PULSE_CFG - Bit field value definitions
1273  */
1274  #define FXOS8700_PULSE_CFG_PLS_DPA_DIS           ((uint8_t) 0x00)  /*  Setting the pls_dpa bit momentarily suspends the   */
1275                                                                     /*  double-tap detection if the start of a pulse is    */
1276                                                                     /*  detected during the time period specified by the   */
1277                                                                     /*  PULSE_LTCY register and the pulse ends before the  */
1278                                                                     /*  end of the time period specified by the PULSE_LTCY */
1279                                                                     /*  register                                           */
1280  #define FXOS8700_PULSE_CFG_PLS_DPA_EN            ((uint8_t) 0x80)  /*  Double-pulse detection is not aborted if the start */
1281                                                                     /*  of a pulse is detected during the time period      */
1282                                                                     /*  specified by the PULSE_LTCY register               */
1283  #define FXOS8700_PULSE_CFG_PLS_ELE_DIS           ((uint8_t) 0x00)  /*  Event flag latch disabled                          */
1284  #define FXOS8700_PULSE_CFG_PLS_ELE_EN            ((uint8_t) 0x40)  /*  Event flag latch enabled                           */
1285  #define FXOS8700_PULSE_CFG_PLS_ZDPEFE_DIS        ((uint8_t) 0x00)  /*  Event flag latch disabled                          */
1286  #define FXOS8700_PULSE_CFG_PLS_ZDPEFE_EN         ((uint8_t) 0x20)  /*  Raise event flag on detection of double-pulse      */
1287                                                                     /*  event on Z-axis                                    */
1288  #define FXOS8700_PULSE_CFG_PLS_ZSPEFE_DIS        ((uint8_t) 0x00)  /*  Event flag latch disabled                          */
1289  #define FXOS8700_PULSE_CFG_PLS_ZSPEFE_EN         ((uint8_t) 0x10)  /*  Raise event flag on detection of single-pulse      */
1290                                                                     /*  event on Z-axis                                    */
1291  #define FXOS8700_PULSE_CFG_PLS_YDPEFE_DIS        ((uint8_t) 0x00)  /*  Event flag latch disabled                          */
1292  #define FXOS8700_PULSE_CFG_PLS_YDPEFE_EN         ((uint8_t) 0x08)  /*  Raise event flag on detection of double-pulse      */
1293                                                                     /*  event on Y-axis                                    */
1294  #define FXOS8700_PULSE_CFG_PLS_YSPEFE_DIS        ((uint8_t) 0x00)  /*  Event flag latch disabled                          */
1295  #define FXOS8700_PULSE_CFG_PLS_YSPEFE_EN         ((uint8_t) 0x04)  /*  Raise event flag on detection of single-pulse      */
1296                                                                     /*  event on Y-axis                                    */
1297  #define FXOS8700_PULSE_CFG_PLS_XDPEFE_DIS        ((uint8_t) 0x00)  /*  Event flag latch disabled                          */
1298  #define FXOS8700_PULSE_CFG_PLS_XDPEFE_EN         ((uint8_t) 0x02)  /*  Raise event flag on detection of double-pulse      */
1299                                                                     /*  event on X-axis                                    */
1300  #define FXOS8700_PULSE_CFG_PLS_XSPEFE_DIS        ((uint8_t) 0x00)  /*  Event flag latch disabled                          */
1301  #define FXOS8700_PULSE_CFG_PLS_XSPEFE_EN         ((uint8_t) 0x01)  /*  Raise event flag on detection of single-pulse      */
1302                                                                     /*  event on X-axis                                    */
1303  /*------------------------------*/
1304  
1305  
1306  
1307  /*--------------------------------
1308  ** Register: PULSE_SRC
1309  ** Enum: FXOS8700_PULSE_SRC
1310  ** --
1311  ** Offset : 0x22 - Pulse function source register.
1312  ** ------------------------------*/
1313  typedef union {
1314      struct {
1315          uint8_t          pls_src_polx : 1;
1316          uint8_t          pls_src_poly : 1;
1317          uint8_t          pls_src_polz : 1;
1318          uint8_t           pls_src_dpe : 1;
1319          uint8_t           pls_src_axx : 1;
1320          uint8_t           pls_src_axy : 1;
1321          uint8_t           pls_src_axz : 1;
1322          uint8_t            pls_src_ea : 1;
1323      } b;
1324      uint8_t w;
1325  } FXOS8700_PULSE_SRC_t;
1326  
1327  
1328  /*
1329  ** PULSE_SRC - Bit field mask definitions
1330  */
1331  #define FXOS8700_PULSE_SRC_PLS_SRC_POLX_MASK   ((uint8_t) 0x01)
1332  #define FXOS8700_PULSE_SRC_PLS_SRC_POLX_SHIFT  ((uint8_t)    0)
1333  
1334  #define FXOS8700_PULSE_SRC_PLS_SRC_POLY_MASK   ((uint8_t) 0x02)
1335  #define FXOS8700_PULSE_SRC_PLS_SRC_POLY_SHIFT  ((uint8_t)    1)
1336  
1337  #define FXOS8700_PULSE_SRC_PLS_SRC_POLZ_MASK   ((uint8_t) 0x04)
1338  #define FXOS8700_PULSE_SRC_PLS_SRC_POLZ_SHIFT  ((uint8_t)    2)
1339  
1340  #define FXOS8700_PULSE_SRC_PLS_SRC_DPE_MASK    ((uint8_t) 0x08)
1341  #define FXOS8700_PULSE_SRC_PLS_SRC_DPE_SHIFT   ((uint8_t)    3)
1342  
1343  #define FXOS8700_PULSE_SRC_PLS_SRC_AXX_MASK    ((uint8_t) 0x10)
1344  #define FXOS8700_PULSE_SRC_PLS_SRC_AXX_SHIFT   ((uint8_t)    4)
1345  
1346  #define FXOS8700_PULSE_SRC_PLS_SRC_AXY_MASK    ((uint8_t) 0x20)
1347  #define FXOS8700_PULSE_SRC_PLS_SRC_AXY_SHIFT   ((uint8_t)    5)
1348  
1349  #define FXOS8700_PULSE_SRC_PLS_SRC_AXZ_MASK    ((uint8_t) 0x40)
1350  #define FXOS8700_PULSE_SRC_PLS_SRC_AXZ_SHIFT   ((uint8_t)    6)
1351  
1352  #define FXOS8700_PULSE_SRC_PLS_SRC_EA_MASK     ((uint8_t) 0x80)
1353  #define FXOS8700_PULSE_SRC_PLS_SRC_EA_SHIFT    ((uint8_t)    7)
1354  
1355  
1356  /*------------------------------*/
1357  
1358  
1359  
1360  /*--------------------------------
1361  ** Register: PULSE_THSX
1362  ** Enum: FXOS8700_PULSE_THSX
1363  ** --
1364  ** Offset : 0x23 - X-axis pulse threshold.
1365  ** ------------------------------*/
1366  typedef union {
1367      struct {
1368          uint8_t              pls_thsx : 7;
1369      } b;
1370      uint8_t w;
1371  } FXOS8700_PULSE_THSX_t;
1372  
1373  
1374  /*
1375  ** PULSE_THSX - Bit field mask definitions
1376  */
1377  #define FXOS8700_PULSE_THSX_PLS_THSX_MASK   ((uint8_t) 0x7F)
1378  #define FXOS8700_PULSE_THSX_PLS_THSX_SHIFT  ((uint8_t)    0)
1379  
1380  
1381  /*------------------------------*/
1382  
1383  
1384  
1385  /*--------------------------------
1386  ** Register: PULSE_THSY
1387  ** Enum: FXOS8700_PULSE_THSY
1388  ** --
1389  ** Offset : 0x24 - Y-axis pulse threshold.
1390  ** ------------------------------*/
1391  typedef union {
1392      struct {
1393          uint8_t              pls_thsy : 7;
1394      } b;
1395      uint8_t w;
1396  } FXOS8700_PULSE_THSY_t;
1397  
1398  
1399  /*
1400  ** PULSE_THSY - Bit field mask definitions
1401  */
1402  #define FXOS8700_PULSE_THSY_PLS_THSY_MASK   ((uint8_t) 0x7F)
1403  #define FXOS8700_PULSE_THSY_PLS_THSY_SHIFT  ((uint8_t)    0)
1404  
1405  
1406  /*------------------------------*/
1407  
1408  
1409  
1410  /*--------------------------------
1411  ** Register: PULSE_THSZ
1412  ** Enum: FXOS8700_PULSE_THSZ
1413  ** --
1414  ** Offset : 0x25 - Z-axis pulse threshold.
1415  ** ------------------------------*/
1416  typedef union {
1417      struct {
1418          uint8_t              pls_thsz : 7;
1419      } b;
1420      uint8_t w;
1421  } FXOS8700_PULSE_THSZ_t;
1422  
1423  
1424  /*
1425  ** PULSE_THSZ - Bit field mask definitions
1426  */
1427  #define FXOS8700_PULSE_THSZ_PLS_THSZ_MASK   ((uint8_t) 0x7F)
1428  #define FXOS8700_PULSE_THSZ_PLS_THSZ_SHIFT  ((uint8_t)    0)
1429  
1430  
1431  /*------------------------------*/
1432  
1433  
1434  
1435  /*--------------------------------
1436  ** Register: PULSE_TMLT
1437  ** Enum: FXOS8700_PULSE_TMLT
1438  ** --
1439  ** Offset : 0x26 - Time limit for pulse detection.
1440  ** ------------------------------*/
1441  typedef uint8_t FXOS8700_PULSE_TMLT_t;
1442  
1443  
1444  
1445  /*--------------------------------
1446  ** Register: PULSE_LTCY
1447  ** Enum: FXOS8700_PULSE_LTCY
1448  ** --
1449  ** Offset : 0x27 - Latency time for second pulse detection.
1450  ** ------------------------------*/
1451  typedef uint8_t FXOS8700_PULSE_LTCY_t;
1452  
1453  
1454  /*--------------------------------
1455  ** Register: PULSE_WIND
1456  ** Enum: FXOS8700_PULSE_WIND
1457  ** --
1458  ** Offset : 0x28 - Window time for second pulse detection.
1459  ** ------------------------------*/
1460  typedef uint8_t FXOS8700_PULSE_WIND_t;
1461  
1462  
1463  
1464  /*--------------------------------
1465  ** Register: ASLP_COUNT
1466  ** Enum: FXOS8700_ASLP_COUNT
1467  ** --
1468  ** Offset : 0x29 - The counter setting for auto-sleep period.
1469  ** ------------------------------*/
1470  typedef uint8_t FXOS8700_ASLP_COUNT_t;
1471  
1472  
1473  
1474  /*--------------------------------
1475  ** Register: CTRL_REG1
1476  ** Enum: FXOS8700_CTRL_REG1
1477  ** --
1478  ** Offset : 0x2A - System ODR, accelerometer OSR (Output sample rate), operating mode.
1479  ** ------------------------------*/
1480  typedef union {
1481      struct {
1482          uint8_t                active : 1;
1483          uint8_t                f_read : 1;
1484          uint8_t                lnoise : 1;
1485          uint8_t                    dr : 3;
1486          uint8_t             aslp_rate : 2;
1487      } b;
1488      uint8_t w;
1489  } FXOS8700_CTRL_REG1_t;
1490  
1491  
1492  /*
1493  ** CTRL_REG1 - Bit field mask definitions
1494  */
1495  #define FXOS8700_CTRL_REG1_ACTIVE_MASK      ((uint8_t) 0x01)
1496  #define FXOS8700_CTRL_REG1_ACTIVE_SHIFT     ((uint8_t)    0)
1497  
1498  #define FXOS8700_CTRL_REG1_F_READ_MASK      ((uint8_t) 0x02)
1499  #define FXOS8700_CTRL_REG1_F_READ_SHIFT     ((uint8_t)    1)
1500  
1501  #define FXOS8700_CTRL_REG1_LNOISE_MASK      ((uint8_t) 0x04)
1502  #define FXOS8700_CTRL_REG1_LNOISE_SHIFT     ((uint8_t)    2)
1503  
1504  #define FXOS8700_CTRL_REG1_DR_MASK          ((uint8_t) 0x38)
1505  #define FXOS8700_CTRL_REG1_DR_SHIFT         ((uint8_t)    3)
1506  
1507  #define FXOS8700_CTRL_REG1_ASLP_RATE_MASK   ((uint8_t) 0xC0)
1508  #define FXOS8700_CTRL_REG1_ASLP_RATE_SHIFT  ((uint8_t)    6)
1509  
1510  
1511  /*
1512  ** CTRL_REG1 - Bit field value definitions
1513  */
1514  #define FXOS8700_CTRL_REG1_ASLP_RATE_50_HZ       ((uint8_t) 0x00)
1515  #define FXOS8700_CTRL_REG1_ASLP_RATE_12P5_HZ     ((uint8_t) 0x40)
1516  #define FXOS8700_CTRL_REG1_ASLP_RATE_6P25_HZ     ((uint8_t) 0x80)
1517  #define FXOS8700_CTRL_REG1_ASLP_RATE_1P56_HZ     ((uint8_t) 0xc0)
1518  #define FXOS8700_CTRL_REG1_DR_SINGLE_800_HZ      ((uint8_t) 0x00)
1519  #define FXOS8700_CTRL_REG1_DR_SINGLE_400_HZ      ((uint8_t) 0x08)
1520  #define FXOS8700_CTRL_REG1_DR_SINGLE_200_HZ      ((uint8_t) 0x10)
1521  #define FXOS8700_CTRL_REG1_DR_SINGLE_100_HZ      ((uint8_t) 0x18)
1522  #define FXOS8700_CTRL_REG1_DR_SINGLE_50_HZ       ((uint8_t) 0x20)
1523  #define FXOS8700_CTRL_REG1_DR_SINGLE_12P5_HZ     ((uint8_t) 0x28)
1524  #define FXOS8700_CTRL_REG1_DR_SINGLE_6P25_HZ     ((uint8_t) 0x30)
1525  #define FXOS8700_CTRL_REG1_DR_SINGLE_1P5625_HZ   ((uint8_t) 0x38)
1526  #define FXOS8700_CTRL_REG1_DR_HYBRID_400_HZ      ((uint8_t) 0x00)
1527  #define FXOS8700_CTRL_REG1_DR_HYBRID_200_HZ      ((uint8_t) 0x08)
1528  #define FXOS8700_CTRL_REG1_DR_HYBRID_100_HZ      ((uint8_t) 0x10)
1529  #define FXOS8700_CTRL_REG1_DR_HYBRID_50_HZ       ((uint8_t) 0x18)
1530  #define FXOS8700_CTRL_REG1_DR_HYBRID_25_HZ       ((uint8_t) 0x20)
1531  #define FXOS8700_CTRL_REG1_DR_HYBRID_6P25_HZ     ((uint8_t) 0x28)
1532  #define FXOS8700_CTRL_REG1_DR_HYBRID_3P125_HZ    ((uint8_t) 0x30)
1533  #define FXOS8700_CTRL_REG1_DR_HYBRID_0P7813_HZ   ((uint8_t) 0x38)
1534  #define FXOS8700_CTRL_REG1_LNOISE_NORMAL         ((uint8_t) 0x00)  /*  Normal mode                                        */
1535  #define FXOS8700_CTRL_REG1_LNOISE_REDUCED_NOISE  ((uint8_t) 0x04)  /*  Reduced noise mode; Note that the FSR setting is   */
1536                                                                     /*  restricted to ±2 g or ±4 g mode. This feature    */
1537                                                                     /*  cannot be used in ±8 g mode                       */
1538  #define FXOS8700_CTRL_REG1_F_READ_NORMAL         ((uint8_t) 0x00)  /*  Normal mode                                        */
1539  #define FXOS8700_CTRL_REG1_F_READ_FAST           ((uint8_t) 0x02)  /*  Fast-read mode                                     */
1540  #define FXOS8700_CTRL_REG1_ACTIVE_ACTIVE_MODE    ((uint8_t) 0x01)  /*  Active mode                                        */
1541  #define FXOS8700_CTRL_REG1_ACTIVE_STANDBY_MODE   ((uint8_t) 0x00)  /*  Standby mode                                       */
1542  /*------------------------------*/
1543  
1544  
1545  
1546  /*--------------------------------
1547  ** Register: CTRL_REG2
1548  ** Enum: FXOS8700_CTRL_REG2
1549  ** --
1550  ** Offset : 0x2B - Self-test, reset, accelerometer OSR, and sleep mode settings.
1551  ** ------------------------------*/
1552  typedef union {
1553      struct {
1554          uint8_t                  mods : 2;
1555          uint8_t                  slpe : 1;
1556          uint8_t                 smods : 2;
1557          uint8_t _reserved_            : 1;
1558          uint8_t                   rst : 1;
1559          uint8_t                    st : 1;
1560      } b;
1561      uint8_t w;
1562  } FXOS8700_CTRL_REG2_t;
1563  
1564  
1565  /*
1566  ** CTRL_REG2 - Bit field mask definitions
1567  */
1568  #define FXOS8700_CTRL_REG2_MODS_MASK    ((uint8_t) 0x03)
1569  #define FXOS8700_CTRL_REG2_MODS_SHIFT   ((uint8_t)    0)
1570  
1571  #define FXOS8700_CTRL_REG2_SLPE_MASK    ((uint8_t) 0x04)
1572  #define FXOS8700_CTRL_REG2_SLPE_SHIFT   ((uint8_t)    2)
1573  
1574  #define FXOS8700_CTRL_REG2_SMODS_MASK   ((uint8_t) 0x18)
1575  #define FXOS8700_CTRL_REG2_SMODS_SHIFT  ((uint8_t)    3)
1576  
1577  #define FXOS8700_CTRL_REG2_RST_MASK     ((uint8_t) 0x40)
1578  #define FXOS8700_CTRL_REG2_RST_SHIFT    ((uint8_t)    6)
1579  
1580  #define FXOS8700_CTRL_REG2_ST_MASK      ((uint8_t) 0x80)
1581  #define FXOS8700_CTRL_REG2_ST_SHIFT     ((uint8_t)    7)
1582  
1583  
1584  /*
1585  ** CTRL_REG2 - Bit field value definitions
1586  */
1587  #define FXOS8700_CTRL_REG2_ST_DIS                ((uint8_t) 0x00)  /*  Self-test disabled                                 */
1588  #define FXOS8700_CTRL_REG2_ST_EN                 ((uint8_t) 0x80)  /*  Self-test enabled                                  */
1589  #define FXOS8700_CTRL_REG2_RST_EN                ((uint8_t) 0x40)  /*  Device reset enabled                               */
1590  #define FXOS8700_CTRL_REG2_RST_DIS               ((uint8_t) 0x00)  /*  Device reset disabled                              */
1591  #define FXOS8700_CTRL_REG2_SMODS_NORMAL          ((uint8_t) 0x00)
1592  #define FXOS8700_CTRL_REG2_SMODS_LOW_NOISE_LOW_POWER ((uint8_t) 0x08)
1593  #define FXOS8700_CTRL_REG2_SMODS_HIGH_RES        ((uint8_t) 0x10)
1594  #define FXOS8700_CTRL_REG2_SMODS_LOW_POWER       ((uint8_t) 0x18)
1595  #define FXOS8700_CTRL_REG2_SLPE_EN               ((uint8_t) 0x04)
1596  #define FXOS8700_CTRL_REG2_SLPE_DISABLE          ((uint8_t) 0x00)
1597  #define FXOS8700_CTRL_REG2_MODS_NORMAL           ((uint8_t) 0x00)
1598  #define FXOS8700_CTRL_REG2_MODS_LOW_NOISE_LOW_POWER ((uint8_t) 0x01)
1599  #define FXOS8700_CTRL_REG2_MODS_HIGH_RES         ((uint8_t) 0x02)
1600  #define FXOS8700_CTRL_REG2_MODS_LOW_POWER        ((uint8_t) 0x03)
1601  /*------------------------------*/
1602  
1603  
1604  
1605  /*--------------------------------
1606  ** Register: CTRL_REG3
1607  ** Enum: FXOS8700_CTRL_REG3
1608  ** --
1609  ** Offset : 0x2C - Sleep mode interrupt wake enable, interrupt polarity, push-pull/open drain configuration.
1610  ** ------------------------------*/
1611  typedef union {
1612      struct {
1613          uint8_t                 pp_od : 1;
1614          uint8_t                  ipol : 1;
1615          uint8_t           wake_a_vecm : 1;
1616          uint8_t             wake_ffmt : 1;
1617          uint8_t            wake_pulse : 1;
1618          uint8_t           wake_lndprt : 1;
1619          uint8_t            wake_trans : 1;
1620          uint8_t             fifo_gate : 1;
1621      } b;
1622      uint8_t w;
1623  } FXOS8700_CTRL_REG3_t;
1624  
1625  
1626  /*
1627  ** CTRL_REG3 - Bit field mask definitions
1628  */
1629  #define FXOS8700_CTRL_REG3_PP_OD_MASK         ((uint8_t) 0x01)
1630  #define FXOS8700_CTRL_REG3_PP_OD_SHIFT        ((uint8_t)    0)
1631  
1632  #define FXOS8700_CTRL_REG3_IPOL_MASK          ((uint8_t) 0x02)
1633  #define FXOS8700_CTRL_REG3_IPOL_SHIFT         ((uint8_t)    1)
1634  
1635  #define FXOS8700_CTRL_REG3_WAKE_A_VECM_MASK   ((uint8_t) 0x04)
1636  #define FXOS8700_CTRL_REG3_WAKE_A_VECM_SHIFT  ((uint8_t)    2)
1637  
1638  #define FXOS8700_CTRL_REG3_WAKE_FFMT_MASK     ((uint8_t) 0x08)
1639  #define FXOS8700_CTRL_REG3_WAKE_FFMT_SHIFT    ((uint8_t)    3)
1640  
1641  #define FXOS8700_CTRL_REG3_WAKE_PULSE_MASK    ((uint8_t) 0x10)
1642  #define FXOS8700_CTRL_REG3_WAKE_PULSE_SHIFT   ((uint8_t)    4)
1643  
1644  #define FXOS8700_CTRL_REG3_WAKE_LNDPRT_MASK   ((uint8_t) 0x20)
1645  #define FXOS8700_CTRL_REG3_WAKE_LNDPRT_SHIFT  ((uint8_t)    5)
1646  
1647  #define FXOS8700_CTRL_REG3_WAKE_TRANS_MASK    ((uint8_t) 0x40)
1648  #define FXOS8700_CTRL_REG3_WAKE_TRANS_SHIFT   ((uint8_t)    6)
1649  
1650  #define FXOS8700_CTRL_REG3_FIFO_GATE_MASK     ((uint8_t) 0x80)
1651  #define FXOS8700_CTRL_REG3_FIFO_GATE_SHIFT    ((uint8_t)    7)
1652  
1653  
1654  /*
1655  ** CTRL_REG3 - Bit field value definitions
1656  */
1657  #define FXOS8700_CTRL_REG3_FIFO_GATE_BYPASSED    ((uint8_t) 0x00)  /*  FIFO gate is bypassed                              */
1658  #define FXOS8700_CTRL_REG3_FIFO_GATE_BLOCKED     ((uint8_t) 0x80)  /*  The FIFO input buffer is blocked from accepting    */
1659                                                                     /*  new samples when transitioning from wake-to-sleep  */
1660                                                                     /*  mode or from sleep-to-wake mode until the FIFO is  */
1661                                                                     /*  flushed                                            */
1662  #define FXOS8700_CTRL_REG3_WAKE_TRANS_DIS        ((uint8_t) 0x00)  /*  Transient function is disabled in sleep mode       */
1663  #define FXOS8700_CTRL_REG3_WAKE_TRANS_EN         ((uint8_t) 0x40)  /*  Transient function is enabled in sleep mode and    */
1664                                                                     /*  can generate an interrupt to wake the system       */
1665  #define FXOS8700_CTRL_REG3_WAKE_LNDPRT_DIS       ((uint8_t) 0x00)  /*  Orientation function is disabled sleep mode        */
1666  #define FXOS8700_CTRL_REG3_WAKE_LNDPRT_EN        ((uint8_t) 0x20)  /*  Orientation function is enabled in sleep mode and  */
1667                                                                     /*  can generate an interrupt to wake the system       */
1668  #define FXOS8700_CTRL_REG3_WAKE_PULSE_DIS        ((uint8_t) 0x00)  /*  Pulse function is disabled in sleep mode           */
1669  #define FXOS8700_CTRL_REG3_WAKE_PULSE_EN         ((uint8_t) 0x10)  /*  Pulse function is enabled in sleep mode and can    */
1670                                                                     /*  generate an interrupt to wake the system           */
1671  #define FXOS8700_CTRL_REG3_WAKE_FFMT_DIS         ((uint8_t) 0x00)  /*  Freefall/motion function is disabled in sleep mode */
1672  #define FXOS8700_CTRL_REG3_WAKE_FFMT_EN          ((uint8_t) 0x08)  /*  Freefall/motion function is enabled in sleep mode  */
1673                                                                     /*  and can generate an interrupt to wake the system   */
1674  #define FXOS8700_CTRL_REG3_WAKE_A_VECM_DIS       ((uint8_t) 0x00)  /*  Acceleration vector-magnitude function is disabled */
1675                                                                     /*  in sleep mode                                      */
1676  #define FXOS8700_CTRL_REG3_WAKE_A_VECM_EN        ((uint8_t) 0x04)  /*  Acceleration vector-magnitude function is enabled  */
1677                                                                     /*  in sleep mode and can generate an interrupt to     */
1678                                                                     /*  wake the system                                    */
1679  #define FXOS8700_CTRL_REG3_IPOL_ACTIVE_LOW       ((uint8_t) 0x00)  /*  Active Low                                         */
1680  #define FXOS8700_CTRL_REG3_IPOL_ACTIVE_HIGH      ((uint8_t) 0x02)  /*  Active High                                        */
1681  #define FXOS8700_CTRL_REG3_PP_OD_PUSH_PULL       ((uint8_t) 0x00)  /*  Push-pull                                          */
1682  #define FXOS8700_CTRL_REG3_PP_OD_OPEN_DRAIN      ((uint8_t) 0x01)  /*  Open Drain                                         */
1683  /*------------------------------*/
1684  
1685  
1686  
1687  /*--------------------------------
1688  ** Register: CTRL_REG4
1689  ** Enum: FXOS8700_CTRL_REG4
1690  ** --
1691  ** Offset : 0x2D - Interrupt enable register.
1692  ** ------------------------------*/
1693  typedef union {
1694      struct {
1695          uint8_t           int_en_drdy : 1;
1696          uint8_t         int_en_a_vecm : 1;
1697          uint8_t           int_en_ffmt : 1;
1698          uint8_t          int_en_pulse : 1;
1699          uint8_t         int_en_lndprt : 1;
1700          uint8_t          int_en_trans : 1;
1701          uint8_t           int_en_fifo : 1;
1702          uint8_t           int_en_aslp : 1;
1703      } b;
1704      uint8_t w;
1705  } FXOS8700_CTRL_REG4_t;
1706  
1707  
1708  /*
1709  ** CTRL_REG4 - Bit field mask definitions
1710  */
1711  #define FXOS8700_CTRL_REG4_INT_EN_DRDY_MASK     ((uint8_t) 0x01)
1712  #define FXOS8700_CTRL_REG4_INT_EN_DRDY_SHIFT    ((uint8_t)    0)
1713  
1714  #define FXOS8700_CTRL_REG4_INT_EN_A_VECM_MASK   ((uint8_t) 0x02)
1715  #define FXOS8700_CTRL_REG4_INT_EN_A_VECM_SHIFT  ((uint8_t)    1)
1716  
1717  #define FXOS8700_CTRL_REG4_INT_EN_FFMT_MASK     ((uint8_t) 0x04)
1718  #define FXOS8700_CTRL_REG4_INT_EN_FFMT_SHIFT    ((uint8_t)    2)
1719  
1720  #define FXOS8700_CTRL_REG4_INT_EN_PULSE_MASK    ((uint8_t) 0x08)
1721  #define FXOS8700_CTRL_REG4_INT_EN_PULSE_SHIFT   ((uint8_t)    3)
1722  
1723  #define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_MASK   ((uint8_t) 0x10)
1724  #define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_SHIFT  ((uint8_t)    4)
1725  
1726  #define FXOS8700_CTRL_REG4_INT_EN_TRANS_MASK    ((uint8_t) 0x20)
1727  #define FXOS8700_CTRL_REG4_INT_EN_TRANS_SHIFT   ((uint8_t)    5)
1728  
1729  #define FXOS8700_CTRL_REG4_INT_EN_FIFO_MASK     ((uint8_t) 0x40)
1730  #define FXOS8700_CTRL_REG4_INT_EN_FIFO_SHIFT    ((uint8_t)    6)
1731  
1732  #define FXOS8700_CTRL_REG4_INT_EN_ASLP_MASK     ((uint8_t) 0x80)
1733  #define FXOS8700_CTRL_REG4_INT_EN_ASLP_SHIFT    ((uint8_t)    7)
1734  
1735  
1736  /*
1737  ** CTRL_REG4 - Bit field value definitions
1738  */
1739  #define FXOS8700_CTRL_REG4_INT_EN_ASLP_DIS       ((uint8_t) 0x00)  /*  Auto-sleep/wake interrupt disabled                 */
1740  #define FXOS8700_CTRL_REG4_INT_EN_ASLP_EN        ((uint8_t) 0x80)  /*  Auto-sleep/wake interrupt Enabled                  */
1741  #define FXOS8700_CTRL_REG4_INT_EN_FIFO_DIS       ((uint8_t) 0x00)  /*  FIFO interrupt disabled                            */
1742  #define FXOS8700_CTRL_REG4_INT_EN_FIFO_EN        ((uint8_t) 0x40)  /*  FIFO interrupt enabled                             */
1743  #define FXOS8700_CTRL_REG4_INT_EN_TRANS_DIS      ((uint8_t) 0x00)  /*  Transient interrupt disabled                       */
1744  #define FXOS8700_CTRL_REG4_INT_EN_TRANS_EN       ((uint8_t) 0x20)  /*  Transient interrupt enabled                        */
1745  #define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_DIS     ((uint8_t) 0x00)  /*  Orientation (landscape/portrait) interrupt         */
1746                                                                     /*  disabled                                           */
1747  #define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_EN      ((uint8_t) 0x10)  /*  Orientation (landscape/portrait) interrupt enabled */
1748  #define FXOS8700_CTRL_REG4_INT_EN_PULSE_DIS      ((uint8_t) 0x00)  /*  Pulse detection interrupt disabled                 */
1749  #define FXOS8700_CTRL_REG4_INT_EN_PULSE_EN       ((uint8_t) 0x08)  /*  Pulse detection interrupt enabled                  */
1750  #define FXOS8700_CTRL_REG4_INT_EN_FFMT_DIS       ((uint8_t) 0x00)  /*  Freefall/motion interrupt disabled                 */
1751  #define FXOS8700_CTRL_REG4_INT_EN_FFMT_EN        ((uint8_t) 0x04)  /*  Freefall/motion interrupt enabled                  */
1752  #define FXOS8700_CTRL_REG4_INT_EN_A_VECM_DIS     ((uint8_t) 0x00)  /*  Acceleration vector-magnitude interrupt disabled   */
1753  #define FXOS8700_CTRL_REG4_INT_EN_A_VECM_EN      ((uint8_t) 0x02)  /*  Acceleration vector-magnitude interrupt disabled   */
1754  #define FXOS8700_CTRL_REG4_INT_EN_DRDY_DIS       ((uint8_t) 0x00)  /*  Data-ready interrupt disabled                      */
1755  #define FXOS8700_CTRL_REG4_INT_EN_DRDY_EN        ((uint8_t) 0x01)  /*  Data-ready interrupt Enabled                       */
1756  /*------------------------------*/
1757  
1758  
1759  
1760  /*--------------------------------
1761  ** Register: CTRL_REG5
1762  ** Enum: FXOS8700_CTRL_REG5
1763  ** --
1764  ** Offset : 0x2E - Interrupt pin (INT1/INT2) map.
1765  ** ------------------------------*/
1766  typedef union {
1767      struct {
1768          uint8_t          int_cfg_drdy : 1;
1769          uint8_t        int_cfg_a_vecm : 1;
1770          uint8_t          int_cfg_ffmt : 1;
1771          uint8_t         int_cfg_pulse : 1;
1772          uint8_t        int_cfg_lndprt : 1;
1773          uint8_t         int_cfg_trans : 1;
1774          uint8_t          int_cfg_fifo : 1;
1775          uint8_t          int_cfg_aslp : 1;
1776      } b;
1777      uint8_t w;
1778  } FXOS8700_CTRL_REG5_t;
1779  
1780  
1781  /*
1782  ** CTRL_REG5 - Bit field mask definitions
1783  */
1784  #define FXOS8700_CTRL_REG5_INT_CFG_DRDY_MASK     ((uint8_t) 0x01)
1785  #define FXOS8700_CTRL_REG5_INT_CFG_DRDY_SHIFT    ((uint8_t)    0)
1786  
1787  #define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_MASK   ((uint8_t) 0x02)
1788  #define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_SHIFT  ((uint8_t)    1)
1789  
1790  #define FXOS8700_CTRL_REG5_INT_CFG_FFMT_MASK     ((uint8_t) 0x04)
1791  #define FXOS8700_CTRL_REG5_INT_CFG_FFMT_SHIFT    ((uint8_t)    2)
1792  
1793  #define FXOS8700_CTRL_REG5_INT_CFG_PULSE_MASK    ((uint8_t) 0x08)
1794  #define FXOS8700_CTRL_REG5_INT_CFG_PULSE_SHIFT   ((uint8_t)    3)
1795  
1796  #define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_MASK   ((uint8_t) 0x10)
1797  #define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_SHIFT  ((uint8_t)    4)
1798  
1799  #define FXOS8700_CTRL_REG5_INT_CFG_TRANS_MASK    ((uint8_t) 0x20)
1800  #define FXOS8700_CTRL_REG5_INT_CFG_TRANS_SHIFT   ((uint8_t)    5)
1801  
1802  #define FXOS8700_CTRL_REG5_INT_CFG_FIFO_MASK     ((uint8_t) 0x40)
1803  #define FXOS8700_CTRL_REG5_INT_CFG_FIFO_SHIFT    ((uint8_t)    6)
1804  
1805  #define FXOS8700_CTRL_REG5_INT_CFG_ASLP_MASK     ((uint8_t) 0x80)
1806  #define FXOS8700_CTRL_REG5_INT_CFG_ASLP_SHIFT    ((uint8_t)    7)
1807  
1808  
1809  /*
1810  ** CTRL_REG5 - Bit field value definitions
1811  */
1812  #define FXOS8700_CTRL_REG5_INT_CFG_ASLP_INT2     ((uint8_t) 0x00)  /*  Interrupt is routed to INT2 pin                    */
1813  #define FXOS8700_CTRL_REG5_INT_CFG_ASLP_INT1     ((uint8_t) 0x80)  /*  Interrupt is routed to INT1 pin                    */
1814  #define FXOS8700_CTRL_REG5_INT_CFG_FIFO_INT2     ((uint8_t) 0x00)  /*  Interrupt is routed to INT2 pin                    */
1815  #define FXOS8700_CTRL_REG5_INT_CFG_FIFO_INT1     ((uint8_t) 0x40)  /*  Interrupt is routed to INT1 pin                    */
1816  #define FXOS8700_CTRL_REG5_INT_CFG_TRANS_INT2    ((uint8_t) 0x00)  /*  Interrupt is routed to INT2 pin                    */
1817  #define FXOS8700_CTRL_REG5_INT_CFG_TRANS_INT1    ((uint8_t) 0x20)  /*  Interrupt is routed to INT1 pin                    */
1818  #define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_INT2   ((uint8_t) 0x00)  /*  Interrupt is routed to INT2 pin                    */
1819  #define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_INT1   ((uint8_t) 0x10)  /*  Interrupt is routed to INT1 pin                    */
1820  #define FXOS8700_CTRL_REG5_INT_CFG_PULSE_INT2    ((uint8_t) 0x00)  /*  Interrupt is routed to INT2 pin                    */
1821  #define FXOS8700_CTRL_REG5_INT_CFG_PULSE_INT1    ((uint8_t) 0x08)  /*  Interrupt is routed to INT1 pin                    */
1822  #define FXOS8700_CTRL_REG5_INT_CFG_FFMT_INT2     ((uint8_t) 0x00)  /*  Interrupt is routed to INT2 pin                    */
1823  #define FXOS8700_CTRL_REG5_INT_CFG_FFMT_INT1     ((uint8_t) 0x04)  /*  Interrupt is routed to INT1 pin                    */
1824  #define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_INT2   ((uint8_t) 0x00)  /*  Interrupt is routed to INT2 pin                    */
1825  #define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_INT1   ((uint8_t) 0x02)  /*  Interrupt is routed to INT1 pin                    */
1826  #define FXOS8700_CTRL_REG5_INT_CFG_DRDY_INT2     ((uint8_t) 0x00)  /*  Interrupt is routed to INT2 pin                    */
1827  #define FXOS8700_CTRL_REG5_INT_CFG_DRDY_INT1     ((uint8_t) 0x01)  /*  Interrupt is routed to INT1 pin                    */
1828  /*------------------------------*/
1829  
1830  
1831  
1832  /*--------------------------------
1833  ** Register: OFF_X
1834  ** Enum: FXOS8700_OFF_X
1835  ** --
1836  ** Offset : 0x2F - X-axis accelerometer offset adjust.
1837  ** ------------------------------*/
1838  typedef uint8_t FXOS8700_OFF_X_t;
1839  
1840  
1841  /*--------------------------------
1842  ** Register: OFF_Y
1843  ** Enum: FXOS8700_OFF_Y
1844  ** --
1845  ** Offset : 0x30 - Y-axis accelerometer offset adjust.
1846  ** ------------------------------*/
1847  typedef uint8_t FXOS8700_OFF_Y_t;
1848  
1849  
1850  /*--------------------------------
1851  ** Register: OFF_Z
1852  ** Enum: FXOS8700_OFF_Z
1853  ** --
1854  ** Offset : 0x31 - Z-axis accelerometer offset adjust.
1855  ** ------------------------------*/
1856  typedef uint8_t FXOS8700_OFF_Z_t;
1857  
1858  
1859  
1860  /*--------------------------------
1861  ** Register: M_DR_STATUS
1862  ** Enum: FXOS8700_M_DR_STATUS
1863  ** --
1864  ** Offset : 0x32 - The magnetometer data ready status.
1865  ** ------------------------------*/
1866  typedef union {
1867      struct {
1868          uint8_t                   xdr : 1;
1869          uint8_t                   ydr : 1;
1870          uint8_t                   zdr : 1;
1871          uint8_t                 zyxdr : 1;
1872          uint8_t                   xow : 1;
1873          uint8_t                   yow : 1;
1874          uint8_t                   zow : 1;
1875          uint8_t                 zyxow : 1;
1876      } b;
1877      uint8_t w;
1878  } FXOS8700_M_DR_STATUS_t;
1879  
1880  
1881  /*
1882  ** M_DR_STATUS - Bit field mask definitions
1883  */
1884  #define FXOS8700_M_DR_STATUS_XDR_MASK     ((uint8_t) 0x01)
1885  #define FXOS8700_M_DR_STATUS_XDR_SHIFT    ((uint8_t)    0)
1886  
1887  #define FXOS8700_M_DR_STATUS_YDR_MASK     ((uint8_t) 0x02)
1888  #define FXOS8700_M_DR_STATUS_YDR_SHIFT    ((uint8_t)    1)
1889  
1890  #define FXOS8700_M_DR_STATUS_ZDR_MASK     ((uint8_t) 0x04)
1891  #define FXOS8700_M_DR_STATUS_ZDR_SHIFT    ((uint8_t)    2)
1892  
1893  #define FXOS8700_M_DR_STATUS_ZYXDR_MASK   ((uint8_t) 0x08)
1894  #define FXOS8700_M_DR_STATUS_ZYXDR_SHIFT  ((uint8_t)    3)
1895  
1896  #define FXOS8700_M_DR_STATUS_XOW_MASK     ((uint8_t) 0x10)
1897  #define FXOS8700_M_DR_STATUS_XOW_SHIFT    ((uint8_t)    4)
1898  
1899  #define FXOS8700_M_DR_STATUS_YOW_MASK     ((uint8_t) 0x20)
1900  #define FXOS8700_M_DR_STATUS_YOW_SHIFT    ((uint8_t)    5)
1901  
1902  #define FXOS8700_M_DR_STATUS_ZOW_MASK     ((uint8_t) 0x40)
1903  #define FXOS8700_M_DR_STATUS_ZOW_SHIFT    ((uint8_t)    6)
1904  
1905  #define FXOS8700_M_DR_STATUS_ZYXOW_MASK   ((uint8_t) 0x80)
1906  #define FXOS8700_M_DR_STATUS_ZYXOW_SHIFT  ((uint8_t)    7)
1907  
1908  
1909  /*------------------------------*/
1910  
1911  
1912  
1913  /*--------------------------------
1914  ** Register: M_OUT_X_MSB
1915  ** Enum: FXOS8700_M_OUT_X_MSB
1916  ** --
1917  ** Offset : 0x33 - MSB of the 16-bit magnetometer data for X-axis.
1918  ** ------------------------------*/
1919  typedef uint8_t FXOS8700_M_OUT_X_MSB_t;
1920  
1921  
1922  /*--------------------------------
1923  ** Register: M_OUT_X_LSB
1924  ** Enum: FXOS8700_M_OUT_X_LSB
1925  ** --
1926  ** Offset : 0x34 - LSB of the 16-bit magnetometer data for X-axis.
1927  ** ------------------------------*/
1928  typedef uint8_t FXOS8700_M_OUT_X_LSB_t;
1929  
1930  
1931  /*--------------------------------
1932  ** Register: M_OUT_Y_MSB
1933  ** Enum: FXOS8700_M_OUT_Y_MSB
1934  ** --
1935  ** Offset : 0x35 - MSB of the 16-bit magnetometer data for Y-axis.
1936  ** ------------------------------*/
1937  typedef uint8_t FXOS8700_M_OUT_Y_MSB_t;
1938  
1939  
1940  /*--------------------------------
1941  ** Register: M_OUT_Y_LSB
1942  ** Enum: FXOS8700_M_OUT_Y_LSB
1943  ** --
1944  ** Offset : 0x36 - LSB of the 16-bit magnetometer data for Y-axis.
1945  ** ------------------------------*/
1946  typedef uint8_t FXOS8700_M_OUT_Y_LSB_t;
1947  
1948  
1949  /*--------------------------------
1950  ** Register: M_OUT_Z_MSB
1951  ** Enum: FXOS8700_M_OUT_Z_MSB
1952  ** --
1953  ** Offset : 0x37 - MSB of the 16-bit magnetometer data for Z-axis.
1954  ** ------------------------------*/
1955  typedef uint8_t FXOS8700_M_OUT_Z_MSB_t;
1956  
1957  
1958  /*--------------------------------
1959  ** Register: M_OUT_Z_LSB
1960  ** Enum: FXOS8700_M_OUT_Z_LSB
1961  ** --
1962  ** Offset : 0x38 - LSB of the 16-bit magnetometer data for Z-axis.
1963  ** ------------------------------*/
1964  typedef uint8_t FXOS8700_M_OUT_Z_LSB_t;
1965  
1966  
1967  
1968  /*--------------------------------
1969  ** Register: CMP_X_MSB
1970  ** Enum: FXOS8700_CMP_X_MSB
1971  ** --
1972  ** Offset : 0x39 - Bits [13:8] of integrated X-axis acceleration data.
1973  ** ------------------------------*/
1974  typedef union {
1975      struct {
1976          uint8_t                 cmp_x : 6;
1977      } b;
1978      uint8_t w;
1979  } FXOS8700_CMP_X_MSB_t;
1980  
1981  
1982  /*
1983  ** CMP_X_MSB - Bit field mask definitions
1984  */
1985  #define FXOS8700_CMP_X_MSB_CMP_X_MASK   ((uint8_t) 0x3F)
1986  #define FXOS8700_CMP_X_MSB_CMP_X_SHIFT  ((uint8_t)    0)
1987  
1988  
1989  /*------------------------------*/
1990  
1991  
1992  
1993  /*--------------------------------
1994  ** Register: CMP_X_LSB
1995  ** Enum: FXOS8700_CMP_X_LSB
1996  ** --
1997  ** Offset : 0x3A - Bits [7:0] of integrated X-axis acceleration data.
1998  ** ------------------------------*/
1999  typedef uint8_t FXOS8700_CMP_X_LSB_t;
2000  
2001  
2002  /*--------------------------------
2003  ** Register: CMP_Y_MSB
2004  ** Enum: FXOS8700_CMP_Y_MSB
2005  ** --
2006  ** Offset : 0x3B - Bits [13:8] of integrated Y-axis acceleration data.
2007  ** ------------------------------*/
2008  typedef union {
2009      struct {
2010          uint8_t                 cmp_y : 6;
2011      } b;
2012      uint8_t w;
2013  } FXOS8700_CMP_Y_MSB_t;
2014  
2015  
2016  /*
2017  ** CMP_Y_MSB - Bit field mask definitions
2018  */
2019  #define FXOS8700_CMP_Y_MSB_CMP_Y_MASK   ((uint8_t) 0x3F)
2020  #define FXOS8700_CMP_Y_MSB_CMP_Y_SHIFT  ((uint8_t)    0)
2021  
2022  
2023  /*------------------------------*/
2024  
2025  
2026  
2027  /*--------------------------------
2028  ** Register: CMP_Y_LSB
2029  ** Enum: FXOS8700_CMP_Y_LSB
2030  ** --
2031  ** Offset : 0x3C - Bits [7:0] of integrated Y-axis acceleration data.
2032  ** ------------------------------*/
2033  typedef uint8_t FXOS8700_CMP_Y_LSB_t;
2034  
2035  
2036  /*--------------------------------
2037  ** Register: CMP_Z_MSB
2038  ** Enum: FXOS8700_CMP_Z_MSB
2039  ** --
2040  ** Offset : 0x3D - Bits [13:8] of integrated Z-axis acceleration data.
2041  ** ------------------------------*/
2042  typedef union {
2043      struct {
2044          uint8_t                 cmp_z : 6;
2045      } b;
2046      uint8_t w;
2047  } FXOS8700_CMP_Z_MSB_t;
2048  
2049  
2050  /*
2051  ** CMP_Z_MSB - Bit field mask definitions
2052  */
2053  #define FXOS8700_CMP_Z_MSB_CMP_Z_MASK   ((uint8_t) 0x3F)
2054  #define FXOS8700_CMP_Z_MSB_CMP_Z_SHIFT  ((uint8_t)    0)
2055  
2056  
2057  /*------------------------------*/
2058  
2059  
2060  
2061  /*--------------------------------
2062  ** Register: CMP_Z_LSB
2063  ** Enum: FXOS8700_CMP_Z_LSB
2064  ** --
2065  ** Offset : 0x3E - Bits [7:0] of integrated Z-axis acceleration data.
2066  ** ------------------------------*/
2067  typedef uint8_t FXOS8700_CMP_Z_LSB_t;
2068  
2069  
2070  /*--------------------------------
2071  ** Register: M_OFF_X_MSB
2072  ** Enum: FXOS8700_M_OFF_X_MSB
2073  ** --
2074  ** Offset : 0x3F - MSB of magnetometer X-axis offset.
2075  ** ------------------------------*/
2076  typedef uint8_t FXOS8700_M_OFF_X_MSB_t;
2077  
2078  
2079  /*--------------------------------
2080  ** Register: M_OFF_X_LSB
2081  ** Enum: FXOS8700_M_OFF_X_LSB
2082  ** --
2083  ** Offset : 0x40 - LSB of magnetometer X-axis offset.
2084  ** ------------------------------*/
2085  typedef union {
2086      struct {
2087          uint8_t _reserved_            : 1;
2088          uint8_t               m_off_x : 7;
2089      } b;
2090      uint8_t w;
2091  } FXOS8700_M_OFF_X_LSB_t;
2092  
2093  
2094  /*
2095  ** M_OFF_X_LSB - Bit field mask definitions
2096  */
2097  #define FXOS8700_M_OFF_X_LSB_M_OFF_X_MASK   ((uint8_t) 0xFE)
2098  #define FXOS8700_M_OFF_X_LSB_M_OFF_X_SHIFT  ((uint8_t)    1)
2099  
2100  
2101  /*------------------------------*/
2102  
2103  
2104  
2105  /*--------------------------------
2106  ** Register: M_OFF_Y_MSB
2107  ** Enum: FXOS8700_M_OFF_Y_MSB
2108  ** --
2109  ** Offset : 0x41 - MSB of magnetometer Y-axis offset.
2110  ** ------------------------------*/
2111  typedef uint8_t FXOS8700_M_OFF_Y_MSB_t;
2112  
2113  
2114  /*--------------------------------
2115  ** Register: M_OFF_Y_LSB
2116  ** Enum: FXOS8700_M_OFF_Y_LSB
2117  ** --
2118  ** Offset : 0x42 - LSB of magnetometer Y-axis offset.
2119  ** ------------------------------*/
2120  typedef union {
2121      struct {
2122          uint8_t _reserved_            : 1;
2123          uint8_t               m_off_y : 7;
2124      } b;
2125      uint8_t w;
2126  } FXOS8700_M_OFF_Y_LSB_t;
2127  
2128  
2129  /*
2130  ** M_OFF_Y_LSB - Bit field mask definitions
2131  */
2132  #define FXOS8700_M_OFF_Y_LSB_M_OFF_Y_MASK   ((uint8_t) 0xFE)
2133  #define FXOS8700_M_OFF_Y_LSB_M_OFF_Y_SHIFT  ((uint8_t)    1)
2134  
2135  
2136  /*------------------------------*/
2137  
2138  
2139  
2140  /*--------------------------------
2141  ** Register: M_OFF_Z_MSB
2142  ** Enum: FXOS8700_M_OFF_Z_MSB
2143  ** --
2144  ** Offset : 0x43 - MSB of magnetometer Z-axis offset.
2145  ** ------------------------------*/
2146  typedef uint8_t FXOS8700_M_OFF_Z_MSB_t;
2147  
2148  
2149  /*--------------------------------
2150  ** Register: M_OFF_Z_LSB
2151  ** Enum: FXOS8700_M_OFF_Z_LSB
2152  ** --
2153  ** Offset : 0x44 - LSB of magnetometer Z-axis offset.
2154  ** ------------------------------*/
2155  typedef union {
2156      struct {
2157          uint8_t _reserved_            : 1;
2158          uint8_t               m_off_z : 7;
2159      } b;
2160      uint8_t w;
2161  } FXOS8700_M_OFF_Z_LSB_t;
2162  
2163  
2164  /*
2165  ** M_OFF_Z_LSB - Bit field mask definitions
2166  */
2167  #define FXOS8700_M_OFF_Z_LSB_M_OFF_Z_MASK   ((uint8_t) 0xFE)
2168  #define FXOS8700_M_OFF_Z_LSB_M_OFF_Z_SHIFT  ((uint8_t)    1)
2169  
2170  
2171  /*------------------------------*/
2172  
2173  
2174  
2175  /*--------------------------------
2176  ** Register: MAX_X_MSB
2177  ** Enum: FXOS8700_MAX_X_MSB
2178  ** --
2179  ** Offset : 0x45 - Magnetometer X-axis maximum value MSB.
2180  ** ------------------------------*/
2181  typedef uint8_t FXOS8700_MAX_X_MSB_t;
2182  
2183  
2184  /*--------------------------------
2185  ** Register: MAX_X_LSB
2186  ** Enum: FXOS8700_MAX_X_LSB
2187  ** --
2188  ** Offset : 0x46 - Magnetometer X-axis maximum value LSB.
2189  ** ------------------------------*/
2190  typedef uint8_t FXOS8700_MAX_X_LSB_t;
2191  
2192  
2193  /*--------------------------------
2194  ** Register: MAX_Y_MSB
2195  ** Enum: FXOS8700_MAX_Y_MSB
2196  ** --
2197  ** Offset : 0x47 - Magnetometer Y-axis maximum value MSB.
2198  ** ------------------------------*/
2199  typedef uint8_t FXOS8700_MAX_Y_MSB_t;
2200  
2201  
2202  /*--------------------------------
2203  ** Register: MAX_Y_LSB
2204  ** Enum: FXOS8700_MAX_Y_LSB
2205  ** --
2206  ** Offset : 0x48 - Magnetometer Y-axis maximum value LSB.
2207  ** ------------------------------*/
2208  typedef uint8_t FXOS8700_MAX_Y_LSB_t;
2209  
2210  
2211  /*--------------------------------
2212  ** Register: MAX_Z_MSB
2213  ** Enum: FXOS8700_MAX_Z_MSB
2214  ** --
2215  ** Offset : 0x49 - Magnetometer Z-axis maximum value MSB.
2216  ** ------------------------------*/
2217  typedef uint8_t FXOS8700_MAX_Z_MSB_t;
2218  
2219  
2220  /*--------------------------------
2221  ** Register: MAX_Z_LSB
2222  ** Enum: FXOS8700_MAX_Z_LSB
2223  ** --
2224  ** Offset : 0x4A - Magnetometer Z-axis maximum value LSB.
2225  ** ------------------------------*/
2226  typedef uint8_t FXOS8700_MAX_Z_LSB_t;
2227  
2228  
2229  /*--------------------------------
2230  ** Register: MIN_X_MSB
2231  ** Enum: FXOS8700_MIN_X_MSB
2232  ** --
2233  ** Offset : 0x4B - Magnetometer X-axis minimum value MSB.
2234  ** ------------------------------*/
2235  typedef uint8_t FXOS8700_MIN_X_MSB_t;
2236  
2237  
2238  /*--------------------------------
2239  ** Register: MIN_X_LSB
2240  ** Enum: FXOS8700_MIN_X_LSB
2241  ** --
2242  ** Offset : 0x4C - Magnetometer X-axis minimum value LSB.
2243  ** ------------------------------*/
2244  typedef uint8_t FXOS8700_MIN_X_LSB_t;
2245  
2246  
2247  /*--------------------------------
2248  ** Register: MIN_Y_MSB
2249  ** Enum: FXOS8700_MIN_Y_MSB
2250  ** --
2251  ** Offset : 0x4D - Magnetometer Y-axis minimum value MSB.
2252  ** ------------------------------*/
2253  typedef uint8_t FXOS8700_MIN_Y_MSB_t;
2254  
2255  
2256  /*--------------------------------
2257  ** Register: MIN_Y_LSB
2258  ** Enum: FXOS8700_MIN_Y_LSB
2259  ** --
2260  ** Offset : 0x4E - Magnetometer Y-axis minimum value LSB.
2261  ** ------------------------------*/
2262  typedef uint8_t FXOS8700_MIN_Y_LSB_t;
2263  
2264  
2265  /*--------------------------------
2266  ** Register: MIN_Z_MSB
2267  ** Enum: FXOS8700_MIN_Z_MSB
2268  ** --
2269  ** Offset : 0x4F - Magnetometer Z-axis minimum value MSB.
2270  ** ------------------------------*/
2271  typedef uint8_t FXOS8700_MIN_Z_MSB_t;
2272  
2273  
2274  /*--------------------------------
2275  ** Register: MIN_Z_LSB
2276  ** Enum: FXOS8700_MIN_Z_LSB
2277  ** --
2278  ** Offset : 0x50 - Magnetometer Z-axis minimum value LSB.
2279  ** ------------------------------*/
2280  typedef uint8_t FXOS8700_MIN_Z_LSB_t;
2281  
2282  
2283  
2284  /*--------------------------------
2285  ** Register: TEMP
2286  ** Enum: FXOS8700_TEMP
2287  ** --
2288  ** Offset : 0x51 - Device temperature with a valid range of -128 to 127 degrees C.
2289  ** ------------------------------*/
2290  typedef union {
2291      struct {
2292          uint8_t       die_temperature;
2293      } b;
2294      uint8_t w;
2295  } FXOS8700_TEMP_t;
2296  
2297  
2298  /*
2299  ** TEMP - Bit field mask definitions
2300  */
2301  #define FXOS8700_TEMP_DIE_TEMPERATURE_MASK   ((uint8_t) 0xFF)
2302  #define FXOS8700_TEMP_DIE_TEMPERATURE_SHIFT  ((uint8_t)    0)
2303  
2304  
2305  /*------------------------------*/
2306  
2307  
2308  
2309  /*--------------------------------
2310  ** Register: M_THS_CFG
2311  ** Enum: FXOS8700_M_THS_CFG
2312  ** --
2313  ** Offset : 0x52 - Magnetic threshold detection function configuration.
2314  ** ------------------------------*/
2315  typedef union {
2316      struct {
2317          uint8_t         m_ths_int_cfg : 1;
2318          uint8_t          m_ths_int_en : 1;
2319          uint8_t         m_ths_wake_en : 1;
2320          uint8_t            m_ths_xefe : 1;
2321          uint8_t            m_ths_yefe : 1;
2322          uint8_t            m_ths_zefe : 1;
2323          uint8_t             m_ths_oae : 1;
2324          uint8_t             m_ths_ele : 1;
2325      } b;
2326      uint8_t w;
2327  } FXOS8700_M_THS_CFG_t;
2328  
2329  
2330  /*
2331  ** M_THS_CFG - Bit field mask definitions
2332  */
2333  #define FXOS8700_M_THS_CFG_M_THS_INT_CFG_MASK   ((uint8_t) 0x01)
2334  #define FXOS8700_M_THS_CFG_M_THS_INT_CFG_SHIFT  ((uint8_t)    0)
2335  
2336  #define FXOS8700_M_THS_CFG_M_THS_INT_EN_MASK    ((uint8_t) 0x02)
2337  #define FXOS8700_M_THS_CFG_M_THS_INT_EN_SHIFT   ((uint8_t)    1)
2338  
2339  #define FXOS8700_M_THS_CFG_M_THS_WAKE_EN_MASK   ((uint8_t) 0x04)
2340  #define FXOS8700_M_THS_CFG_M_THS_WAKE_EN_SHIFT  ((uint8_t)    2)
2341  
2342  #define FXOS8700_M_THS_CFG_M_THS_XEFE_MASK      ((uint8_t) 0x08)
2343  #define FXOS8700_M_THS_CFG_M_THS_XEFE_SHIFT     ((uint8_t)    3)
2344  
2345  #define FXOS8700_M_THS_CFG_M_THS_YEFE_MASK      ((uint8_t) 0x10)
2346  #define FXOS8700_M_THS_CFG_M_THS_YEFE_SHIFT     ((uint8_t)    4)
2347  
2348  #define FXOS8700_M_THS_CFG_M_THS_ZEFE_MASK      ((uint8_t) 0x20)
2349  #define FXOS8700_M_THS_CFG_M_THS_ZEFE_SHIFT     ((uint8_t)    5)
2350  
2351  #define FXOS8700_M_THS_CFG_M_THS_OAE_MASK       ((uint8_t) 0x40)
2352  #define FXOS8700_M_THS_CFG_M_THS_OAE_SHIFT      ((uint8_t)    6)
2353  
2354  #define FXOS8700_M_THS_CFG_M_THS_ELE_MASK       ((uint8_t) 0x80)
2355  #define FXOS8700_M_THS_CFG_M_THS_ELE_SHIFT      ((uint8_t)    7)
2356  
2357  
2358  /*------------------------------*/
2359  
2360  
2361  
2362  /*--------------------------------
2363  ** Register: M_THS_SRC
2364  ** Enum: FXOS8700_M_THS_SRC
2365  ** --
2366  ** Offset : 0x53 - Magnetic threshold event source register.
2367  ** ------------------------------*/
2368  typedef union {
2369      struct {
2370          uint8_t             m_ths_xhp : 1;
2371          uint8_t             m_ths_xhe : 1;
2372          uint8_t             m_ths_yhp : 1;
2373          uint8_t             m_ths_yhe : 1;
2374          uint8_t             m_ths_zhp : 1;
2375          uint8_t             m_ths_zhe : 1;
2376          uint8_t _reserved_            : 1;
2377          uint8_t              m_ths_ea : 1;
2378      } b;
2379      uint8_t w;
2380  } FXOS8700_M_THS_SRC_t;
2381  
2382  
2383  /*
2384  ** M_THS_SRC - Bit field mask definitions
2385  */
2386  #define FXOS8700_M_THS_SRC_M_THS_XHP_MASK   ((uint8_t) 0x01)
2387  #define FXOS8700_M_THS_SRC_M_THS_XHP_SHIFT  ((uint8_t)    0)
2388  
2389  #define FXOS8700_M_THS_SRC_M_THS_XHE_MASK   ((uint8_t) 0x02)
2390  #define FXOS8700_M_THS_SRC_M_THS_XHE_SHIFT  ((uint8_t)    1)
2391  
2392  #define FXOS8700_M_THS_SRC_M_THS_YHP_MASK   ((uint8_t) 0x04)
2393  #define FXOS8700_M_THS_SRC_M_THS_YHP_SHIFT  ((uint8_t)    2)
2394  
2395  #define FXOS8700_M_THS_SRC_M_THS_YHE_MASK   ((uint8_t) 0x08)
2396  #define FXOS8700_M_THS_SRC_M_THS_YHE_SHIFT  ((uint8_t)    3)
2397  
2398  #define FXOS8700_M_THS_SRC_M_THS_ZHP_MASK   ((uint8_t) 0x10)
2399  #define FXOS8700_M_THS_SRC_M_THS_ZHP_SHIFT  ((uint8_t)    4)
2400  
2401  #define FXOS8700_M_THS_SRC_M_THS_ZHE_MASK   ((uint8_t) 0x20)
2402  #define FXOS8700_M_THS_SRC_M_THS_ZHE_SHIFT  ((uint8_t)    5)
2403  
2404  #define FXOS8700_M_THS_SRC_M_THS_EA_MASK    ((uint8_t) 0x80)
2405  #define FXOS8700_M_THS_SRC_M_THS_EA_SHIFT   ((uint8_t)    7)
2406  
2407  
2408  /*------------------------------*/
2409  
2410  
2411  
2412  /*--------------------------------
2413  ** Register: M_THS_X_MSB
2414  ** Enum: FXOS8700_M_THS_X_MSB
2415  ** --
2416  ** Offset : 0x54 - X-axis magnetic threshold MSB.
2417  ** ------------------------------*/
2418  typedef union {
2419      struct {
2420          uint8_t               m_ths_x : 7;
2421      } b;
2422      uint8_t w;
2423  } FXOS8700_M_THS_X_MSB_t;
2424  
2425  
2426  /*
2427  ** M_THS_X_MSB - Bit field mask definitions
2428  */
2429  #define FXOS8700_M_THS_X_MSB_M_THS_X_MASK   ((uint8_t) 0x7F)
2430  #define FXOS8700_M_THS_X_MSB_M_THS_X_SHIFT  ((uint8_t)    0)
2431  
2432  
2433  /*------------------------------*/
2434  
2435  
2436  
2437  /*--------------------------------
2438  ** Register: M_THS_X_LSB
2439  ** Enum: FXOS8700_M_THS_X_LSB
2440  ** --
2441  ** Offset : 0x55 - X-axis magnetic threshold LSB.
2442  ** ------------------------------*/
2443  typedef uint8_t FXOS8700_M_THS_X_LSB_t;
2444  
2445  
2446  /*--------------------------------
2447  ** Register: M_THS_Y_MSB
2448  ** Enum: FXOS8700_M_THS_Y_MSB
2449  ** --
2450  ** Offset : 0x56 - Y-axis magnetic threshold MSB.
2451  ** ------------------------------*/
2452  typedef union {
2453      struct {
2454          uint8_t               m_ths_y : 7;
2455      } b;
2456      uint8_t w;
2457  } FXOS8700_M_THS_Y_MSB_t;
2458  
2459  
2460  /*
2461  ** M_THS_Y_MSB - Bit field mask definitions
2462  */
2463  #define FXOS8700_M_THS_Y_MSB_M_THS_Y_MASK   ((uint8_t) 0x7F)
2464  #define FXOS8700_M_THS_Y_MSB_M_THS_Y_SHIFT  ((uint8_t)    0)
2465  
2466  
2467  /*------------------------------*/
2468  
2469  
2470  
2471  /*--------------------------------
2472  ** Register: M_THS_Y_LSB
2473  ** Enum: FXOS8700_M_THS_Y_LSB
2474  ** --
2475  ** Offset : 0x57 - Y-axis magnetic threshold LSB.
2476  ** ------------------------------*/
2477  typedef uint8_t FXOS8700_M_THS_Y_LSB_t;
2478  
2479  
2480  /*--------------------------------
2481  ** Register: M_THS_Z_MSB
2482  ** Enum: FXOS8700_M_THS_Z_MSB
2483  ** --
2484  ** Offset : 0x58 - Z-axis magnetic threshold MSB.
2485  ** ------------------------------*/
2486  typedef union {
2487      struct {
2488          uint8_t               m_ths_z : 7;
2489      } b;
2490      uint8_t w;
2491  } FXOS8700_M_THS_Z_MSB_t;
2492  
2493  
2494  /*
2495  ** M_THS_Z_MSB - Bit field mask definitions
2496  */
2497  #define FXOS8700_M_THS_Z_MSB_M_THS_Z_MASK   ((uint8_t) 0x7F)
2498  #define FXOS8700_M_THS_Z_MSB_M_THS_Z_SHIFT  ((uint8_t)    0)
2499  
2500  
2501  /*------------------------------*/
2502  
2503  
2504  
2505  /*--------------------------------
2506  ** Register: M_THS_Z_LSB
2507  ** Enum: FXOS8700_M_THS_Z_LSB
2508  ** --
2509  ** Offset : 0x59 - Z-axis magnetic threshold LSB.
2510  ** ------------------------------*/
2511  typedef uint8_t FXOS8700_M_THS_Z_LSB_t;
2512  
2513  
2514  /*--------------------------------
2515  ** Register: M_THS_COUNT
2516  ** Enum: FXOS8700_M_THS_COUNT
2517  ** --
2518  ** Offset : 0x5A - Magnetic threshold debounce counter.
2519  ** ------------------------------*/
2520  typedef uint8_t FXOS8700_M_THS_COUNT_t;
2521  
2522  
2523  
2524  /*--------------------------------
2525  ** Register: M_CTRL_REG1
2526  ** Enum: FXOS8700_M_CTRL_REG1
2527  ** --
2528  ** Offset : 0x5B - Control for magnetometer sensor functions.
2529  ** ------------------------------*/
2530  typedef union {
2531      struct {
2532          uint8_t                 m_hms : 2;
2533          uint8_t                  m_os : 3; /*  M-cell oversample ratio                                                    */
2534  
2535          uint8_t                 m_ost : 1; /*  One-shot triggered magnetic measurement mode:                              */
2536  
2537          uint8_t                 m_rst : 1;
2538          uint8_t                m_acal : 1;
2539      } b;
2540      uint8_t w;
2541  } FXOS8700_M_CTRL_REG1_t;
2542  
2543  
2544  /*
2545  ** M_CTRL_REG1 - Bit field mask definitions
2546  */
2547  #define FXOS8700_M_CTRL_REG1_M_HMS_MASK    ((uint8_t) 0x03)
2548  #define FXOS8700_M_CTRL_REG1_M_HMS_SHIFT   ((uint8_t)    0)
2549  
2550  #define FXOS8700_M_CTRL_REG1_M_OS_MASK     ((uint8_t) 0x1C)
2551  #define FXOS8700_M_CTRL_REG1_M_OS_SHIFT    ((uint8_t)    2)
2552  
2553  #define FXOS8700_M_CTRL_REG1_M_OST_MASK    ((uint8_t) 0x20)
2554  #define FXOS8700_M_CTRL_REG1_M_OST_SHIFT   ((uint8_t)    5)
2555  
2556  #define FXOS8700_M_CTRL_REG1_M_RST_MASK    ((uint8_t) 0x40)
2557  #define FXOS8700_M_CTRL_REG1_M_RST_SHIFT   ((uint8_t)    6)
2558  
2559  #define FXOS8700_M_CTRL_REG1_M_ACAL_MASK   ((uint8_t) 0x80)
2560  #define FXOS8700_M_CTRL_REG1_M_ACAL_SHIFT  ((uint8_t)    7)
2561  
2562  
2563  /*
2564  ** M_CTRL_REG1 - Bit field value definitions
2565  */
2566  #define FXOS8700_M_CTRL_REG1_M_ACAL_EN             ((uint8_t) 0x80)  /*  Auto-calibration feature enabled                 */
2567  #define FXOS8700_M_CTRL_REG1_M_ACAL_DISABLE        ((uint8_t) 0x00)  /*  Auto-calibration feature disabled                */
2568  #define FXOS8700_M_CTRL_REG1_M_RST_EN              ((uint8_t) 0x40)  /*  One-shot magnetic sensor reset enabled, hw       */
2569                                                                       /*  cleared when complete                            */
2570  #define FXOS8700_M_CTRL_REG1_M_RST_DISABLE         ((uint8_t) 0x00)  /*  No magnetic sensor reset active                  */
2571  #define FXOS8700_M_CTRL_REG1_M_OST_EN              ((uint8_t) 0x20)  /*  If device is in Active mode no action is taken.  */
2572                                                                       /*  If device is in Standby mode, take one set of    */
2573                                                                       /*  magnetic measurements, clear this bit, and       */
2574                                                                       /*  return to Standby mode.                          */
2575  #define FXOS8700_M_CTRL_REG1_M_OST_DISABLE         ((uint8_t) 0x00)  /*  No action taken, or one-shot measurement         */
2576                                                                       /*  complete                                         */
2577  #define FXOS8700_M_CTRL_REG1_M_OS_OSR0             ((uint8_t) 0x00)  /*  1.56=16, 6.25=4, 12.5=2, 50=2, 100=2, 200=2,     */
2578                                                                       /*  400=2, 800=2                                     */
2579  #define FXOS8700_M_CTRL_REG1_M_OS_OSR1             ((uint8_t) 0x04)  /*  1.56=16, 6.25=4, 12.5=2, 50=2, 100=2, 200=2,     */
2580                                                                       /*  400=2, 800=2                                     */
2581  #define FXOS8700_M_CTRL_REG1_M_OS_OSR2             ((uint8_t) 0x08)  /*  1.56=32, 6.25=8, 12.5=4, 50=2, 100=2, 200=2,     */
2582                                                                       /*  400=2, 800=2                                     */
2583  #define FXOS8700_M_CTRL_REG1_M_OS_OSR3             ((uint8_t) 0x0c)  /*  1.56=64, 6.25=16, 12.5=8, 50=2, 100=2, 200=2,    */
2584                                                                       /*  400=2, 800=2                                     */
2585  #define FXOS8700_M_CTRL_REG1_M_OS_OSR4             ((uint8_t) 0x10)  /*  1.56=128, 6.25=32, 12.5=16, 50=4, 100=2, 200=2,  */
2586                                                                       /*  400=2, 800=2                                     */
2587  #define FXOS8700_M_CTRL_REG1_M_OS_OSR5             ((uint8_t) 0x14)  /*  1.56=256, 6.25=64, 12.5=32, 50=8, 100=4, 200=2,  */
2588                                                                       /*  400=2, 800=2                                     */
2589  #define FXOS8700_M_CTRL_REG1_M_OS_OSR6             ((uint8_t) 0x18)  /*  1.56=512, 6.25=128, 12.5=64, 50=16, 100=8,       */
2590                                                                       /*  200=4, 400=2, 800=2                              */
2591  #define FXOS8700_M_CTRL_REG1_M_OS_OSR7             ((uint8_t) 0x1c)  /*  1.56=1024, 6.25=256, 12.5=128, 50=32, 100=16,    */
2592                                                                       /*  200=8, 400=4, 800=2                              */
2593  #define FXOS8700_M_CTRL_REG1_M_HMS_ACCEL_ONLY      ((uint8_t) 0x00)  /*  0b00 = Only accelerometer sensor is active       */
2594  #define FXOS8700_M_CTRL_REG1_M_HMS_MAG_ONLY        ((uint8_t) 0x01)  /*  0b01 = Only magnetometer sensor is active        */
2595  #define FXOS8700_M_CTRL_REG1_M_HMS_HYBRID_MODE     ((uint8_t) 0x03)  /*  0b11 = Hybrid mode, both accelerometer and       */
2596                                                                       /*  magnetometer sensors are active                  */
2597  /*------------------------------*/
2598  
2599  
2600  
2601  /*--------------------------------
2602  ** Register: M_CTRL_REG2
2603  ** Enum: FXOS8700_M_CTRL_REG2
2604  ** --
2605  ** Offset : 0x5C - Control for magnetometer sensor functions.
2606  ** ------------------------------*/
2607  typedef union {
2608      struct {
2609          uint8_t             m_rst_cnt : 2;
2610          uint8_t          m_maxmin_rst : 1;
2611          uint8_t      m_maxmin_dis_ths : 1;
2612          uint8_t          m_maxmin_dis : 1;
2613          uint8_t             m_autoinc : 1;
2614      } b;
2615      uint8_t w;
2616  } FXOS8700_M_CTRL_REG2_t;
2617  
2618  
2619  /*
2620  ** M_CTRL_REG2 - Bit field mask definitions
2621  */
2622  #define FXOS8700_M_CTRL_REG2_M_RST_CNT_MASK          ((uint8_t) 0x03)
2623  #define FXOS8700_M_CTRL_REG2_M_RST_CNT_SHIFT         ((uint8_t)    0)
2624  
2625  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_MASK       ((uint8_t) 0x04)
2626  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_SHIFT      ((uint8_t)    2)
2627  
2628  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_MASK   ((uint8_t) 0x08)
2629  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_SHIFT  ((uint8_t)    3)
2630  
2631  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_MASK       ((uint8_t) 0x10)
2632  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_SHIFT      ((uint8_t)    4)
2633  
2634  #define FXOS8700_M_CTRL_REG2_M_AUTOINC_MASK          ((uint8_t) 0x20)
2635  #define FXOS8700_M_CTRL_REG2_M_AUTOINC_SHIFT         ((uint8_t)    5)
2636  
2637  
2638  /*
2639  ** M_CTRL_REG2 - Bit field value definitions
2640  */
2641  #define FXOS8700_M_CTRL_REG2_M_AUTOINC_HYBRID_MODE ((uint8_t) 0x20)  /*  With hyb_autoinc_mode = 1 and fast-read mode is  */
2642                                                                       /*  disabled (CTRL_REG1 [f_read] = 0), the register  */
2643                                                                       /*  address will automatically advance to register   */
2644                                                                       /*  x33 (M_OUT_X_MSB) after reading register x06     */
2645                                                                       /*  (OUT_Z_LSB) in burst-read mode.                  */
2646                                                                       /*  For hyb_autoinc_mode = 1 and fast read mode      */
2647                                                                       /*  enabled (CTRL_REG1[f_read = 1) the register      */
2648                                                                       /*  address will automatically advance to register   */
2649                                                                       /*  x33 (M_OUT_X_MSB) after reading register x05     */
2650                                                                       /*  (OUT_Z_MSB) during a burstread mode. Please      */
2651                                                                       /*  refer to the register map auto-increment address */
2652                                                                       /*  column for further information.                  */
2653  #define FXOS8700_M_CTRL_REG2_M_AUTOINC_ACCEL_ONLY_MODE ((uint8_t) 0x00)  /*  hyb_autoinc_mode = 0                         */
2654  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_DIS      ((uint8_t) 0x00)  /*  Magnetic min/max detection function is enabled   */
2655  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_EN       ((uint8_t) 0x10)  /*  Magnetic min/max detection function is disabled  */
2656  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_DIS  ((uint8_t) 0x00)  /*  No impact to magnetic min/max detection function */
2657                                                                       /*  on a magnetic threshold event                    */
2658  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_EN   ((uint8_t) 0x08)  /*  Magnetic min/max detection function is disabled  */
2659                                                                       /*  when magnetic threshold event is triggered       */
2660  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_NO_SEQUENCE ((uint8_t) 0x00)  /*  No reset sequence is active                   */
2661  #define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_SET      ((uint8_t) 0x04)  /*  Setting this bit resets the MIN_X/Y/Z and        */
2662                                                                       /*  MAX_X/Y/Z registers to 0x7FFF and 0x8000         */
2663  #define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY1      ((uint8_t) 0x00)  /*  Automatic magnetic reset at the beginning of     */
2664                                                                       /*  each ODR cycle (default).                        */
2665  #define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY16     ((uint8_t) 0x01)  /*  Automatic magnetic reset every 16 ODR cycles     */
2666  #define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY512    ((uint8_t) 0x02)  /*  Automatic magnetic reset every 512 ODR cycles    */
2667  #define FXOS8700_M_CTRL_REG2_M_RST_CNT_DISABLE     ((uint8_t) 0x03)  /*  Automatic magnetic reset is disabled. Magnetic   */
2668                                                                       /*  reset only occurs automatically on a transition  */
2669                                                                       /*  from Standby to Active mode, or can be triggered */
2670                                                                       /*  manually by setting M_CTRL_REG1[m_rst] = 1       */
2671  /*------------------------------*/
2672  
2673  
2674  
2675  
2676  /*--------------------------------
2677  ** Register: M_CTRL_REG3
2678  ** Enum: FXOS8700_M_CTRL_REG3
2679  ** --
2680  ** Offset : 0x5D - Control for magnetometer sensor functions.
2681  ** ------------------------------*/
2682  typedef union {
2683      struct {
2684          uint8_t               m_st_xy : 2;
2685          uint8_t                m_st_z : 1;
2686          uint8_t      m_ths_xyz_update : 1;
2687          uint8_t             m_aslp_os : 3;
2688          uint8_t                 m_raw : 1;
2689      } b;
2690      uint8_t w;
2691  } FXOS8700_M_CTRL_REG3_t;
2692  
2693  
2694  /*
2695  ** M_CTRL_REG3 - Bit field mask definitions
2696  */
2697  #define FXOS8700_M_CTRL_REG3_M_ST_XY_MASK            ((uint8_t) 0x03)
2698  #define FXOS8700_M_CTRL_REG3_M_ST_XY_SHIFT           ((uint8_t)    0)
2699  
2700  #define FXOS8700_M_CTRL_REG3_M_ST_Z_MASK             ((uint8_t) 0x04)
2701  #define FXOS8700_M_CTRL_REG3_M_ST_Z_SHIFT            ((uint8_t)    2)
2702  
2703  #define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_MASK   ((uint8_t) 0x08)
2704  #define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_SHIFT  ((uint8_t)    3)
2705  
2706  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_MASK          ((uint8_t) 0x70)
2707  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_SHIFT         ((uint8_t)    4)
2708  
2709  #define FXOS8700_M_CTRL_REG3_M_RAW_MASK              ((uint8_t) 0x80)
2710  #define FXOS8700_M_CTRL_REG3_M_RAW_SHIFT             ((uint8_t)    7)
2711  
2712  
2713  /*
2714  ** M_CTRL_REG3 - Bit field value definitions
2715  */
2716  #define FXOS8700_M_CTRL_REG3_M_RAW_EN              ((uint8_t) 0x80)  /*  Values stored in the M_OFF_X/Y/Z registers are   */
2717                                                                       /*  applied to the magnetic sample data              */
2718  #define FXOS8700_M_CTRL_REG3_M_RAW_DIS             ((uint8_t) 0x00)  /*  Values stored in M_OFF_X/Y/Z are not applied to  */
2719                                                                       /*  the magnetic sample data                         */
2720  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_0       ((uint8_t) 0x00)  /*  OSR 0 look at table 203                          */
2721  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_1       ((uint8_t) 0x10)  /*  OSR 1 look at table 203                          */
2722  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_2       ((uint8_t) 0x20)  /*  OSR 2 look at table 203                          */
2723  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_3       ((uint8_t) 0x30)  /*  OSR 3 look at table 203                          */
2724  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_4       ((uint8_t) 0x40)  /*  OSR 4 look at table 203                          */
2725  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_5       ((uint8_t) 0x50)  /*  OSR 5 look at table 203                          */
2726  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_6       ((uint8_t) 0x60)  /*  OSR 6 look at table 203                          */
2727  #define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_7       ((uint8_t) 0x70)  /*  OSR look at table 203                            */
2728  #define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_EN   ((uint8_t) 0x08)  /*  Only the reference value for the axis that       */
2729                                                                       /*  triggered the detection event is updated         */
2730  #define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_DIS  ((uint8_t) 0x00)  /*  X, Y and Z reference values are all updated when */
2731                                                                       /*  the function triggers on any of the X, Y, or Z   */
2732                                                                       /*  axes                                             */
2733  /*------------------------------*/
2734  
2735  
2736  
2737  /*--------------------------------
2738  ** Register: M_INT_SRC
2739  ** Enum: FXOS8700_M_INT_SRC
2740  ** --
2741  ** Offset : 0x5E - Magnetometer interrupt source.
2742  ** ------------------------------*/
2743  typedef union {
2744      struct {
2745          uint8_t            src_m_drdy : 1;
2746          uint8_t            src_m_vecm : 1;
2747          uint8_t             src_m_ths : 1;
2748      } b;
2749      uint8_t w;
2750  } FXOS8700_M_INT_SRC_t;
2751  
2752  
2753  /*
2754  ** M_INT_SRC - Bit field mask definitions
2755  */
2756  #define FXOS8700_M_INT_SRC_SRC_M_DRDY_MASK   ((uint8_t) 0x01)
2757  #define FXOS8700_M_INT_SRC_SRC_M_DRDY_SHIFT  ((uint8_t)    0)
2758  
2759  #define FXOS8700_M_INT_SRC_SRC_M_VECM_MASK   ((uint8_t) 0x02)
2760  #define FXOS8700_M_INT_SRC_SRC_M_VECM_SHIFT  ((uint8_t)    1)
2761  
2762  #define FXOS8700_M_INT_SRC_SRC_M_THS_MASK    ((uint8_t) 0x04)
2763  #define FXOS8700_M_INT_SRC_SRC_M_THS_SHIFT   ((uint8_t)    2)
2764  
2765  
2766  /*------------------------------*/
2767  
2768  
2769  
2770  /*--------------------------------
2771  ** Register: A_VECM_CFG
2772  ** Enum: FXOS8700_A_VECM_CFG
2773  ** --
2774  ** Offset : 0x5F - Acceleration vector magnitude configuration register.
2775  ** ------------------------------*/
2776  typedef union {
2777      struct {
2778          uint8_t _reserved_            : 4;
2779          uint8_t           a_vecm_updm : 1;
2780          uint8_t          a_vecm_initm : 1;
2781          uint8_t            a_vecm_ele : 1;
2782          uint8_t             a_vecm_en : 1;
2783      } b;
2784      uint8_t w;
2785  } FXOS8700_A_VECM_CFG_t;
2786  
2787  
2788  /*
2789  ** A_VECM_CFG - Bit field mask definitions
2790  */
2791  #define FXOS8700_A_VECM_CFG_A_VECM_UPDM_MASK    ((uint8_t) 0x10)
2792  #define FXOS8700_A_VECM_CFG_A_VECM_UPDM_SHIFT   ((uint8_t)    4)
2793  
2794  #define FXOS8700_A_VECM_CFG_A_VECM_INITM_MASK   ((uint8_t) 0x20)
2795  #define FXOS8700_A_VECM_CFG_A_VECM_INITM_SHIFT  ((uint8_t)    5)
2796  
2797  #define FXOS8700_A_VECM_CFG_A_VECM_ELE_MASK     ((uint8_t) 0x40)
2798  #define FXOS8700_A_VECM_CFG_A_VECM_ELE_SHIFT    ((uint8_t)    6)
2799  
2800  #define FXOS8700_A_VECM_CFG_A_VECM_EN_MASK      ((uint8_t) 0x80)
2801  #define FXOS8700_A_VECM_CFG_A_VECM_EN_SHIFT     ((uint8_t)    7)
2802  
2803  
2804  /*------------------------------*/
2805  
2806  
2807  
2808  /*--------------------------------
2809  ** Register: A_VECM_THS_MSB
2810  ** Enum: FXOS8700_A_VECM_THS_MSB
2811  ** --
2812  ** Offset : 0x60 - Acceleration vector magnitude threshold MSB.
2813  ** ------------------------------*/
2814  typedef union {
2815      struct {
2816          uint8_t           a_vbecm_ths : 5;
2817          uint8_t _reserved_            : 2;
2818          uint8_t        a_vbecm_dbcntm : 1;
2819      } b;
2820      uint8_t w;
2821  } FXOS8700_A_VECM_THS_MSB_t;
2822  
2823  
2824  /*
2825  ** A_VECM_THS_MSB - Bit field mask definitions
2826  */
2827  #define FXOS8700_A_VECM_THS_MSB_A_VBECM_THS_MASK      ((uint8_t) 0x1F)
2828  #define FXOS8700_A_VECM_THS_MSB_A_VBECM_THS_SHIFT     ((uint8_t)    0)
2829  
2830  #define FXOS8700_A_VECM_THS_MSB_A_VBECM_DBCNTM_MASK   ((uint8_t) 0x80)
2831  #define FXOS8700_A_VECM_THS_MSB_A_VBECM_DBCNTM_SHIFT  ((uint8_t)    7)
2832  
2833  
2834  /*------------------------------*/
2835  
2836  
2837  
2838  /*--------------------------------
2839  ** Register: A_VECM_THS_LSB
2840  ** Enum: FXOS8700_A_VECM_THS_LSB
2841  ** --
2842  ** Offset : 0x61 - Acceleration vector magnitude threshold LSB.
2843  ** ------------------------------*/
2844  typedef uint8_t FXOS8700_A_VECM_THS_LSB_t;
2845  
2846  
2847  /*--------------------------------
2848  ** Register: A_VECM_CNT
2849  ** Enum: FXOS8700_A_VECM_CNT
2850  ** --
2851  ** Offset : 0x62 - Acceleration vector magnitude debounce count.
2852  ** ------------------------------*/
2853  typedef uint8_t FXOS8700_A_VECM_CNT_t;
2854  
2855  
2856  
2857  /*--------------------------------
2858  ** Register: A_VECM_INITX_MSB
2859  ** Enum: FXOS8700_A_VECM_INITX_MSB
2860  ** --
2861  ** Offset : 0x63 - Acceleration vector magnitude X-axis reference value MSB.
2862  ** ------------------------------*/
2863  typedef union {
2864      struct {
2865          uint8_t          a_vecm_initx : 6;
2866      } b;
2867      uint8_t w;
2868  } FXOS8700_A_VECM_INITX_MSB_t;
2869  
2870  
2871  /*
2872  ** A_VECM_INITX_MSB - Bit field mask definitions
2873  */
2874  #define FXOS8700_A_VECM_INITX_MSB_A_VECM_INITX_MASK   ((uint8_t) 0x3F)
2875  #define FXOS8700_A_VECM_INITX_MSB_A_VECM_INITX_SHIFT  ((uint8_t)    0)
2876  
2877  
2878  /*------------------------------*/
2879  
2880  
2881  
2882  /*--------------------------------
2883  ** Register: A_VECM_INITX_LSB
2884  ** Enum: FXOS8700_A_VECM_INITX_LSB
2885  ** --
2886  ** Offset : 0x64 - Acceleration vector magnitude X-axis reference value LSB.
2887  ** ------------------------------*/
2888  typedef uint8_t FXOS8700_A_VECM_INITX_LSB_t;
2889  
2890  
2891  /*--------------------------------
2892  ** Register: A_VECM_INITY_MSB
2893  ** Enum: FXOS8700_A_VECM_INITY_MSB
2894  ** --
2895  ** Offset : 0x65 - Acceleration vector magnitude Y-axis reference value MSB.
2896  ** ------------------------------*/
2897  typedef union {
2898      struct {
2899          uint8_t          a_vecm_inity : 6;
2900      } b;
2901      uint8_t w;
2902  } FXOS8700_A_VECM_INITY_MSB_t;
2903  
2904  
2905  /*
2906  ** A_VECM_INITY_MSB - Bit field mask definitions
2907  */
2908  #define FXOS8700_A_VECM_INITY_MSB_A_VECM_INITY_MASK   ((uint8_t) 0x3F)
2909  #define FXOS8700_A_VECM_INITY_MSB_A_VECM_INITY_SHIFT  ((uint8_t)    0)
2910  
2911  
2912  /*------------------------------*/
2913  
2914  
2915  
2916  /*--------------------------------
2917  ** Register: A_VECM_INITY_LSB
2918  ** Enum: FXOS8700_A_VECM_INITY_LSB
2919  ** --
2920  ** Offset : 0x66 - Acceleration vector magnitude Y-axis reference value LSB.
2921  ** ------------------------------*/
2922  typedef uint8_t FXOS8700_A_VECM_INITY_LSB_t;
2923  
2924  
2925  /*--------------------------------
2926  ** Register: A_VECM_INITZ_MSB
2927  ** Enum: FXOS8700_A_VECM_INITZ_MSB
2928  ** --
2929  ** Offset : 0x67 - Acceleration vector magnitude Z-axis reference value MSB.
2930  ** ------------------------------*/
2931  typedef union {
2932      struct {
2933          uint8_t          a_vecm_initz : 6;
2934      } b;
2935      uint8_t w;
2936  } FXOS8700_A_VECM_INITZ_MSB_t;
2937  
2938  
2939  /*
2940  ** A_VECM_INITZ_MSB - Bit field mask definitions
2941  */
2942  #define FXOS8700_A_VECM_INITZ_MSB_A_VECM_INITZ_MASK   ((uint8_t) 0x3F)
2943  #define FXOS8700_A_VECM_INITZ_MSB_A_VECM_INITZ_SHIFT  ((uint8_t)    0)
2944  
2945  
2946  /*------------------------------*/
2947  
2948  
2949  
2950  /*--------------------------------
2951  ** Register: A_VECM_INITZ_LSB
2952  ** Enum: FXOS8700_A_VECM_INITZ_LSB
2953  ** --
2954  ** Offset : 0x68 - Acceleration vector magnitude Z-axis reference value LSB.
2955  ** ------------------------------*/
2956  typedef uint8_t FXOS8700_A_VECM_INITZ_LSB_t;
2957  
2958  
2959  /*--------------------------------
2960  ** Register: M_VECM_CFG
2961  ** Enum: FXOS8700_M_VECM_CFG
2962  ** --
2963  ** Offset : 0x69 - Magnetic vector magnitude configuration register.
2964  ** ------------------------------*/
2965  typedef union {
2966      struct {
2967          uint8_t       m_vecm_init_cfg : 1;
2968          uint8_t         m_vecm_int_en : 1;
2969          uint8_t        m_vecm_wake_en : 1;
2970          uint8_t             a_vecm_en : 1;
2971          uint8_t           m_vecm_updm : 1;
2972          uint8_t          m_vecm_initm : 1;
2973          uint8_t            m_vecm_ele : 1;
2974          uint8_t              reserved : 1;
2975      } b;
2976      uint8_t w;
2977  } FXOS8700_M_VECM_CFG_t;
2978  
2979  
2980  /*
2981  ** M_VECM_CFG - Bit field mask definitions
2982  */
2983  #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_MASK   ((uint8_t) 0x01)
2984  #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_SHIFT  ((uint8_t)    0)
2985  
2986  #define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_MASK     ((uint8_t) 0x02)
2987  #define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_SHIFT    ((uint8_t)    1)
2988  
2989  #define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_MASK    ((uint8_t) 0x04)
2990  #define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_SHIFT   ((uint8_t)    2)
2991  
2992  #define FXOS8700_M_VECM_CFG_A_VECM_EN_MASK         ((uint8_t) 0x08)
2993  #define FXOS8700_M_VECM_CFG_A_VECM_EN_SHIFT        ((uint8_t)    3)
2994  
2995  #define FXOS8700_M_VECM_CFG_M_VECM_UPDM_MASK       ((uint8_t) 0x10)
2996  #define FXOS8700_M_VECM_CFG_M_VECM_UPDM_SHIFT      ((uint8_t)    4)
2997  
2998  #define FXOS8700_M_VECM_CFG_M_VECM_INITM_MASK      ((uint8_t) 0x20)
2999  #define FXOS8700_M_VECM_CFG_M_VECM_INITM_SHIFT     ((uint8_t)    5)
3000  
3001  #define FXOS8700_M_VECM_CFG_M_VECM_ELE_MASK        ((uint8_t) 0x40)
3002  #define FXOS8700_M_VECM_CFG_M_VECM_ELE_SHIFT       ((uint8_t)    6)
3003  
3004  #define FXOS8700_M_VECM_CFG_RESERVED_MASK          ((uint8_t) 0x80)
3005  #define FXOS8700_M_VECM_CFG_RESERVED_SHIFT         ((uint8_t)    7)
3006  
3007  
3008  /*
3009  ** M_VECM_CFG - Bit field value definitions
3010  */
3011  #define FXOS8700_M_VECM_CFG_M_VECM_ELE_DIS        ((uint8_t) 0x00)  /*  Event latch disabled                              */
3012  #define FXOS8700_M_VECM_CFG_M_VECM_ELE_EN         ((uint8_t) 0x40)  /*  Event latch enabled                               */
3013  #define FXOS8700_M_VECM_CFG_M_VECM_INITM_OUT      ((uint8_t) 0x00)  /*  The ASIC uses the current magnetic output data as */
3014                                                                      /*  the initial reference values at the time the      */
3015                                                                      /*  m_vecm_en bit is set                              */
3016  #define FXOS8700_M_VECM_CFG_M_VECM_INITM_STORED   ((uint8_t) 0x20)  /*  The ASIC uses the data stored in the              */
3017                                                                      /*  M_VECM_X/Y/Z_INIT registers as the initial        */
3018                                                                      /*  reference values at the time the m_vecm_en bit is */
3019                                                                      /*  set                                               */
3020  #define FXOS8700_M_VECM_CFG_M_VECM_UPDM_DIS       ((uint8_t) 0x00)  /*  The function updates the reference values with    */
3021                                                                      /*  the current X, Y, and Z magnetic data when the    */
3022                                                                      /*  event is triggered                                */
3023  #define FXOS8700_M_VECM_CFG_M_VECM_UPDM_EN        ((uint8_t) 0x10)  /*  The function does not update the reference values */
3024                                                                      /*  when the event is triggered                       */
3025  #define FXOS8700_M_VECM_CFG_A_VECM_EN_EN          ((uint8_t) 0x00)  /*  Function is disabled                              */
3026  #define FXOS8700_M_VECM_CFG_A_VECM_EN_DIS         ((uint8_t) 0x08)  /*  Function is enabled                               */
3027  #define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_EN     ((uint8_t) 0x00)  /*  The system excludes the src_m_vecm event flag     */
3028                                                                      /*  when evaluating the auto-sleep function           */
3029  #define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_DIS    ((uint8_t) 0x04)  /*  The system includes the src_m_vecm event flag     */
3030                                                                      /*  when evaluating the auto-sleep function           */
3031  #define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_EN      ((uint8_t) 0x00)  /*  Magnetic vector-magnitude interrupt is disabled   */
3032  #define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_DIS     ((uint8_t) 0x02)  /*  Magnetic vector-magnitude interrupt is enabled    */
3033  #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_INT2  ((uint8_t) 0x00)  /*  Magnetic vector-magnitude interrupt is output on  */
3034                                                                      /*  INT2 pin                                          */
3035  #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_INT1  ((uint8_t) 0x01)  /*  Magnetic vector-magnitude interrupt is output on  */
3036                                                                      /*  INT1 pin.                                         */
3037  #define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_DIS   ((uint8_t) 0x01)  /*  Function is enabled                               */
3038  /*------------------------------*/
3039  
3040  
3041  
3042  /*--------------------------------
3043  ** Register: M_VECM_THS_MSB
3044  ** Enum: FXOS8700_M_VECM_THS_MSB
3045  ** --
3046  ** Offset : 0x6A - Magnetic vector magnitude threshold MSB.
3047  ** ------------------------------*/
3048  typedef union {
3049      struct {
3050          uint8_t            m_vecm_ths : 7;
3051      } b;
3052      uint8_t w;
3053  } FXOS8700_M_VECM_THS_MSB_t;
3054  
3055  
3056  /*
3057  ** M_VECM_THS_MSB - Bit field mask definitions
3058  */
3059  #define FXOS8700_M_VECM_THS_MSB_M_VECM_THS_MASK   ((uint8_t) 0x7F)
3060  #define FXOS8700_M_VECM_THS_MSB_M_VECM_THS_SHIFT  ((uint8_t)    0)
3061  
3062  
3063  /*------------------------------*/
3064  
3065  
3066  
3067  /*--------------------------------
3068  ** Register: M_VECM_THS_LSB
3069  ** Enum: FXOS8700_M_VECM_THS_LSB
3070  ** --
3071  ** Offset : 0x6B - Magnetic vector magnitude threshold LSB.
3072  ** ------------------------------*/
3073  typedef uint8_t FXOS8700_M_VECM_THS_LSB_t;
3074  
3075  
3076  /*--------------------------------
3077  ** Register: M_VECM_CNT
3078  ** Enum: FXOS8700_M_VECM_CNT
3079  ** --
3080  ** Offset : 0x6C - Magnetic vector magnitude debounce count.
3081  ** ------------------------------*/
3082  typedef uint8_t FXOS8700_M_VECM_CNT_t;
3083  
3084  
3085  /*--------------------------------
3086  ** Register: M_VECM_INITX_MSB
3087  ** Enum: FXOS8700_M_VECM_INITX_MSB
3088  ** --
3089  ** Offset : 0x6D - Magnetic vector magnitude X-axis reference value MSB.
3090  ** ------------------------------*/
3091  typedef uint8_t FXOS8700_M_VECM_INITX_MSB_t;
3092  
3093  
3094  /*--------------------------------
3095  ** Register: M_VECM_INITX_LSB
3096  ** Enum: FXOS8700_M_VECM_INITX_LSB
3097  ** --
3098  ** Offset : 0x6E - Magnetic vector magnitude X-axis reference value LSB.
3099  ** ------------------------------*/
3100  typedef uint8_t FXOS8700_M_VECM_INITX_LSB_t;
3101  
3102  
3103  /*--------------------------------
3104  ** Register: M_VECM_INITY_MSB
3105  ** Enum: FXOS8700_M_VECM_INITY_MSB
3106  ** --
3107  ** Offset : 0x6F - Magnetic vector magnitude Y-axis reference value MSB.
3108  ** ------------------------------*/
3109  typedef uint8_t FXOS8700_M_VECM_INITY_MSB_t;
3110  
3111  
3112  /*--------------------------------
3113  ** Register: M_VECM_INITY_LSB
3114  ** Enum: FXOS8700_M_VECM_INITY_LSB
3115  ** --
3116  ** Offset : 0x70 - Magnetic vector magnitude Y-axis reference value LSB.
3117  ** ------------------------------*/
3118  typedef uint8_t FXOS8700_M_VECM_INITY_LSB_t;
3119  
3120  
3121  /*--------------------------------
3122  ** Register: M_VECM_INITZ_MSB
3123  ** Enum: FXOS8700_M_VECM_INITZ_MSB
3124  ** --
3125  ** Offset : 0x71 - Magnetic vector magnitude Z-axis reference value MSB.
3126  ** ------------------------------*/
3127  typedef uint8_t FXOS8700_M_VECM_INITZ_MSB_t;
3128  
3129  
3130  /*--------------------------------
3131  ** Register: M_VECM_INITZ_LSB
3132  ** Enum: FXOS8700_M_VECM_INITZ_LSB
3133  ** --
3134  ** Offset : 0x72 - Magnetic vector magnitude Z-axis reference value LSB.
3135  ** ------------------------------*/
3136  typedef uint8_t FXOS8700_M_VECM_INITZ_LSB_t;
3137  
3138  
3139  /*--------------------------------
3140  ** Register: A_FFMT_THS_X_MSB
3141  ** Enum: FXOS8700_A_FFMT_THS_X_MSB
3142  ** --
3143  ** Offset : 0x73 - X-axis FFMT threshold MSB.
3144  ** ------------------------------*/
3145  typedef uint8_t FXOS8700_A_FFMT_THS_X_MSB_t;
3146  
3147  
3148  
3149  /*--------------------------------
3150  ** Register: A_FFMT_THS_X_LSB
3151  ** Enum: FXOS8700_A_FFMT_THS_X_LSB
3152  ** --
3153  ** Offset : 0x74 - X-axis FFMT threshold LSB.
3154  ** ------------------------------*/
3155  typedef union {
3156      struct {
3157          uint8_t          a_ffmt_ths_x : 7;
3158      } b;
3159      uint8_t w;
3160  } FXOS8700_A_FFMT_THS_X_LSB_t;
3161  
3162  
3163  /*
3164  ** A_FFMT_THS_X_LSB - Bit field mask definitions
3165  */
3166  #define FXOS8700_A_FFMT_THS_X_LSB_A_FFMT_THS_X_MASK   ((uint8_t) 0x7F)
3167  #define FXOS8700_A_FFMT_THS_X_LSB_A_FFMT_THS_X_SHIFT  ((uint8_t)    0)
3168  
3169  
3170  /*------------------------------*/
3171  
3172  
3173  
3174  /*--------------------------------
3175  ** Register: A_FFMT_THS_Y_MSB
3176  ** Enum: FXOS8700_A_FFMT_THS_Y_MSB
3177  ** --
3178  ** Offset : 0x75 - Y-axis FFMT threshold MSB.
3179  ** ------------------------------*/
3180  typedef uint8_t FXOS8700_A_FFMT_THS_Y_MSB_t;
3181  
3182  
3183  /*--------------------------------
3184  ** Register: A_FFMT_THS_Y_LSB
3185  ** Enum: FXOS8700_A_FFMT_THS_Y_LSB
3186  ** --
3187  ** Offset : 0x76 - Y-axis FFMT threshold LSB.
3188  ** ------------------------------*/
3189  typedef union {
3190      struct {
3191          uint8_t          a_ffmt_ths_y : 7;
3192      } b;
3193      uint8_t w;
3194  } FXOS8700_A_FFMT_THS_Y_LSB_t;
3195  
3196  
3197  /*
3198  ** A_FFMT_THS_Y_LSB - Bit field mask definitions
3199  */
3200  #define FXOS8700_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_MASK   ((uint8_t) 0x7F)
3201  #define FXOS8700_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_SHIFT  ((uint8_t)    0)
3202  
3203  
3204  /*------------------------------*/
3205  
3206  
3207  
3208  /*--------------------------------
3209  ** Register: A_FFMT_THS_Z_MSB
3210  ** Enum: FXOS8700_A_FFMT_THS_Z_MSB
3211  ** --
3212  ** Offset : 0x77 - Z-axis FFMT threshold MSB.
3213  ** ------------------------------*/
3214  typedef uint8_t FXOS8700_A_FFMT_THS_Z_MSB_t;
3215  
3216  
3217  /*--------------------------------
3218  ** Register: A_FFMT_THS_Z_LSB
3219  ** Enum: FXOS8700_A_FFMT_THS_Z_LSB
3220  ** --
3221  ** Offset : 0x78 - Z-axis FFMT threshold LSB.
3222  ** ------------------------------*/
3223  typedef union {
3224      struct {
3225          uint8_t          a_ffmt_ths_z : 7;
3226      } b;
3227      uint8_t w;
3228  } FXOS8700_A_FFMT_THS_Z_LSB_t;
3229  
3230  
3231  /*
3232  ** A_FFMT_THS_Z_LSB - Bit field mask definitions
3233  */
3234  #define FXOS8700_A_FFMT_THS_Z_LSB_A_FFMT_THS_Z_MASK   ((uint8_t) 0x7F)
3235  #define FXOS8700_A_FFMT_THS_Z_LSB_A_FFMT_THS_Z_SHIFT  ((uint8_t)    0)
3236  
3237  
3238  /*------------------------------*/
3239  
3240  
3241  #endif /* FXOS8700_H_ */
3242  
3243  // STATUS :  0x00
3244