1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_FTM_H_
9 #define _FSL_FTM_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup ftm
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief FTM driver version 2.6.0. */
25 #define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
26 /*@}*/
27
28 /*!
29 * @brief List of FTM channels
30 * @note Actual number of available channels is SoC dependent
31 */
32 typedef enum _ftm_chnl
33 {
34 kFTM_Chnl_0 = 0U, /*!< FTM channel number 0*/
35 kFTM_Chnl_1, /*!< FTM channel number 1 */
36 kFTM_Chnl_2, /*!< FTM channel number 2 */
37 kFTM_Chnl_3, /*!< FTM channel number 3 */
38 kFTM_Chnl_4, /*!< FTM channel number 4 */
39 kFTM_Chnl_5, /*!< FTM channel number 5 */
40 kFTM_Chnl_6, /*!< FTM channel number 6 */
41 kFTM_Chnl_7 /*!< FTM channel number 7 */
42 } ftm_chnl_t;
43
44 /*! @brief List of FTM faults */
45 typedef enum _ftm_fault_input
46 {
47 kFTM_Fault_0 = 0U, /*!< FTM fault 0 input pin */
48 kFTM_Fault_1, /*!< FTM fault 1 input pin */
49 kFTM_Fault_2, /*!< FTM fault 2 input pin */
50 kFTM_Fault_3 /*!< FTM fault 3 input pin */
51 } ftm_fault_input_t;
52
53 /*! @brief FTM PWM operation modes */
54 typedef enum _ftm_pwm_mode
55 {
56 kFTM_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
57 kFTM_CenterAlignedPwm, /*!< Center-aligned PWM */
58 kFTM_EdgeAlignedCombinedPwm, /*!< Edge-aligned combined PWM */
59 kFTM_CenterAlignedCombinedPwm, /*!< Center-aligned combined PWM */
60 kFTM_AsymmetricalCombinedPwm /*!< Asymmetrical combined PWM */
61 } ftm_pwm_mode_t;
62
63 /*! @brief FTM PWM output pulse mode: high-true, low-true or no output */
64 typedef enum _ftm_pwm_level_select
65 {
66 kFTM_NoPwmSignal = 0U, /*!< No PWM output on pin */
67 kFTM_LowTrue, /*!< Low true pulses */
68 kFTM_HighTrue /*!< High true pulses */
69 } ftm_pwm_level_select_t;
70
71 /*! @brief Options to configure a FTM channel's PWM signal */
72 typedef struct _ftm_chnl_pwm_signal_param
73 {
74 ftm_chnl_t chnlNumber; /*!< The channel/channel pair number.
75 In combined mode, this represents the channel pair number. */
76 ftm_pwm_level_select_t level; /*!< PWM output active level select. */
77 uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
78 0 = inactive signal(0% duty cycle)...
79 100 = always active signal (100% duty cycle).*/
80 uint8_t firstEdgeDelayPercent; /*!< Used only in kFTM_AsymmetricalCombinedPwm mode to generate an asymmetrical PWM.
81 Specifies the delay to the first edge in a PWM period.
82 If unsure leave as 0; Should be specified as a
83 percentage of the PWM period */
84 bool enableComplementary; /*!< Used only in combined PWM mode.
85 true: The combined channels output complementary signals;
86 false: The combined channels output same signals; */
87 bool enableDeadtime; /*!< Used only in combined PWM mode with enable complementary.
88 true: The deadtime insertion in this pair of channels is enabled;
89 false: The deadtime insertion in this pair of channels is disabled. */
90 } ftm_chnl_pwm_signal_param_t;
91
92 /*! @brief Options to configure a FTM channel using precise setting.*/
93 typedef struct _ftm_chnl_pwm_config_param
94 {
95 ftm_chnl_t chnlNumber; /*!< The channel/channel pair number.
96 In combined mode, this represents the channel pair number. */
97 ftm_pwm_level_select_t level; /*!< PWM output active level select. */
98 uint16_t dutyValue; /*!< PWM pulse width, the uint of this value is timer ticks. */
99 uint16_t firstEdgeValue; /*!< Used only in kFTM_AsymmetricalCombinedPwm mode to generate an asymmetrical PWM.
100 Specifies the delay to the first edge in a PWM period.
101 If unsure leave as 0, uint of this value is timer ticks. */
102 bool enableComplementary; /*!< Used only in combined PWM mode.
103 true: The combined channels output complementary signals;
104 false: The combined channels output same signals; */
105 bool enableDeadtime; /*!< Used only in combined PWM mode with enable complementary.
106 true: The deadtime insertion in this pair of channels is enabled;
107 false: The deadtime insertion in this pair of channels is disabled. */
108 } ftm_chnl_pwm_config_param_t;
109
110 /*! @brief FlexTimer output compare mode */
111 typedef enum _ftm_output_compare_mode
112 {
113 kFTM_NoOutputSignal = (1U << FTM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */
114 kFTM_ToggleOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (1U << FTM_CnSC_ELSA_SHIFT)), /*!< Toggle output */
115 kFTM_ClearOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (2U << FTM_CnSC_ELSA_SHIFT)), /*!< Clear output */
116 kFTM_SetOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (3U << FTM_CnSC_ELSA_SHIFT)) /*!< Set output */
117 } ftm_output_compare_mode_t;
118
119 /*! @brief FlexTimer input capture edge */
120 typedef enum _ftm_input_capture_edge
121 {
122 kFTM_RisingEdge = (1U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only*/
123 kFTM_FallingEdge = (2U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only*/
124 kFTM_RiseAndFallEdge = (3U << FTM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */
125 } ftm_input_capture_edge_t;
126
127 /*! @brief FlexTimer dual edge capture modes */
128 typedef enum _ftm_dual_edge_capture_mode
129 {
130 kFTM_OneShot = 0U, /*!< One-shot capture mode */
131 kFTM_Continuous = (1U << FTM_CnSC_MSA_SHIFT) /*!< Continuous capture mode */
132 } ftm_dual_edge_capture_mode_t;
133
134 /*! @brief FlexTimer dual edge capture parameters */
135 typedef struct _ftm_dual_edge_capture_param
136 {
137 ftm_dual_edge_capture_mode_t mode; /*!< Dual Edge Capture mode */
138 ftm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
139 ftm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
140 } ftm_dual_edge_capture_param_t;
141
142 /*! @brief FlexTimer quadrature decode modes */
143 typedef enum _ftm_quad_decode_mode
144 {
145 kFTM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
146 kFTM_QuadCountAndDir /*!< Count and direction encoding mode */
147 } ftm_quad_decode_mode_t;
148
149 /*! @brief FlexTimer quadrature phase polarities */
150 typedef enum _ftm_phase_polarity
151 {
152 kFTM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
153 kFTM_QuadPhaseInvert /*!< Phase input signal is inverted */
154 } ftm_phase_polarity_t;
155
156 /*! @brief FlexTimer quadrature decode phase parameters */
157 typedef struct _ftm_phase_param
158 {
159 bool enablePhaseFilter; /*!< True: enable phase filter; false: disable filter */
160 uint32_t phaseFilterVal; /*!< Filter value, used only if phase filter is enabled */
161 ftm_phase_polarity_t phasePolarity; /*!< Phase polarity */
162 } ftm_phase_params_t;
163
164 /*! @brief Structure is used to hold the parameters to configure a FTM fault */
165 typedef struct _ftm_fault_param
166 {
167 bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */
168 bool faultLevel; /*!< True: Fault polarity is active low; in other words, '0' indicates a fault;
169 False: Fault polarity is active high */
170 bool useFaultFilter; /*!< True: Use the filtered fault signal;
171 False: Use the direct path from fault input */
172 } ftm_fault_param_t;
173
174 /*! @brief FlexTimer pre-scaler factor for the dead time insertion*/
175 typedef enum _ftm_deadtime_prescale
176 {
177 kFTM_Deadtime_Prescale_1 = 1U, /*!< Divide by 1 */
178 kFTM_Deadtime_Prescale_4, /*!< Divide by 4 */
179 kFTM_Deadtime_Prescale_16 /*!< Divide by 16 */
180 } ftm_deadtime_prescale_t;
181
182 /*! @brief FlexTimer clock source selection*/
183 typedef enum _ftm_clock_source
184 {
185 kFTM_SystemClock = 1U, /*!< System clock selected */
186 kFTM_FixedClock, /*!< Fixed frequency clock */
187 kFTM_ExternalClock /*!< External clock */
188 } ftm_clock_source_t;
189
190 /*! @brief FlexTimer pre-scaler factor selection for the clock source*/
191 typedef enum _ftm_clock_prescale
192 {
193 kFTM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
194 kFTM_Prescale_Divide_2, /*!< Divide by 2 */
195 kFTM_Prescale_Divide_4, /*!< Divide by 4 */
196 kFTM_Prescale_Divide_8, /*!< Divide by 8 */
197 kFTM_Prescale_Divide_16, /*!< Divide by 16 */
198 kFTM_Prescale_Divide_32, /*!< Divide by 32 */
199 kFTM_Prescale_Divide_64, /*!< Divide by 64 */
200 kFTM_Prescale_Divide_128 /*!< Divide by 128 */
201 } ftm_clock_prescale_t;
202
203 /*! @brief Options for the FlexTimer behaviour in BDM Mode */
204 typedef enum _ftm_bdm_mode
205 {
206 kFTM_BdmMode_0 = 0U,
207 /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V
208 registers bypass the register buffers */
209 kFTM_BdmMode_1,
210 /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to
211 MOD,CNTIN and C(n)V registers bypass the register buffers */
212 kFTM_BdmMode_2,
213 /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode,
214 writes to MOD,CNTIN and C(n)V registers bypass the register buffers */
215 kFTM_BdmMode_3
216 /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and
217 C(n)V registers is in fully functional mode */
218 } ftm_bdm_mode_t;
219
220 /*! @brief Options for the FTM fault control mode */
221 typedef enum _ftm_fault_mode
222 {
223 kFTM_Fault_Disable = 0U, /*!< Fault control is disabled for all channels */
224 kFTM_Fault_EvenChnls, /*!< Enabled for even channels only(0,2,4,6) with manual fault clearing */
225 kFTM_Fault_AllChnlsMan, /*!< Enabled for all channels with manual fault clearing */
226 kFTM_Fault_AllChnlsAuto /*!< Enabled for all channels with automatic fault clearing */
227 } ftm_fault_mode_t;
228
229 /*!
230 * @brief FTM external trigger options
231 * @note Actual available external trigger sources are SoC-specific
232 */
233 typedef enum _ftm_external_trigger
234 {
235 kFTM_Chnl0Trigger = (1U << 4), /*!< Generate trigger when counter equals chnl 0 CnV reg */
236 kFTM_Chnl1Trigger = (1U << 5), /*!< Generate trigger when counter equals chnl 1 CnV reg */
237 kFTM_Chnl2Trigger = (1U << 0), /*!< Generate trigger when counter equals chnl 2 CnV reg */
238 kFTM_Chnl3Trigger = (1U << 1), /*!< Generate trigger when counter equals chnl 3 CnV reg */
239 kFTM_Chnl4Trigger = (1U << 2), /*!< Generate trigger when counter equals chnl 4 CnV reg */
240 kFTM_Chnl5Trigger = (1U << 3), /*!< Generate trigger when counter equals chnl 5 CnV reg */
241 #if defined(FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER) && (FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER)
242 kFTM_Chnl6Trigger =
243 (1U << 8), /*!< Available on certain SoC's, generate trigger when counter equals chnl 6 CnV reg */
244 #endif
245 #if defined(FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER) && (FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER)
246 kFTM_Chnl7Trigger =
247 (1U << 9), /*!< Available on certain SoC's, generate trigger when counter equals chnl 7 CnV reg */
248 #endif
249 kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */
250 #if defined(FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) && (FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER)
251 kFTM_ReloadInitTrigger = (1U << 7) /*!< Available on certain SoC's, trigger on reload point */
252 #endif
253 } ftm_external_trigger_t;
254
255 /*! @brief FlexTimer PWM sync options to update registers with buffer */
256 typedef enum _ftm_pwm_sync_method
257 {
258 kFTM_SoftwareTrigger = FTM_SYNC_SWSYNC_MASK, /*!< Software triggers PWM sync */
259 kFTM_HardwareTrigger_0 = FTM_SYNC_TRIG0_MASK, /*!< Hardware trigger 0 causes PWM sync */
260 kFTM_HardwareTrigger_1 = FTM_SYNC_TRIG1_MASK, /*!< Hardware trigger 1 causes PWM sync */
261 kFTM_HardwareTrigger_2 = FTM_SYNC_TRIG2_MASK /*!< Hardware trigger 2 causes PWM sync */
262 } ftm_pwm_sync_method_t;
263
264 /*!
265 * @brief FTM options available as loading point for register reload
266 * @note Actual available reload points are SoC-specific
267 */
268 typedef enum _ftm_reload_point
269 {
270 kFTM_Chnl0Match = (1U << 0), /*!< Channel 0 match included as a reload point */
271 kFTM_Chnl1Match = (1U << 1), /*!< Channel 1 match included as a reload point */
272 kFTM_Chnl2Match = (1U << 2), /*!< Channel 2 match included as a reload point */
273 kFTM_Chnl3Match = (1U << 3), /*!< Channel 3 match included as a reload point */
274 kFTM_Chnl4Match = (1U << 4), /*!< Channel 4 match included as a reload point */
275 kFTM_Chnl5Match = (1U << 5), /*!< Channel 5 match included as a reload point */
276 kFTM_Chnl6Match = (1U << 6), /*!< Channel 6 match included as a reload point */
277 kFTM_Chnl7Match = (1U << 7), /*!< Channel 7 match included as a reload point */
278 kFTM_CntMax = (1U << 8), /*!< Use in up-down count mode only, reload when counter reaches the maximum value */
279 kFTM_CntMin = (1U << 9), /*!< Use in up-down count mode only, reload when counter reaches the minimum value */
280 kFTM_HalfCycMatch = (1U << 10) /*!< Available on certain SoC's, half cycle match reload point */
281 } ftm_reload_point_t;
282
283 /*!
284 * @brief List of FTM interrupts
285 * @note Actual available interrupts are SoC-specific
286 */
287 typedef enum _ftm_interrupt_enable
288 {
289 kFTM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt */
290 kFTM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt */
291 kFTM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt */
292 kFTM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt */
293 kFTM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt */
294 kFTM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt */
295 kFTM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt */
296 kFTM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt */
297 kFTM_FaultInterruptEnable = (1U << 8), /*!< Fault interrupt */
298 kFTM_TimeOverflowInterruptEnable = (1U << 9), /*!< Time overflow interrupt */
299 kFTM_ReloadInterruptEnable = (1U << 10) /*!< Reload interrupt; Available only on certain SoC's */
300 } ftm_interrupt_enable_t;
301
302 /*!
303 * @brief List of FTM flags
304 * @note Actual available flags are SoC-specific
305 */
306 typedef enum _ftm_status_flags
307 {
308 kFTM_Chnl0Flag = (1U << 0), /*!< Channel 0 Flag */
309 kFTM_Chnl1Flag = (1U << 1), /*!< Channel 1 Flag */
310 kFTM_Chnl2Flag = (1U << 2), /*!< Channel 2 Flag */
311 kFTM_Chnl3Flag = (1U << 3), /*!< Channel 3 Flag */
312 kFTM_Chnl4Flag = (1U << 4), /*!< Channel 4 Flag */
313 kFTM_Chnl5Flag = (1U << 5), /*!< Channel 5 Flag */
314 kFTM_Chnl6Flag = (1U << 6), /*!< Channel 6 Flag */
315 kFTM_Chnl7Flag = (1U << 7), /*!< Channel 7 Flag */
316 kFTM_FaultFlag = (1U << 8), /*!< Fault Flag */
317 kFTM_TimeOverflowFlag = (1U << 9), /*!< Time overflow Flag */
318 kFTM_ChnlTriggerFlag = (1U << 10), /*!< Channel trigger Flag */
319 kFTM_ReloadFlag = (1U << 11) /*!< Reload Flag; Available only on certain SoC's */
320 } ftm_status_flags_t;
321
322 #if !(defined(FSL_FEATURE_FTM_HAS_NO_QDCTRL) && FSL_FEATURE_FTM_HAS_NO_QDCTRL)
323 /*!
324 * @brief List of FTM Quad Decoder flags.
325 */
326 enum
327 {
328 kFTM_QuadDecoderCountingIncreaseFlag = FTM_QDCTRL_QUADIR_MASK, /*!< Counting direction is increasing (FTM counter
329 increment), or the direction is decreasing. */
330 kFTM_QuadDecoderCountingOverflowOnTopFlag = FTM_QDCTRL_TOFDIR_MASK, /*!< Indicates if the TOF bit was set on the top
331 or the bottom of counting. */
332 };
333 #endif
334
335 /*!
336 * @brief FTM configuration structure
337 *
338 * This structure holds the configuration settings for the FTM peripheral. To initialize this
339 * structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a
340 * pointer to the configuration structure instance.
341 *
342 * The configuration structure can be made constant so as to reside in flash.
343 */
344 typedef struct _ftm_config
345 {
346 ftm_clock_prescale_t prescale; /*!< FTM clock prescale value */
347 ftm_bdm_mode_t bdmMode; /*!< FTM behavior in BDM mode */
348 uint32_t pwmSyncMode; /*!< Synchronization methods to use to update buffered registers; Multiple
349 update modes can be used by providing an OR'ed list of options
350 available in enumeration ::ftm_pwm_sync_method_t. */
351 uint32_t reloadPoints; /*!< FTM reload points; When using this, the PWM
352 synchronization is not required. Multiple reload points can be used by providing
353 an OR'ed list of options available in
354 enumeration ::ftm_reload_point_t. */
355 ftm_fault_mode_t faultMode; /*!< FTM fault control mode */
356 uint8_t faultFilterValue; /*!< Fault input filter value */
357 ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */
358 uint32_t deadTimeValue; /*!< The dead time value
359 deadTimeValue's available range is 0-1023 when register has DTVALEX,
360 otherwise its available range is 0-63. */
361 uint32_t extTriggers; /*!< External triggers to enable. Multiple trigger sources can be
362 enabled by providing an OR'ed list of options available in
363 enumeration ::ftm_external_trigger_t. */
364 uint8_t chnlInitState; /*!< Defines the initialization value of the channels in OUTINT register */
365 uint8_t chnlPolarity; /*!< Defines the output polarity of the channels in POL register */
366 bool useGlobalTimeBase; /*!< True: Use of an external global time base is enabled;
367 False: disabled */
368 bool swTriggerResetCount; /*!< FTM counter synchronization activated by software trigger, avtive when (syncMethod &
369 FTM_SYNC_SWSYNC_MASK) != 0U */
370 bool hwTriggerResetCount; /*!< FTM counter synchronization activated by hardware trigger, avtive when (syncMethod &
371 (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK)) != 0U */
372 } ftm_config_t;
373
374 /*******************************************************************************
375 * API
376 ******************************************************************************/
377
378 #if defined(__cplusplus)
379 extern "C" {
380 #endif
381
382 /*!
383 * @name Initialization and deinitialization
384 * @{
385 */
386
387 /*!
388 * @brief Ungates the FTM clock and configures the peripheral for basic operation.
389 *
390 * @note This API should be called at the beginning of the application which is using the FTM driver.
391 * If the FTM instance has only TPM features, please use the TPM driver.
392 *
393 * @param base FTM peripheral base address
394 * @param config Pointer to the user configuration structure.
395 *
396 * @return kStatus_Success indicates success; Else indicates failure.
397 */
398 status_t FTM_Init(FTM_Type *base, const ftm_config_t *config);
399
400 /*!
401 * @brief Gates the FTM clock.
402 *
403 * @param base FTM peripheral base address
404 */
405 void FTM_Deinit(FTM_Type *base);
406
407 /*!
408 * @brief Fills in the FTM configuration structure with the default settings.
409 *
410 * The default values are:
411 * @code
412 * config->prescale = kFTM_Prescale_Divide_1;
413 * config->bdmMode = kFTM_BdmMode_0;
414 * config->pwmSyncMode = kFTM_SoftwareTrigger;
415 * config->reloadPoints = 0;
416 * config->faultMode = kFTM_Fault_Disable;
417 * config->faultFilterValue = 0;
418 * config->deadTimePrescale = kFTM_Deadtime_Prescale_1;
419 * config->deadTimeValue = 0;
420 * config->extTriggers = 0;
421 * config->chnlInitState = 0;
422 * config->chnlPolarity = 0;
423 * config->useGlobalTimeBase = false;
424 * config->hwTriggerResetCount = false;
425 * config->swTriggerResetCount = true;
426 * @endcode
427 * @param config Pointer to the user configuration structure.
428 */
429 void FTM_GetDefaultConfig(ftm_config_t *config);
430
431 /*!
432 * brief Calculates the counter clock prescaler.
433 *
434 * This function calculates the values for SC[PS] bit.
435 *
436 * param base FTM peripheral base address
437 * param counterPeriod_Hz The desired frequency in Hz which corresponding to the time when the counter reaches the
438 * mod value
439 * param srcClock_Hz FTM counter clock in Hz
440 *
441 * return Calculated clock prescaler value, see @ref ftm_clock_prescale_t.
442 */
FTM_CalculateCounterClkDiv(FTM_Type * base,uint32_t counterPeriod_Hz,uint32_t srcClock_Hz)443 static inline ftm_clock_prescale_t FTM_CalculateCounterClkDiv(FTM_Type *base,
444 uint32_t counterPeriod_Hz,
445 uint32_t srcClock_Hz)
446 {
447 uint8_t i;
448 assert((srcClock_Hz / 2U) > counterPeriod_Hz);
449 assert((srcClock_Hz / 128U / 0xFFFFU) <= counterPeriod_Hz);
450 for (i = 0U; i < (uint32_t)kFTM_Prescale_Divide_128; i++)
451 {
452 if ((srcClock_Hz / (1UL << i) / 0xFFFFU) < counterPeriod_Hz)
453 {
454 break;
455 }
456 }
457 return (ftm_clock_prescale_t)i;
458 }
459
460 /*! @}*/
461
462 /*!
463 * @name Channel mode operations
464 * @{
465 */
466
467 /*!
468 * @brief Configures the PWM signal parameters.
469 *
470 * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this
471 * function to configure all FTM channels that are used to output a PWM signal.
472 *
473 * @param base FTM peripheral base address
474 * @param chnlParams Array of PWM channel parameters to configure the channel(s)
475 * @param numOfChnls Number of channels to configure; This should be the size of the array passed in
476 * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t
477 * @param pwmFreq_Hz PWM signal frequency in Hz
478 * @param srcClock_Hz FTM counter clock in Hz
479 *
480 * @return kStatus_Success if the PWM setup was successful
481 * kStatus_Error on failure
482 */
483 status_t FTM_SetupPwm(FTM_Type *base,
484 const ftm_chnl_pwm_signal_param_t *chnlParams,
485 uint8_t numOfChnls,
486 ftm_pwm_mode_t mode,
487 uint32_t pwmFreq_Hz,
488 uint32_t srcClock_Hz);
489
490 /*!
491 * @brief Updates the duty cycle of an active PWM signal.
492 *
493 * @param base FTM peripheral base address
494 * @param chnlNumber The channel/channel pair number. In combined mode, this represents
495 * the channel pair number
496 * @param currentPwmMode The current PWM mode set during PWM setup
497 * @param dutyCyclePercent New PWM pulse width; The value should be between 0 to 100
498 * 0=inactive signal(0% duty cycle)...
499 * 100=active signal (100% duty cycle)
500 * @return kStatus_Success if the PWM update was successful
501 * kStatus_Error on failure
502 */
503 status_t FTM_UpdatePwmDutycycle(FTM_Type *base,
504 ftm_chnl_t chnlNumber,
505 ftm_pwm_mode_t currentPwmMode,
506 uint8_t dutyCyclePercent);
507
508 /*!
509 * @brief Updates the edge level selection for a channel.
510 *
511 * @param base FTM peripheral base address
512 * @param chnlNumber The channel number
513 * @param level The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11.
514 * See the Kinetis SoC reference manual for details about this field.
515 */
516 void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level);
517
518 /*!
519 * @brief Configures the PWM mode parameters.
520 *
521 * Call this function to configure the PWM signal mode, duty cycle in ticks, and edge. Use this
522 * function to configure all FTM channels that are used to output a PWM signal.
523 * Please note that: This API is similar with FTM_SetupPwm() API, but will not set the timer period,
524 * and this API will set channel match value in timer ticks, not period percent.
525 *
526 * @param base FTM peripheral base address
527 * @param chnlParams Array of PWM channel parameters to configure the channel(s)
528 * @param numOfChnls Number of channels to configure; This should be the size of the array passed in
529 * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t
530 *
531 * @return kStatus_Success if the PWM setup was successful
532 * kStatus_Error on failure
533 */
534 status_t FTM_SetupPwmMode(FTM_Type *base,
535 const ftm_chnl_pwm_config_param_t *chnlParams,
536 uint8_t numOfChnls,
537 ftm_pwm_mode_t mode);
538
539 /*!
540 * @brief Enables capturing an input signal on the channel using the function parameters.
541 *
542 * When the edge specified in the captureMode argument occurs on the channel, the FTM counter is
543 * captured into the CnV register. The user has to read the CnV register separately to get this
544 * value. The filter function is disabled if the filterVal argument passed in is 0. The filter
545 * function is available only for channels 0, 1, 2, 3.
546 *
547 * @param base FTM peripheral base address
548 * @param chnlNumber The channel number
549 * @param captureMode Specifies which edge to capture
550 * @param filterValue Filter value, specify 0 to disable filter. Available only for channels 0-3.
551 */
552 void FTM_SetupInputCapture(FTM_Type *base,
553 ftm_chnl_t chnlNumber,
554 ftm_input_capture_edge_t captureMode,
555 uint32_t filterValue);
556
557 /*!
558 * @brief Configures the FTM to generate timed pulses.
559 *
560 * When the FTM counter matches the value of compareVal argument (this is written into CnV reg),
561 * the channel output is changed based on what is specified in the compareMode argument.
562 *
563 * @param base FTM peripheral base address
564 * @param chnlNumber The channel number
565 * @param compareMode Action to take on the channel output when the compare condition is met
566 * @param compareValue Value to be programmed in the CnV register.
567 */
568 void FTM_SetupOutputCompare(FTM_Type *base,
569 ftm_chnl_t chnlNumber,
570 ftm_output_compare_mode_t compareMode,
571 uint32_t compareValue);
572
573 /*!
574 * @brief Configures the dual edge capture mode of the FTM.
575 *
576 * This function sets up the dual edge capture mode on a channel pair. The capture edge for the
577 * channel pair and the capture mode (one-shot or continuous) is specified in the parameter
578 * argument. The filter function is disabled if the filterVal argument passed is zero. The filter
579 * function is available only on channels 0 and 2. The user has to read the channel CnV registers
580 * separately to get the capture values.
581 *
582 * @param base FTM peripheral base address
583 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
584 * @param edgeParam Sets up the dual edge capture function
585 * @param filterValue Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1.
586 */
587 void FTM_SetupDualEdgeCapture(FTM_Type *base,
588 ftm_chnl_t chnlPairNumber,
589 const ftm_dual_edge_capture_param_t *edgeParam,
590 uint32_t filterValue);
591
592 /*! @}*/
593
594 /*!
595 * @brief Sets up the working of the FTM fault inputs protection.
596 *
597 * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and input filter.
598 *
599 * @param base FTM peripheral base address
600 * @param faultNumber FTM fault to configure.
601 * @param faultParams Parameters passed in to set up the fault
602 */
603 void FTM_SetupFaultInput(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams);
604
605 /*!
606 * @name Interrupt Interface
607 * @{
608 */
609
610 /*!
611 * @brief Enables the selected FTM interrupts.
612 *
613 * @param base FTM peripheral base address
614 * @param mask The interrupts to enable. This is a logical OR of members of the
615 * enumeration ::ftm_interrupt_enable_t
616 */
617 void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask);
618
619 /*!
620 * @brief Disables the selected FTM interrupts.
621 *
622 * @param base FTM peripheral base address
623 * @param mask The interrupts to enable. This is a logical OR of members of the
624 * enumeration ::ftm_interrupt_enable_t
625 */
626 void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask);
627
628 /*!
629 * @brief Gets the enabled FTM interrupts.
630 *
631 * @param base FTM peripheral base address
632 *
633 * @return The enabled interrupts. This is the logical OR of members of the
634 * enumeration ::ftm_interrupt_enable_t
635 */
636 uint32_t FTM_GetEnabledInterrupts(FTM_Type *base);
637
638 /*! @}*/
639
640 /*!
641 * @name Status Interface
642 * @{
643 */
644
645 /*!
646 * @brief Gets the FTM status flags.
647 *
648 * @param base FTM peripheral base address
649 *
650 * @return The status flags. This is the logical OR of members of the
651 * enumeration ::ftm_status_flags_t
652 */
653 uint32_t FTM_GetStatusFlags(FTM_Type *base);
654
655 /*!
656 * @brief Clears the FTM status flags.
657 *
658 * @param base FTM peripheral base address
659 * @param mask The status flags to clear. This is a logical OR of members of the
660 * enumeration ::ftm_status_flags_t
661 */
662 void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask);
663
664 /*! @}*/
665
666 /*!
667 * @name Read and write the timer period
668 * @{
669 */
670
671 /*!
672 * @brief Sets the timer period in units of ticks.
673 *
674 * Timers counts from 0 until it equals the count value set here. The count value is written to
675 * the MOD register.
676 *
677 * @note
678 * 1. This API allows the user to use the FTM module as a timer. Do not mix usage
679 * of this API with FTM's PWM setup API's.
680 * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
681 *
682 * @param base FTM peripheral base address
683 * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
684 */
FTM_SetTimerPeriod(FTM_Type * base,uint32_t ticks)685 static inline void FTM_SetTimerPeriod(FTM_Type *base, uint32_t ticks)
686 {
687 base->CNTIN = 0x0U;
688 base->MOD = ticks;
689 }
690
691 /*!
692 * @brief Reads the current timer counting value.
693 *
694 * This function returns the real-time timer counting value in a range from 0 to a
695 * timer period.
696 *
697 * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
698 *
699 * @param base FTM peripheral base address
700 *
701 * @return The current counter value in ticks
702 */
FTM_GetCurrentTimerCount(FTM_Type * base)703 static inline uint32_t FTM_GetCurrentTimerCount(FTM_Type *base)
704 {
705 return (uint32_t)((base->CNT & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT);
706 }
707
708 /*!
709 * @brief Reads the captured value.
710 *
711 * This function returns the captured value of a FTM channel configured in input capture or dual edge capture mode.
712 *
713 * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
714 *
715 * @param base FTM peripheral base address
716 * @param chnlNumber Channel to be read
717 *
718 * @return The captured FTM counter value of the input modes.
719 */
FTM_GetInputCaptureValue(FTM_Type * base,ftm_chnl_t chnlNumber)720 static inline uint32_t FTM_GetInputCaptureValue(FTM_Type *base, ftm_chnl_t chnlNumber)
721 {
722 return (base->CONTROLS[chnlNumber].CnV & FTM_CnV_VAL_MASK);
723 }
724
725 /*! @}*/
726 /*!
727 * @name Timer Start and Stop
728 * @{
729 */
730
731 /*!
732 * @brief Starts the FTM counter.
733 *
734 * @param base FTM peripheral base address
735 * @param clockSource FTM clock source; After the clock source is set, the counter starts running.
736 */
FTM_StartTimer(FTM_Type * base,ftm_clock_source_t clockSource)737 static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource)
738 {
739 uint32_t reg = base->SC;
740
741 reg &= ~(FTM_SC_CLKS_MASK);
742 reg |= FTM_SC_CLKS(clockSource);
743 base->SC = reg;
744 }
745
746 /*!
747 * @brief Stops the FTM counter.
748 *
749 * @param base FTM peripheral base address
750 */
FTM_StopTimer(FTM_Type * base)751 static inline void FTM_StopTimer(FTM_Type *base)
752 {
753 /* Set clock source to none to disable counter */
754 base->SC &= ~(FTM_SC_CLKS_MASK);
755 }
756
757 /*! @}*/
758
759 /*!
760 * @name Software output control
761 * @{
762 */
763
764 /*!
765 * @brief Enables or disables the channel software output control.
766 *
767 * @param base FTM peripheral base address
768 * @param chnlNumber Channel to be enabled or disabled
769 * @param value true: channel output is affected by software output control
770 false: channel output is unaffected by software output control
771 */
FTM_SetSoftwareCtrlEnable(FTM_Type * base,ftm_chnl_t chnlNumber,bool value)772 static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
773 {
774 if (value)
775 {
776 base->SWOCTRL |= (1UL << (uint32_t)chnlNumber);
777 }
778 else
779 {
780 base->SWOCTRL &= ~(1UL << (uint32_t)chnlNumber);
781 }
782 }
783
784 /*!
785 * @brief Sets the channel software output control value.
786 *
787 * @param base FTM peripheral base address.
788 * @param chnlNumber Channel to be configured
789 * @param value true to set 1, false to set 0
790 */
FTM_SetSoftwareCtrlVal(FTM_Type * base,ftm_chnl_t chnlNumber,bool value)791 static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
792 {
793 if (value)
794 {
795 base->SWOCTRL |= (1UL << ((uint32_t)chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT));
796 }
797 else
798 {
799 base->SWOCTRL &= ~(1UL << ((uint32_t)chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT));
800 }
801 }
802
803 /*! @}*/
804
805 /*!
806 * @brief Enables or disables the FTM global time base signal generation to other FTMs.
807 *
808 * @param base FTM peripheral base address
809 * @param enable true to enable, false to disable
810 */
FTM_SetGlobalTimeBaseOutputEnable(FTM_Type * base,bool enable)811 static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable)
812 {
813 if (enable)
814 {
815 base->CONF |= FTM_CONF_GTBEOUT_MASK;
816 }
817 else
818 {
819 base->CONF &= ~FTM_CONF_GTBEOUT_MASK;
820 }
821 }
822
823 /*!
824 * @brief Sets the FTM peripheral timer channel output mask.
825 *
826 * @param base FTM peripheral base address
827 * @param chnlNumber Channel to be configured
828 * @param mask true: masked, channel is forced to its inactive state; false: unmasked
829 */
FTM_SetOutputMask(FTM_Type * base,ftm_chnl_t chnlNumber,bool mask)830 static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask)
831 {
832 if (mask)
833 {
834 base->OUTMASK |= (1UL << (uint32_t)chnlNumber);
835 }
836 else
837 {
838 base->OUTMASK &= ~(1UL << (uint32_t)chnlNumber);
839 }
840 }
841
842 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
843 /*!
844 * @brief Allows users to enable an output on an FTM channel.
845 *
846 * To enable the PWM channel output call this function with val=true. For input mode,
847 * call this function with val=false.
848 *
849 * @param base FTM peripheral base address
850 * @param chnlNumber Channel to be configured
851 * @param value true: enable output; false: output is disabled, used in input mode
852 */
FTM_SetPwmOutputEnable(FTM_Type * base,ftm_chnl_t chnlNumber,bool value)853 static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
854 {
855 if (value)
856 {
857 base->SC |= (1UL << ((uint32_t)chnlNumber + FTM_SC_PWMEN0_SHIFT));
858 }
859 else
860 {
861 base->SC &= ~(1UL << ((uint32_t)chnlNumber + FTM_SC_PWMEN0_SHIFT));
862 }
863 }
864 #endif
865
866 /*!
867 * @name Channel pair operations
868 * @{
869 */
870
871 /*!
872 * @brief This function enables/disables the fault control in a channel pair.
873 *
874 * @param base FTM peripheral base address
875 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
876 * @param value true: Enable fault control for this channel pair; false: No fault control
877 */
FTM_SetFaultControlEnable(FTM_Type * base,ftm_chnl_t chnlPairNumber,bool value)878 static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
879 {
880 /* Fault input is not supported if the instance has only basic feature.*/
881 #if (defined(FSL_FEATURE_FTM_HAS_BASIC_FEATURE_ONLY_INSTANCE) && FSL_FEATURE_FTM_HAS_BASIC_FEATURE_ONLY_INSTANCE)
882 assert(0 == FSL_FEATURE_FTM_IS_BASIC_FEATURE_ONLY_INSTANCEn(base));
883 #endif
884 if (value)
885 {
886 base->COMBINE |=
887 (1UL << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumber)));
888 }
889 else
890 {
891 base->COMBINE &=
892 ~(1UL << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumber)));
893 }
894 }
895
896 /*!
897 * @brief This function enables/disables the dead time insertion in a channel pair.
898 *
899 * @param base FTM peripheral base address
900 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
901 * @param value true: Insert dead time in this channel pair; false: No dead time inserted
902 */
FTM_SetDeadTimeEnable(FTM_Type * base,ftm_chnl_t chnlPairNumber,bool value)903 static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
904 {
905 if (value)
906 {
907 base->COMBINE |= (1UL << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumber)));
908 }
909 else
910 {
911 base->COMBINE &= ~(1UL << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumber)));
912 }
913 }
914
915 /*!
916 * @brief This function enables/disables complementary mode in a channel pair.
917 *
918 * @param base FTM peripheral base address
919 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
920 * @param value true: enable complementary mode; false: disable complementary mode
921 */
FTM_SetComplementaryEnable(FTM_Type * base,ftm_chnl_t chnlPairNumber,bool value)922 static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
923 {
924 if (value)
925 {
926 base->COMBINE |= (1UL << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumber)));
927 }
928 else
929 {
930 base->COMBINE &= ~(1UL << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumber)));
931 }
932 }
933
934 /*!
935 * @brief This function enables/disables inverting control in a channel pair.
936 *
937 * @param base FTM peripheral base address
938 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
939 * @param value true: enable inverting; false: disable inverting
940 */
FTM_SetInvertEnable(FTM_Type * base,ftm_chnl_t chnlPairNumber,bool value)941 static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
942 {
943 if (value)
944 {
945 base->INVCTRL |= (1UL << (uint32_t)chnlPairNumber);
946 }
947 else
948 {
949 base->INVCTRL &= ~(1UL << (uint32_t)chnlPairNumber);
950 }
951 }
952
953 /*! @}*/
954
955 /*!
956 * @name Quad Decoder
957 * @{
958 */
959
960 /*!
961 * @brief Configures the parameters and activates the quadrature decoder mode.
962 *
963 * @param base FTM peripheral base address
964 * @param phaseAParams Phase A configuration parameters
965 * @param phaseBParams Phase B configuration parameters
966 * @param quadMode Selects encoding mode used in quadrature decoder mode
967 */
968 void FTM_SetupQuadDecode(FTM_Type *base,
969 const ftm_phase_params_t *phaseAParams,
970 const ftm_phase_params_t *phaseBParams,
971 ftm_quad_decode_mode_t quadMode);
972
973 #if !(defined(FSL_FEATURE_FTM_HAS_NO_QDCTRL) && FSL_FEATURE_FTM_HAS_NO_QDCTRL)
974 /*!
975 * @brief Gets the FTM Quad Decoder flags.
976 *
977 * @param base FTM peripheral base address.
978 * @return Flag mask of FTM Quad Decoder, see _ftm_quad_decoder_flags.
979 */
FTM_GetQuadDecoderFlags(FTM_Type * base)980 static inline uint32_t FTM_GetQuadDecoderFlags(FTM_Type *base)
981 {
982 return base->QDCTRL & (FTM_QDCTRL_QUADIR_MASK | FTM_QDCTRL_TOFDIR_MASK);
983 }
984 #endif
985
986 /*!
987 * @brief Sets the modulo values for Quad Decoder.
988 *
989 * The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the
990 * counter goes over, the counter value goes to the other side and decrease/increase again.
991 *
992 * @param base FTM peripheral base address.
993 * @param startValue The low limit value for Quad Decoder counter.
994 * @param overValue The high limit value for Quad Decoder counter.
995 */
FTM_SetQuadDecoderModuloValue(FTM_Type * base,uint32_t startValue,uint32_t overValue)996 static inline void FTM_SetQuadDecoderModuloValue(FTM_Type *base, uint32_t startValue, uint32_t overValue)
997 {
998 base->CNTIN = startValue;
999 base->MOD = overValue;
1000 }
1001
1002 /*!
1003 * @brief Gets the current Quad Decoder counter value.
1004 *
1005 * @param base FTM peripheral base address.
1006 * @return Current quad Decoder counter value.
1007 */
FTM_GetQuadDecoderCounterValue(FTM_Type * base)1008 static inline uint32_t FTM_GetQuadDecoderCounterValue(FTM_Type *base)
1009 {
1010 return base->CNT;
1011 }
1012
1013 /*!
1014 * @brief Clears the current Quad Decoder counter value.
1015 *
1016 * The counter is set as the initial value.
1017 *
1018 * @param base FTM peripheral base address.
1019 */
FTM_ClearQuadDecoderCounterValue(FTM_Type * base)1020 static inline void FTM_ClearQuadDecoderCounterValue(FTM_Type *base)
1021 {
1022 base->CNT = base->CNTIN;
1023 }
1024
1025 /*! @}*/
1026
1027 /*!
1028 * @brief Enables or disables the FTM software trigger for PWM synchronization.
1029 *
1030 * @param base FTM peripheral base address
1031 * @param enable true: software trigger is selected, false: software trigger is not selected
1032 */
FTM_SetSoftwareTrigger(FTM_Type * base,bool enable)1033 static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable)
1034 {
1035 if (enable)
1036 {
1037 base->SYNC |= FTM_SYNC_SWSYNC_MASK;
1038 }
1039 else
1040 {
1041 base->SYNC &= ~FTM_SYNC_SWSYNC_MASK;
1042 }
1043 }
1044
1045 /*!
1046 * @brief Enables or disables the FTM write protection.
1047 *
1048 * @param base FTM peripheral base address
1049 * @param enable true: Write-protection is enabled, false: Write-protection is disabled
1050 */
FTM_SetWriteProtection(FTM_Type * base,bool enable)1051 static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable)
1052 {
1053 /* Configure write protection */
1054 if (enable)
1055 {
1056 base->FMS |= FTM_FMS_WPEN_MASK;
1057 }
1058 else
1059 {
1060 base->MODE |= FTM_MODE_WPDIS_MASK;
1061 }
1062 }
1063
1064 #if defined(FSL_FEATURE_FTM_HAS_DMA_SUPPORT) && FSL_FEATURE_FTM_HAS_DMA_SUPPORT
1065 /*!
1066 * @brief Enable DMA transfer or not.
1067 *
1068 * Note: CHnIE bit needs to be set when calling this API. The channel DMA transfer request
1069 * is generated and the channel interrupt is not generated if (CHnF = 1) when DMA and CHnIE
1070 * bits are set.
1071 *
1072 * @param base FTM peripheral base address.
1073 * @param chnlNumber Channel to be configured
1074 * @param enable true to enable, false to disable
1075 */
FTM_EnableDmaTransfer(FTM_Type * base,ftm_chnl_t chnlNumber,bool enable)1076 static inline void FTM_EnableDmaTransfer(FTM_Type *base, ftm_chnl_t chnlNumber, bool enable)
1077 {
1078 if (enable)
1079 {
1080 /* Enable DMA transfer */
1081 base->CONTROLS[chnlNumber].CnSC |= FTM_CnSC_DMA_MASK;
1082 }
1083 else
1084 {
1085 /* Disable DMA transfer */
1086 base->CONTROLS[chnlNumber].CnSC &= ~FTM_CnSC_DMA_MASK;
1087 }
1088 }
1089 #endif /* FSL_FEATURE_FTM_HAS_DMA_SUPPORT */
1090
1091 /*!
1092 * @brief Enable the LDOK bit
1093 *
1094 * This function enables loading updated values.
1095 *
1096 * @param base FTM peripheral base address
1097 * @param value true: loading updated values is enabled; false: loading updated values is disabled.
1098 */
FTM_SetLdok(FTM_Type * base,bool value)1099 static inline void FTM_SetLdok(FTM_Type *base, bool value)
1100 {
1101 if (value)
1102 {
1103 base->PWMLOAD |= FTM_PWMLOAD_LDOK_MASK;
1104 }
1105 else
1106 {
1107 base->PWMLOAD &= ~FTM_PWMLOAD_LDOK_MASK;
1108 }
1109 }
1110
1111 #if defined(FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) && FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD
1112 /*!
1113 * @brief Sets the half cycle relade period in units of ticks.
1114 *
1115 * This function can be callled to set the half-cycle reload value when half-cycle matching is enabled as a reload
1116 * point.
1117 * Note: Need enable kFTM_HalfCycMatch as reload point, and when this API call after FTM_StartTimer(), the new
1118 * HCR value will not be active until next reload point (need call FTM_SetLdok to set LDOK) or register synchronization.
1119 *
1120 * @param base FTM peripheral base address
1121 * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
1122 */
FTM_SetHalfCycReloadMatchValue(FTM_Type * base,uint32_t ticks)1123 static inline void FTM_SetHalfCycReloadMatchValue(FTM_Type *base, uint32_t ticks)
1124 {
1125 base->HCR = ticks;
1126 }
1127 #endif /* FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD */
1128
1129 #if defined(FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT) && FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT
1130 /*!
1131 * @brief Set load frequency value.
1132 *
1133 * @param base FTM peripheral base address.
1134 *
1135 * @param loadfreq PWM reload frequency, range: 0 ~ 31.
1136 */
FTM_SetLoadFreq(FTM_Type * base,uint32_t loadfreq)1137 static inline void FTM_SetLoadFreq(FTM_Type *base, uint32_t loadfreq)
1138 {
1139 uint32_t reg = base->CONF;
1140
1141 reg &= ~(FTM_CONF_LDFQ_MASK);
1142 reg |= FTM_CONF_LDFQ(loadfreq);
1143 base->CONF = reg;
1144 }
1145 #endif /* FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT */
1146
1147 #if defined(__cplusplus)
1148 }
1149 #endif
1150
1151 /*! @}*/
1152
1153 #endif /* _FSL_FTM_H_*/
1154
