1 /*
2 * Copyright (c) 2016 Linaro Limited
3 * Copyright 2024 NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/kernel.h>
9 #include <zephyr/device.h>
10 #include <string.h>
11 #include <zephyr/drivers/flash.h>
12 #include <errno.h>
13 #include <zephyr/init.h>
14 #include <soc.h>
15 #include <zephyr/sys/barrier.h>
16 #include "flash_priv.h"
17
18 #include "fsl_common.h"
19
20 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
21 #include <zephyr/logging/log.h>
22 LOG_MODULE_REGISTER(flash_mcux);
23
24
25 #if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, nxp_kinetis_ftfa))
26 #define DT_DRV_COMPAT nxp_kinetis_ftfa
27 #elif DT_NODE_HAS_STATUS_OKAY(DT_INST(0, nxp_kinetis_ftfe))
28 #define DT_DRV_COMPAT nxp_kinetis_ftfe
29 #elif DT_NODE_HAS_STATUS_OKAY(DT_INST(0, nxp_kinetis_ftfl))
30 #define DT_DRV_COMPAT nxp_kinetis_ftfl
31 #elif DT_NODE_HAS_STATUS_OKAY(DT_INST(0, nxp_iap_fmc55))
32 #define DT_DRV_COMPAT nxp_iap_fmc55
33 #define SOC_HAS_IAP 1
34 #elif DT_NODE_HAS_STATUS_OKAY(DT_INST(0, nxp_iap_fmc553))
35 #define DT_DRV_COMPAT nxp_iap_fmc553
36 #define SOC_HAS_IAP 1
37 #elif DT_NODE_HAS_STATUS_OKAY(DT_INST(0, nxp_msf1))
38 #define DT_DRV_COMPAT nxp_msf1
39 #define SOC_HAS_MSF1 1
40 #else
41 #error No matching compatible for soc_flash_mcux.c
42 #endif
43
44 #if defined(SOC_HAS_IAP) && !defined(CONFIG_SOC_LPC55S36)
45 #include "fsl_iap.h"
46 #elif defined(CONFIG_SOC_MCXA156)
47 #include "fsl_romapi.h"
48 #define FLASH_Erase FLASH_EraseSector
49 #define FLASH_Program FLASH_ProgramPhrase
50 #elif defined(CONFIG_MCUX_FLASH_K4_API)
51 #include "fsl_k4_flash.h"
52 #else
53 #include "fsl_flash.h"
54 #endif /* SOC_HAS_IAP && !CONFIG_SOC_LPC55S36*/
55
56 #define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
57
58 #if defined(CONFIG_CHECK_BEFORE_READING) && !defined(CONFIG_SOC_LPC55S36)
59 #define FMC_STATUS_FAIL FLASH_INT_CLR_ENABLE_FAIL_MASK
60 #define FMC_STATUS_ERR FLASH_INT_CLR_ENABLE_ERR_MASK
61 #define FMC_STATUS_DONE FLASH_INT_CLR_ENABLE_DONE_MASK
62 #define FMC_STATUS_ECC FLASH_INT_CLR_ENABLE_ECC_ERR_MASK
63
64 #define FMC_STATUS_FAILURES \
65 (FMC_STATUS_FAIL | FMC_STATUS_ERR | FMC_STATUS_ECC)
66
67 #define FMC_CMD_BLANK_CHECK 5
68 #define FMC_CMD_MARGIN_CHECK 6
69
70 /* Issue single command that uses an a start and stop address. */
get_cmd_status(uint32_t cmd,uint32_t addr,size_t len)71 static uint32_t get_cmd_status(uint32_t cmd, uint32_t addr, size_t len)
72 {
73 FLASH_Type *p_fmc = (FLASH_Type *)DT_INST_REG_ADDR(0);
74 uint32_t status;
75
76 /* issue low level command */
77 p_fmc->INT_CLR_STATUS = 0xF;
78 p_fmc->STARTA = (addr>>4) & 0x3FFFF;
79 p_fmc->STOPA = ((addr+len-1)>>4) & 0x3FFFF;
80 p_fmc->CMD = cmd;
81 barrier_dsync_fence_full();
82 barrier_isync_fence_full();
83
84 /* wait for command to be done */
85 while (!(p_fmc->INT_STATUS & FMC_STATUS_DONE))
86 ;
87
88 /* get read status and then clear it */
89 status = p_fmc->INT_STATUS;
90 p_fmc->INT_CLR_STATUS = 0xF;
91
92 return status;
93 }
94
95 /* This function prevents erroneous reading. Some ECC enabled devices will
96 * crash when reading an erased area.
97 */
is_area_readable(uint32_t addr,size_t len)98 static status_t is_area_readable(uint32_t addr, size_t len)
99 {
100 uint32_t key;
101 status_t status;
102
103 key = irq_lock();
104
105 /* If the area was erased, ECC errors are triggered on read. */
106 status = get_cmd_status(FMC_CMD_BLANK_CHECK, addr, len);
107 if (!(status & FMC_STATUS_FAIL)) {
108 LOG_DBG("read request on erased addr:0x%08x size:%d",
109 addr, len);
110 irq_unlock(key);
111 return -ENODATA;
112 }
113
114 irq_unlock(key);
115
116 return 0;
117 }
118 #endif /* CONFIG_CHECK_BEFORE_READING && ! CONFIG_SOC_LPC55S36 */
119
120 #define SOC_FLASH_NEED_CLEAR_CACHES 1
121 #ifdef CONFIG_SOC_SERIES_MCXW
clear_flash_caches(void)122 static void clear_flash_caches(void)
123 {
124 volatile uint32_t *const smscm_ocmdr0 = (volatile uint32_t *)0x40015400;
125 /* this bit clears the flash cache */
126 *smscm_ocmdr0 |= BIT(8);
127 volatile uint32_t *mcm_cpcr2 = (volatile uint32_t *)0xe0080034;
128 /* this bit clears the code cache */
129 *mcm_cpcr2 |= BIT(0);
130 }
131 #elif CONFIG_SOC_SERIES_MCXN
clear_flash_caches(void)132 static void clear_flash_caches(void)
133 {
134 volatile uint32_t *const nvm_ctrl = (volatile uint32_t *)0x40000400;
135 /* this bit clears the flash cache */
136 *nvm_ctrl |= BIT(5);
137 volatile uint32_t *const lpcac_ctrl = (volatile uint32_t *)0x40000824;
138 /* this bit clears the code cache */
139 *lpcac_ctrl |= BIT(1);
140 }
141 #else
142 #undef SOC_FLASH_NEED_CLEAR_CACHES
143 #define clear_flash_caches(...)
144 #endif
145
146 struct flash_priv {
147 flash_config_t config;
148 /*
149 * HACK: flash write protection is managed in software.
150 */
151 struct k_sem write_lock;
152 uint32_t pflash_block_base;
153 };
154
155 static const struct flash_parameters flash_mcux_parameters = {
156 #if DT_NODE_HAS_PROP(SOC_NV_FLASH_NODE, write_block_size)
157 .write_block_size = DT_PROP(SOC_NV_FLASH_NODE, write_block_size),
158 #else
159 .write_block_size = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE,
160 #endif
161 .erase_value = 0xff,
162 };
163
164 /*
165 * Interrupt vectors could be executed from flash hence the need for locking.
166 * The underlying MCUX driver takes care of copying the functions to SRAM.
167 *
168 * For more information, see the application note below on Read-While-Write
169 * http://cache.freescale.com/files/32bit/doc/app_note/AN4695.pdf
170 *
171 */
172
flash_mcux_erase(const struct device * dev,off_t offset,size_t len)173 static int flash_mcux_erase(const struct device *dev, off_t offset,
174 size_t len)
175 {
176 struct flash_priv *priv = dev->data;
177 uint32_t addr;
178 status_t rc;
179 unsigned int key;
180
181 if (k_sem_take(&priv->write_lock, K_FOREVER)) {
182 return -EACCES;
183 }
184
185 addr = offset + priv->pflash_block_base;
186
187 key = irq_lock();
188 rc = FLASH_Erase(&priv->config,
189 #if CONFIG_MCUX_FLASH_K4_API
190 (FMU_Type *) DT_INST_REG_ADDR(0),
191 #endif
192 addr, len, kFLASH_ApiEraseKey);
193
194 if (IS_ENABLED(SOC_FLASH_NEED_CLEAR_CACHES)) {
195 clear_flash_caches();
196 }
197
198 irq_unlock(key);
199
200 k_sem_give(&priv->write_lock);
201
202 return (rc == kStatus_Success) ? 0 : -EINVAL;
203 }
204
205
206 /*
207 * @brief Read a flash memory area.
208 *
209 * @param dev Device struct
210 * @param offset The address's offset
211 * @param data The buffer to store or read the value
212 * @param length The size of the buffer
213 * @return 0 on success,
214 * -EIO for erroneous area
215 */
flash_mcux_read(const struct device * dev,off_t offset,void * data,size_t len)216 static int flash_mcux_read(const struct device *dev, off_t offset,
217 void *data, size_t len)
218 {
219 struct flash_priv *priv = dev->data;
220 uint32_t addr;
221 status_t rc = 0;
222
223 /*
224 * The MCUX supports different flash chips whose valid ranges are
225 * hidden below the API: until the API export these ranges, we can not
226 * do any generic validation
227 */
228 addr = offset + priv->pflash_block_base;
229
230 #ifdef CONFIG_CHECK_BEFORE_READING
231 /*
232 * Ensure the area is readable, since a direct access may cause faults
233 * on erased or otherwise unreadable pages. Emulate erased pages,
234 * return other errors.
235 */
236 #ifdef CONFIG_SOC_LPC55S36
237 /* On LPC55S36, use a HAL function to safely copy from Flash. */
238 rc = FLASH_Read(&priv->config, addr, data, len);
239 switch (rc) {
240 case kStatus_FLASH_Success:
241 rc = 0;
242 break;
243 case kStatus_FLASH_EccError:
244 /* Check id the ECC issue is due to the Flash being erased
245 * ("addr" and "len" must be word-aligned for this call).
246 */
247 rc = FLASH_VerifyErase(&priv->config,
248 ROUND_DOWN(addr, 4),
249 ROUND_DOWN(addr + len + 3, 4) - ROUND_DOWN(addr, 4));
250 if (rc == kStatus_FLASH_Success) {
251 rc = -ENODATA;
252 } else {
253 rc = -EIO;
254 }
255 break;
256 default:
257 rc = -EIO;
258 break;
259 }
260 #else /* CONFIG_SOC_LPC55S36 */
261 /* On all other targets, check if the Flash area is readable.
262 * If so, copy data from it directly.
263 */
264 rc = is_area_readable(addr, len);
265 if (!rc) {
266 memcpy(data, (void *) addr, len);
267 }
268 #endif /* CONFIG_SOC_LPC55S36 */
269
270 if (rc == -ENODATA) {
271 /* Erased area, return dummy data as an erased page. */
272 memset(data, 0xFF, len);
273 rc = 0;
274 }
275 #else /* CONFIG_CHECK_BEFORE_READING */
276 /* No safety checks, directly copy the memory mapped data. */
277 memcpy(data, (void *) addr, len);
278 #endif /* CONFIG_CHECK_BEFORE_READING */
279
280 return rc;
281 }
282
flash_mcux_write(const struct device * dev,off_t offset,const void * data,size_t len)283 static int flash_mcux_write(const struct device *dev, off_t offset,
284 const void *data, size_t len)
285 {
286 struct flash_priv *priv = dev->data;
287 uint32_t addr;
288 status_t rc;
289 unsigned int key;
290
291 if (k_sem_take(&priv->write_lock, K_FOREVER)) {
292 return -EACCES;
293 }
294
295 addr = offset + priv->pflash_block_base;
296
297 key = irq_lock();
298 rc = FLASH_Program(&priv->config,
299 #if CONFIG_MCUX_FLASH_K4_API
300 (FMU_Type *) DT_INST_REG_ADDR(0),
301 #endif
302 addr, (uint8_t *) data, len);
303
304 if (IS_ENABLED(SOC_FLASH_NEED_CLEAR_CACHES)) {
305 clear_flash_caches();
306 }
307
308 irq_unlock(key);
309
310 k_sem_give(&priv->write_lock);
311
312 return (rc == kStatus_Success) ? 0 : -EINVAL;
313 }
314
315 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
316 static const struct flash_pages_layout dev_layout = {
317 .pages_count = DT_REG_SIZE(SOC_NV_FLASH_NODE) /
318 DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
319 .pages_size = DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
320 };
321
flash_mcux_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)322 static void flash_mcux_pages_layout(const struct device *dev,
323 const struct flash_pages_layout **layout,
324 size_t *layout_size)
325 {
326 *layout = &dev_layout;
327 *layout_size = 1;
328 }
329 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
330
331 static const struct flash_parameters *
flash_mcux_get_parameters(const struct device * dev)332 flash_mcux_get_parameters(const struct device *dev)
333 {
334 ARG_UNUSED(dev);
335
336 return &flash_mcux_parameters;
337 }
338
339 static struct flash_priv flash_data;
340
341 static DEVICE_API(flash, flash_mcux_api) = {
342 .erase = flash_mcux_erase,
343 .write = flash_mcux_write,
344 .read = flash_mcux_read,
345 .get_parameters = flash_mcux_get_parameters,
346 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
347 .page_layout = flash_mcux_pages_layout,
348 #endif
349 };
350
351 #if (defined(SOC_HAS_IAP) || defined(SOC_HAS_MSF1)) && !defined(CONFIG_MCUX_FLASH_K4_API)
352 #define FLASH_PROP_BLOCK_BASE kFLASH_PropertyPflashBlockBaseAddr
353 #else
354 #define FLASH_PROP_BLOCK_BASE kFLASH_PropertyPflash0BlockBaseAddr
355 #endif
356
flash_mcux_init(const struct device * dev)357 static int flash_mcux_init(const struct device *dev)
358 {
359 struct flash_priv *priv = dev->data;
360 uint32_t pflash_block_base;
361 status_t rc;
362
363 k_sem_init(&priv->write_lock, 1, 1);
364
365 rc = FLASH_Init(&priv->config);
366
367 FLASH_GetProperty(&priv->config, FLASH_PROP_BLOCK_BASE, &pflash_block_base);
368
369 priv->pflash_block_base = (uint32_t) pflash_block_base;
370
371 return (rc == kStatus_Success) ? 0 : -EIO;
372 }
373
374 DEVICE_DT_INST_DEFINE(0, flash_mcux_init, NULL,
375 &flash_data, NULL, POST_KERNEL,
376 CONFIG_FLASH_INIT_PRIORITY, &flash_mcux_api);
377
