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Searched refs:FIFOSTAT (Results 1 – 25 of 56) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcomm/usart/
Dfsl_usart.c621 while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) in USART_WriteBlocking()
623 while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) in USART_WriteBlocking()
695 while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) in USART_ReadBlocking()
697 while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) in USART_ReadBlocking()
709 if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) in USART_ReadBlocking()
712 base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; in USART_ReadBlocking()
891 ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); in USART_TransferGetSendCount()
1118 if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) in USART_TransferHandleIRQ()
1121 base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; in USART_TransferHandleIRQ()
1131 if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) in USART_TransferHandleIRQ()
[all …]
Dfsl_usart.h495 … return (base->FIFOSTAT & 0xFF0000FFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); in USART_GetStatusFlags()
519 base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); in USART_ClearStatusFlags()
736 return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); in USART_GetRxFifoCount()
747 return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); in USART_GetTxFifoCount()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcomm/i2s/
Dfsl_i2s.c185 while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) in I2S_EmptyTxFifo()
195 while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) in I2S_EmptyTxFifo()
201 return ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) ? kStatus_Fail : kStatus_Success; in I2S_EmptyTxFifo()
835 base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); in I2S_TxHandleIRQ()
849 while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) in I2S_TxHandleIRQ()
1021 base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); in I2S_TxHandleIRQ()
1044 base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); in I2S_RxHandleIRQ()
1049 while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) in I2S_RxHandleIRQ()
1183 base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); in I2S_RxHandleIRQ()
1196 base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); in I2S_RxHandleIRQ()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcomm/spi/
Dfsl_spi.c559 base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; in SPI_MasterTransferBlocking()
578 if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) in SPI_MasterTransferBlocking()
597 … if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && in SPI_MasterTransferBlocking()
635 while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) in SPI_MasterTransferBlocking()
637 while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) in SPI_MasterTransferBlocking()
697 base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; in SPI_MasterTransferNonBlocking()
919 if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) in SPI_TransferHandleIRQInternal()
948 …if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDept… in SPI_TransferHandleIRQInternal()
Dfsl_spi.h441 return base->FIFOSTAT; in SPI_GetStatusFlags()
Dfsl_spi_dma.c244 base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; in SPI_MasterTransferDMA()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h3696 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
6964 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
9322 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h3902 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
7267 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
10357 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
DLPC54114_cm4.h3913 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
7278 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
10370 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h3914 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
7279 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
10371 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h4949 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
10578 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
15342 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h5292 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
11352 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
16307 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h5295 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
10708 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
15663 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h5357 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
11370 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
16134 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h9518 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
14931 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
19886 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h8632 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
13959 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
18278 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h9443 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
14856 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
19811 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h9516 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
15576 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
20531 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h9195 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
15471 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
20235 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h9195 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
15471 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
20235 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h13490 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
19463 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
24115 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h9439 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
15499 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
20454 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h9603 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
16263 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
21027 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h8997 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
14665 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
18984 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h9514 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
15777 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member
20732 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ member

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