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Searched refs:DevAssert (Results 1 – 25 of 30) sorted by relevance

12

/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip.c268 DevAssert(EMIOS_PWM_IP_INSTANCE_COUNT > Instance); in Emios_Pwm_Ip_GetCounterBusPeriod()
269 DevAssert(EMIOS_PWM_IP_CHANNEL_COUNT > Channel); in Emios_Pwm_Ip_GetCounterBusPeriod()
277 DevAssert(0xFFU != MasterBusCh); in Emios_Pwm_Ip_GetCounterBusPeriod()
330 DevAssert(NULL_PTR != UserChCfg); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
331 DevAssert(EMIOS_PWM_IP_INSTANCE_COUNT > Instance); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
332 DevAssert(EMIOS_PWM_IP_CHANNEL_COUNT > UserChCfg->ChannelId); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
334 DevAssert((UserChCfg->Mode == EMIOS_PWM_IP_MODE_OPWFMB_FLAG) || in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
337 …DevAssert(TRUE == Emios_Pwm_Ip_ValidateMode(Instance, UserChCfg->ChannelId, EMIOS_PWM_IP_HW_MODE_O… in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
339 DevAssert(EMIOS_PWM_IP_MIN_CNT_VAL < UserChCfg->PeriodCount); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
340 DevAssert(UserChCfg->DutyCycle <= UserChCfg->PeriodCount); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c164 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_Init()
165 DevAssert(ConfigPtr != NULL_PTR); in Emios_Mcl_Ip_Init()
266 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_EnableChannel()
267 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT); in Emios_Mcl_Ip_EnableChannel()
278 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_DisableChannel()
279 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT); in Emios_Mcl_Ip_DisableChannel()
290 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_ComparatorTransferEnable()
291 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL); in Emios_Mcl_Ip_ComparatorTransferEnable()
303 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_ComparatorTransferDisable()
304 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL); in Emios_Mcl_Ip_ComparatorTransferDisable()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip.c519 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_Init()
520 DevAssert(userConfig != NULL_PTR); in Emios_Icu_Ip_Init()
671 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_Deinit()
759 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetSleepMode()
760 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetSleepMode()
761 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED); in Emios_Icu_Ip_SetSleepMode()
772 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetNormalMode()
773 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetNormalMode()
793 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetActivation()
794 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetActivation()
[all …]
DSiul2_Icu_Ip.c223 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_DeInit()
277 DevAssert(userConfig->numChannels <= (uint8)SIUL2_ICU_IP_NUM_OF_CHANNELS); in Siul2_Icu_Ip_Init()
278 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_Init()
374 DevAssert(hwChannel < (uint8)SIUL2_ICU_IP_NUM_OF_CHANNELS); in Siul2_Icu_Ip_SetActivationCondition()
375 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_SetActivationCondition()
411 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_GetInputState()
412 DevAssert(hwChannel < SIUL2_ICU_IP_NUM_OF_CHANNELS); in Siul2_Icu_Ip_GetInputState()
435 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_SetClockMode()
453 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_EnableInterrupt()
454 DevAssert(hwChannel < SIUL2_ICU_IP_NUM_OF_CHANNELS); in Siul2_Icu_Ip_EnableInterrupt()
[all …]
DWkpu_Ip.c406 DevAssert(instance < WKPU_INSTANCE_COUNT); in Wkpu_Ip_EnableInterrupt()
407 DevAssert(hwChannel < WKPU_IP_NUM_OF_CHANNELS); in Wkpu_Ip_EnableInterrupt()
469 DevAssert(instance < WKPU_INSTANCE_COUNT); in Wkpu_Ip_DisableInterrupt()
470 DevAssert(hwChannel < WKPU_IP_NUM_OF_CHANNELS); in Wkpu_Ip_DisableInterrupt()
530 DevAssert(instance < WKPU_INSTANCE_COUNT); in Wkpu_Ip_Init()
531 DevAssert(userConfig != NULL_PTR); in Wkpu_Ip_Init()
618 DevAssert(instance < WKPU_INSTANCE_COUNT); in Wkpu_Ip_DeInit()
701 DevAssert(instance < WKPU_INSTANCE_COUNT); in Wkpu_Ip_SetActivationCondition()
702 DevAssert(hwChannel < WKPU_IP_NUM_OF_CHANNELS); in Wkpu_Ip_SetActivationCondition()
810 DevAssert(instance < WKPU_INSTANCE_COUNT); in Wkpu_Ip_GetInputState()
[all …]
DEmios_Icu_Ip_Irq.c401 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_GetCaptureRegA()
402 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_GetCaptureRegA()
996 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SignalMeasurementHandler()
997 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SignalMeasurementHandler()
998 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED); in Emios_Icu_Ip_SignalMeasurementHandler()
1038 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_IrqHandler()
1039 DevAssert(channel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_IrqHandler()
/hal_nxp-3.5.0/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip.c724 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_AddMACFilterEntry()
725 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]); in Netc_Eth_Ip_AddMACFilterEntry()
754 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_DeleteMACFilterEntry()
755 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]); in Netc_Eth_Ip_DeleteMACFilterEntry()
942 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_Init()
943 DevAssert(config != NULL_PTR); in Netc_Eth_Ip_Init()
1150 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_EnableController()
1151 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR); in Netc_Eth_Ip_EnableController()
1210 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_DisableController()
1211 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR); in Netc_Eth_Ip_DisableController()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Adc/src/
DAdc_Sar_Ip.c1230 DevAssert((ResultsRaw != NULL_PTR) || (ResultsStruct != NULL_PTR)); in Adc_Sar_GetConvResults()
1783 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_IRQHandler()
1976 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_Init()
1977 DevAssert(pConfig != NULL_PTR); in Adc_Sar_Ip_Init()
1981 DevAssert(pConfig->CtuMode != ADC_SAR_IP_CTU_MODE_TRIGGER); in Adc_Sar_Ip_Init()
2190 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_Deinit()
2359 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_ChainConfig()
2360 DevAssert(pChansIdxMask != NULL_PTR); in Adc_Sar_Ip_ChainConfig()
2366 …DevAssert((pChansIdxMask->ChanMaskArr[i] & (~Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][i])) == 0u); in Adc_Sar_Ip_ChainConfig()
2382 DevAssert(FALSE); in Adc_Sar_Ip_ChainConfig()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Icu/src/
DSiul2_Icu_Ip.c191 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_DeInit()
243 DevAssert(userConfig->numChannels <= (uint8)SIUL2_ICU_IP_NUM_OF_CHANNELS); in Siul2_Icu_Ip_Init()
244 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_Init()
340 DevAssert(hwChannel < (uint8)SIUL2_ICU_IP_NUM_OF_CHANNELS); in Siul2_Icu_Ip_SetActivationCondition()
341 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_SetActivationCondition()
377 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_GetInputState()
378 DevAssert(hwChannel < SIUL2_ICU_IP_NUM_OF_CHANNELS); in Siul2_Icu_Ip_GetInputState()
401 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_SetClockMode()
419 DevAssert(instance < SIUL2_ICU_IP_NUM_OF_INSTANCES); in Siul2_Icu_Ip_EnableInterrupt()
420 DevAssert(hwChannel < SIUL2_ICU_IP_NUM_OF_CHANNELS); in Siul2_Icu_Ip_EnableInterrupt()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/EthSwt_NETC/src/
DNetc_EthSwt_Ip.c429 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS); in Netc_EthSwt_Ip_SetPortMode()
430 DevAssert(SwitchPortIdx < NETC_ETHSWT_NUMBER_OF_PORTS); in Netc_EthSwt_Ip_SetPortMode()
477 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS); in Netc_EthSwt_Ip_GetPortMode()
478 DevAssert(SwitchPortIdx < NETC_ETHSWT_NUMBER_OF_PORTS); in Netc_EthSwt_Ip_GetPortMode()
534 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS); in Netc_EthSwt_Ip_GetPortSpeed()
535 DevAssert(SwitchPortIdx < NETC_ETHSWT_NUMBER_OF_PORTS); in Netc_EthSwt_Ip_GetPortSpeed()
604 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS); in Netc_EthSwt_Ip_SetPortSpeed()
605 DevAssert(SwitchPortIdx < NETC_ETHSWT_NUMBER_OF_PORTS); in Netc_EthSwt_Ip_SetPortSpeed()
702 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS); in Netc_EthSwt_Ip_GetDuplexMode()
703 DevAssert(SwitchPortIdx < NETC_ETHSWT_NUMBER_OF_PORTS); in Netc_EthSwt_Ip_GetDuplexMode()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Swt/src/
DSwt_Ip.c434 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_Init()
435 DevAssert(ConfigPtr != NULL_PTR); in Swt_Ip_Init()
491 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_Deinit()
538 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_Service()
596 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_Config()
597 DevAssert(ConfigPtr != NULL_PTR); in Swt_Ip_Config()
646 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_SetTimeout()
701 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_StartTimer()
733 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_StopTimer()
774 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_ClearResetRequest()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c1213 DevAssert((Length%4) == 0u); in Spi_Ip_CheckValidParameters()
1217 DevAssert((Length%2) == 0u); in Spi_Ip_CheckValidParameters()
1342 DevAssert(PhyUnitConfigPtr != NULL_PTR); in Spi_Ip_Init()
1348 DevAssert(State == NULL_PTR); in Spi_Ip_Init()
1390 DevAssert(Instance < SPI_INSTANCE_COUNT); in Spi_Ip_DeInit()
1395 DevAssert(State != NULL_PTR); in Spi_Ip_DeInit()
1440 DevAssert(ExternalDevice != NULL_PTR); in Spi_Ip_SyncTransmit()
1441 DevAssert(0u != Length); in Spi_Ip_SyncTransmit()
1442 DevAssert(0u != TimeOut); in Spi_Ip_SyncTransmit()
1448 DevAssert(State != NULL_PTR); in Spi_Ip_SyncTransmit()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Gpt/src/
DStm_Ip.c504 DevAssert(STM_INSTANCE_COUNT > instance); in Stm_Ip_Init()
505 DevAssert(NULL_PTR != configPtr); in Stm_Ip_Init()
537 DevAssert(NULL_PTR != configPtr); in Stm_Ip_InitChannel()
538 DevAssert(STM_INSTANCE_COUNT > instance); in Stm_Ip_InitChannel()
539 DevAssert(STM_CHANNEL_COUNT > configPtr->hwChannel); in Stm_Ip_InitChannel()
578 DevAssert(STM_INSTANCE_COUNT > instance); in Stm_Ip_Deinit()
619 DevAssert(STM_INSTANCE_COUNT > instance); in Stm_Ip_StartCounting()
620 DevAssert(STM_CHANNEL_COUNT > channel); in Stm_Ip_StartCounting()
650 DevAssert(STM_INSTANCE_COUNT > instance); in Stm_Ip_StartCountingAbsolute()
651 DevAssert(STM_CHANNEL_COUNT > channel); in Stm_Ip_StartCountingAbsolute()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Platform/src/
DMru_Ip.c131 DevAssert(NULL_PTR != HWUnitConfigPtr); in Mru_Ip_Init()
136 DevAssert(NULL_PTR == State); in Mru_Ip_Init()
164 DevAssert(NULL_PTR != TransmitChCfgPtr); in Mru_Ip_Transmit()
165 DevAssert(NULL_PTR != TxBufferPtr); in Mru_Ip_Transmit()
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/include/
DDevassert.h53 #define DevAssert(x) macro
67 static inline void DevAssert(volatile boolean x) in DevAssert() function
DOsIf_Cfg_TypesDef.h37 #define OSIF_DEV_ASSERT(x) DevAssert(x)
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/include/
DDevassert.h53 #define DevAssert(x) macro
67 static inline void DevAssert(volatile boolean x) in DevAssert() function
DOsIf_Cfg_TypesDef.h37 #define OSIF_DEV_ASSERT(x) DevAssert(x)
/hal_nxp-3.5.0/s32/drivers/s32ze/Can_CANEXCEL/include/
DCanEXCEL_Ip_HwAccess.h283 DevAssert(timeSeg != NULL_PTR); in CanXL_SetFDBaudRate()
303 DevAssert(timeSeg != NULL_PTR); in CanXL_SetXLBaudRate()
323 DevAssert(timeSeg != NULL_PTR); in CanXL_SetBaudRate()
/hal_nxp-3.5.0/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c137 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_ConfigTimeStamp()
162 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_SetStopMode()
347 DevAssert(FALSE); in Canexcel_Ip_ConfigRx()
832 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_GetStopMode()
848 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_ConfigRxFifo()
849 DevAssert(filterConfig->noActAddrFilters < CANXL_RXFIFO_ADDRACPTFLTAR_COUNT); in Canexcel_Ip_ConfigRxFifo()
850 DevAssert(filterConfig->noIdFilters < CANXL_RXFIFO_IDACPTFLTAR_COUNT); in Canexcel_Ip_ConfigRxFifo()
851 DevAssert(filterConfig->noSduFilters < CANXL_RXFIFO_SDUACPTFLTAR_COUNT); in Canexcel_Ip_ConfigRxFifo()
852 DevAssert(filterConfig->noVcanFilters < CANXL_RXFIFO_VCANACPTFLTAR_COUNT); in Canexcel_Ip_ConfigRxFifo()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
DPower_Ip_Private.h114 #define POWER_IP_DEV_ASSERT(x) DevAssert(x)
/hal_nxp-3.5.0/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HwAccess.h283 DevAssert(RegisterNumber < ADC_SAR_IP_THRHLR_COUNT); in Adc_Sar_WriteThresholds()
469 DevAssert(FALSE); in Adc_Sar_GetChannelWatchdogAddress()
/hal_nxp-3.5.0/s32/drivers/s32k3/Port/include/
DSiul2_Port_Ip.h169 #define SIUL2_PORT_IP_DEV_ASSERT(par) DevAssert(par)
/hal_nxp-3.5.0/s32/drivers/s32k3/Dio/include/
DSiul2_Dio_Ip.h159 #define SIUL2_DIO_IP_DEV_ASSERT(par) DevAssert(par)
/hal_nxp-3.5.0/s32/drivers/s32ze/Dio/include/
DSiul2_Dio_Ip.h159 #define SIUL2_DIO_IP_DEV_ASSERT(par) DevAssert(par)

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