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Searched refs:DMA0_TRIG5_PIO1_12 (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-3.5.0/dts/nxp/lpc/
DLPC51U68JBD64-pinctrl.h1323 #define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ macro
DLPC54114J256BD64-pinctrl.h1505 #define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ macro
/hal_nxp-3.5.0/dts/nxp/nxp_imx/rt/
DMIMXRT685SFAWBR-pinctrl.h3236 #define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ macro
DMIMXRT595SFAWC-pinctrl.h3782 #define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ macro
DMIMXRT595SFFOC-pinctrl.h3804 #define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ macro
DMIMXRT685SFFOB-pinctrl.h3977 #define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ macro
DMIMXRT685SFVKB-pinctrl.h3977 #define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ macro