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Searched refs:DIVHFCLK (Results 1 – 25 of 29) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/dmic/
Dfsl_dmic.c171 base->CHANNEL[channel].DIVHFCLK = (uint32_t)channel_config->divhfclk; in DMIC_ConfigChannel()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h2211 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
DLPC54114_cm4.h2222 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h2223 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h2563 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h2564 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h2567 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h2971 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h4108 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h3808 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h4033 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h4106 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h4106 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h4106 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h4029 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h4514 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h4173 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h4104 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h4514 …__IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, ar… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h6618 …__IO uint32_t DIVHFCLK; /**< Divider for generating PDM clock from DMIC c… member
DMIMXRT685S_cm33.h12610 …__IO uint32_t DIVHFCLK; /**< Divider for generating PDM clock from DMIC c… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h12610 …__IO uint32_t DIVHFCLK; /**< Divider for generating PDM clock from DMIC c… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h10556 …__IO uint32_t DIVHFCLK; /**< DMIC Clock, array offset: 0x4, array step: 0… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h11472 …__IO uint32_t DIVHFCLK; /**< DMIC Clock, array offset: 0x4, array step: 0… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h10556 …__IO uint32_t DIVHFCLK; /**< DMIC Clock, array offset: 0x4, array step: 0… member

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