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Searched refs:ConfigPtr (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c161 …_CommonStatusType Emios_Mcl_Ip_Init(uint8 Instance, const Emios_Mcl_Ip_ConfigType* const ConfigPtr) in Emios_Mcl_Ip_Init() argument
165 DevAssert(ConfigPtr != NULL_PTR); in Emios_Mcl_Ip_Init()
186 …Base->MCR = eMIOS_MCR_GPRE(ConfigPtr->emiosGlobalConfig->clkDivVal) | eMIOS_MCR_FRZ(((uint32)Confi… in Emios_Mcl_Ip_Init()
187 eMIOS_MCR_GTBE(ConfigPtr->emiosGlobalConfig->enableGlobalTimeBase); in Emios_Mcl_Ip_Init()
190 for (CurrentChannel = 0; CurrentChannel < ConfigPtr->channelsNumber; CurrentChannel++) in Emios_Mcl_Ip_Init()
192 if ((*ConfigPtr->masterBusConfig)[CurrentChannel].allowDebugMode) in Emios_Mcl_Ip_Init()
194 … Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_FREN_MASK; in Emios_Mcl_Ip_Init()
198 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C2 |= eMIOS_C2_UCEXTPRE((*Con… in Emios_Mcl_Ip_Init()
200 switch ((*ConfigPtr->masterBusConfig)[CurrentChannel].masterMode) in Emios_Mcl_Ip_Init()
203 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Swt/src/
DSwt_Ip.c305 const Swt_Ip_ConfigType * const ConfigPtr) in Swt_Ip_RegisterConfig() argument
309 Swt_Ip_ServiceModeType ServiceMode = ConfigPtr->eServiceMode; in Swt_Ip_RegisterConfig()
312 TempCr = (SWT_IP_MAP(ConfigPtr->u8MapEnBitmask) in Swt_Ip_RegisterConfig()
314 | SWT_CR_RIA(ConfigPtr->bEnResetOnInvalidAccess ? 1UL : 0UL) in Swt_Ip_RegisterConfig()
315 | SWT_CR_WND(ConfigPtr->bEnWindow ? 1UL : 0UL) in Swt_Ip_RegisterConfig()
316 | SWT_CR_ITR(ConfigPtr->bEnInterrupt ? 1UL : 0UL) in Swt_Ip_RegisterConfig()
318 | SWT_CR_STP(ConfigPtr->bEnRunInStopMode? 0UL : 1UL) in Swt_Ip_RegisterConfig()
320 | SWT_CR_FRZ(ConfigPtr->bEnRunInDebugMode ? 0UL : 1UL)); in Swt_Ip_RegisterConfig()
330 Base->TO = ConfigPtr->u32TimeoutValue; in Swt_Ip_RegisterConfig()
333 if (ConfigPtr->bEnWindow) in Swt_Ip_RegisterConfig()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DPower_Ip_DCM_GPR.c187 void Power_Ip_DCM_GPR_Config(const Power_Ip_DCM_GPR_ConfigType * ConfigPtr) in Power_Ip_DCM_GPR_Config() argument
189 (void)ConfigPtr; in Power_Ip_DCM_GPR_Config()
192 if (TRUE == ConfigPtr->DcmGprUnderMcuControl) in Power_Ip_DCM_GPR_Config()
195 if (1U == ConfigPtr->BootMode) in Power_Ip_DCM_GPR_Config()
198 IP_DCM_GPR->DCMRWF5 = (ConfigPtr->BootAddress) | (uint32)(ConfigPtr->BootMode); in Power_Ip_DCM_GPR_Config()
209 TempValue |= (ConfigPtr->ConfigRegister); in Power_Ip_DCM_GPR_Config()
DPower_Ip_PMC.c230 void Power_Ip_PMC_PowerInit(const Power_Ip_PMC_ConfigType * ConfigPtr) in Power_Ip_PMC_PowerInit() argument
241 (void)ConfigPtr; in Power_Ip_PMC_PowerInit()
257 ConfigValue |= (ConfigPtr->ConfigRegister & (uint32)PMC_CONFIG_RWBITS_MASK); in Power_Ip_PMC_PowerInit()
261 if (PMC_CONFIG_LAST_MILE_REG_ENABLE == (ConfigPtr->ConfigRegister & PMC_CONFIG_LMEN_MASK)) in Power_Ip_PMC_PowerInit()
263 IP_PMC->CONFIG = (uint32)(ConfigPtr->ConfigRegister & (~(uint32)PMC_CONFIG_LMEN_MASK)); in Power_Ip_PMC_PowerInit()
266 … if(PMC_CONFIG_LM_BASE_CONTROL_ENABLE == (ConfigPtr->ConfigRegister & PMC_CONFIG_LMBCTLEN_MASK)) in Power_Ip_PMC_PowerInit()
298 IP_PMC->CONFIG = ConfigPtr->ConfigRegister; in Power_Ip_PMC_PowerInit()
300 …if (PMC_CONFIG_LAST_MILE_REG_AUTO_ENABLE == (ConfigPtr->ConfigRegister & PMC_CONFIG_LMAUTOEN_MASK)) in Power_Ip_PMC_PowerInit()
328 ConfigValue = ConfigPtr->SMPSRegister; in Power_Ip_PMC_PowerInit()
358 void Power_Ip_PMC_AE_PowerInit(const Power_Ip_PMC_ConfigType * ConfigPtr) in Power_Ip_PMC_AE_PowerInit() argument
[all …]
DPower_Ip_MC_RGM.c345 void Power_Ip_MC_RGM_ResetInit(const Power_Ip_MC_RGM_ConfigType * ConfigPtr) in Power_Ip_MC_RGM_ResetInit() argument
368 Power_Ip_pxMC_RGM->FERD = ConfigPtr->FuncResetOpt; in Power_Ip_MC_RGM_ResetInit()
381 Power_Ip_pxMC_RGM->FRET = ConfigPtr->FesThresholdReset; in Power_Ip_MC_RGM_ResetInit()
391 Power_Ip_pxMC_RGM->DRET = ConfigPtr->DesThresholdReset; in Power_Ip_MC_RGM_ResetInit()
397 Power_Ip_pxMC_RGM->FRENTC = ConfigPtr->ResetEntryTimeout; in Power_Ip_MC_RGM_ResetInit()
754 void Power_Ip_MC_RGM_PerformReset(const Power_Ip_MC_RGM_ConfigType * ConfigPtr) in Power_Ip_MC_RGM_PerformReset() argument
756 switch (ConfigPtr->ResetType) in Power_Ip_MC_RGM_PerformReset()
DPower_Ip_AEC.c171 void Power_Ip_AEC_Reset_Config(const Power_Ip_AEC_ConfigType * ConfigPtr) in Power_Ip_AEC_Reset_Config() argument
177 TmpAe = (uint16)(TmpAe | (uint16)(ConfigPtr->Rstgencfg)); in Power_Ip_AEC_Reset_Config()
/hal_nxp-3.5.0/s32/drivers/s32k3/Port/src/
DSiul2_Port_Ip.c862 const Siul2_Port_Ip_PinSettingsConfig * ConfigPtr = pPort_Setting; in Siul2_Port_Ip_RevertPinConfiguration() local
892 if (ConfigPtr[u32PinIdx].pinPortIdx == u32MscrId) in Siul2_Port_Ip_RevertPinConfiguration()
894 Siul2_Port_Ip_PinInit(&ConfigPtr[u32PinIdx]); in Siul2_Port_Ip_RevertPinConfiguration()
915 const Siul2_Port_Ip_PinSettingsConfig * ConfigPtr = pPort_Setting; in Siul2_Port_Ip_GetPinConfiguration() local
948 if (ConfigPtr[u32PinIdx].pinPortIdx == u32MscrId) in Siul2_Port_Ip_GetPinConfiguration()
950 config->base = ConfigPtr[u32PinIdx].base; in Siul2_Port_Ip_GetPinConfiguration()
951 config->pinPortIdx = ConfigPtr[u32PinIdx].pinPortIdx; in Siul2_Port_Ip_GetPinConfiguration()
952 config->initValue = ConfigPtr[u32PinIdx].initValue; in Siul2_Port_Ip_GetPinConfiguration()
956 … config->inputMuxReg[inputMuxIterator] = ConfigPtr[u32PinIdx].inputMuxReg[inputMuxIterator]; in Siul2_Port_Ip_GetPinConfiguration()
957 … config->inputMux[inputMuxIterator] = ConfigPtr[u32PinIdx].inputMux[inputMuxIterator]; in Siul2_Port_Ip_GetPinConfiguration()
/hal_nxp-3.5.0/s32/drivers/s32ze/Port/src/
DSiul2_Port_Ip.c1163 const Siul2_Port_Ip_PinSettingsConfig * ConfigPtr = pPort_Setting; in Siul2_Port_Ip_RevertPinConfiguration() local
1221 if (ConfigPtr[u32PinIdx].pinPortIdx == u32MscrId) in Siul2_Port_Ip_RevertPinConfiguration()
1223 Siul2_Port_Ip_PinInit(&ConfigPtr[u32PinIdx]); in Siul2_Port_Ip_RevertPinConfiguration()
1244 const Siul2_Port_Ip_PinSettingsConfig * ConfigPtr = pPort_Setting; in Siul2_Port_Ip_GetPinConfiguration() local
1305 if (ConfigPtr[u32PinIdx].pinPortIdx == u32MscrId) in Siul2_Port_Ip_GetPinConfiguration()
1307 config->base = ConfigPtr[u32PinIdx].base; in Siul2_Port_Ip_GetPinConfiguration()
1308 config->pinPortIdx = ConfigPtr[u32PinIdx].pinPortIdx; in Siul2_Port_Ip_GetPinConfiguration()
1309 config->initValue = ConfigPtr[u32PinIdx].initValue; in Siul2_Port_Ip_GetPinConfiguration()
1313 … config->inputMuxReg[inputMuxIterator] = ConfigPtr[u32PinIdx].inputMuxReg[inputMuxIterator]; in Siul2_Port_Ip_GetPinConfiguration()
1314 … config->inputMux[inputMuxIterator] = ConfigPtr[u32PinIdx].inputMux[inputMuxIterator]; in Siul2_Port_Ip_GetPinConfiguration()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
DPower_Ip_PMC.h126 void Power_Ip_PMC_PowerInit(const Power_Ip_PMC_ConfigType * ConfigPtr);
129 void Power_Ip_PMC_AE_PowerInit(const Power_Ip_PMC_ConfigType * ConfigPtr);
DPower_Ip_MC_RGM.h202 void Power_Ip_MC_RGM_ResetInit(const Power_Ip_MC_RGM_ConfigType * ConfigPtr);
220 void Power_Ip_MC_RGM_PerformReset(const Power_Ip_MC_RGM_ConfigType * ConfigPtr);
DPower_Ip_TrustedFunctions.h198 extern void Power_Ip_MC_RGM_ResetInit(const Power_Ip_MC_RGM_ConfigType * ConfigPtr);
210 extern void Power_Ip_MC_RGM_PerformReset(const Power_Ip_MC_RGM_ConfigType * ConfigPtr);
DPower_Ip_DCM_GPR.h126 void Power_Ip_DCM_GPR_Config(const Power_Ip_DCM_GPR_ConfigType * ConfigPtr);
DPower_Ip_AEC.h140 void Power_Ip_AEC_Reset_Config(const Power_Ip_AEC_ConfigType * ConfigPtr);
/hal_nxp-3.5.0/s32/drivers/s32ze/Swt/include/
DSwt_Ip.h130 const Swt_Ip_ConfigType * const ConfigPtr);
167 const Swt_Ip_ConfigType * const ConfigPtr);
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/include/
DEmios_Mcl_Ip.h186 …CommonStatusType Emios_Mcl_Ip_Init(uint8 Instance, const Emios_Mcl_Ip_ConfigType *const ConfigPtr);