Clock_Ip_apxCgm (reference) in projects: hal_nxp-3.5.0

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Searched refs:Clock_Ip_apxCgm (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_Selector.c	160 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC \|= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswSwip() 161 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssClkswSwip() 198 …if (SelectorValue != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & SelectorMask) >> SelectorSh… in Clock_Ip_SetCgmXCscCssClkswSwip() 205 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip() 209 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip() 213 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip() 221 …while((CLOCK_IP_MC_CGM_MUX_CSS_CLK_SW_NOT_REQUESTED == (Clock_Ip_apxCgm[Instance][SelectorIndex]->… in Clock_Ip_SetCgmXCscCssClkswSwip() 231 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip() 236 …if (CLOCK_IP_MC_CGM_MUX_CSS_SWTRG_SUCCEEDED != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & M… in Clock_Ip_SetCgmXCscCssClkswSwip() 292 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC \|= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswRampupRampdownSwip() [all …]
D	Clock_Ip_DividerTrigger.c	138 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() 142 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() 172 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG = MC_CGM_MUX_DIV_TRIG_TRIGGER(CLOCK_IP_TRIG… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat() 178 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
D	Clock_Ip_Divider.c	163 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 166 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 188 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 199 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] \|= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 203 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
D	Clock_Ip_Data.c	`3312 Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_MUXS_CO… variable`
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Selector.c	157 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC \|= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswSwip() 158 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssClkswSwip() 179 …if (SelectorValue != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & SelectorMask) >> SelectorSh… in Clock_Ip_SetCgmXCscCssClkswSwip() 186 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip() 190 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip() 194 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip() 202 …while((CLOCK_IP_MC_CGM_MUX_CSS_CLK_SW_NOT_REQUESTED == (Clock_Ip_apxCgm[Instance][SelectorIndex]->… in Clock_Ip_SetCgmXCscCssClkswSwip() 212 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip() 217 …if (CLOCK_IP_MC_CGM_MUX_CSS_SWTRG_SUCCEEDED != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & M… in Clock_Ip_SetCgmXCscCssClkswSwip() 259 …Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC \|= (MC_CGM_MUX_CSC_CG_MASK \| MC_CGM_MUX_CSC_FCG_MASK… in Clock_Ip_ResetCgmXCscCssCsGrip() [all …]
D	Clock_Ip_Divider.c	153 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 156 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 178 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 189 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] \|= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 193 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() 224 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() 227 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() 231 …if ((Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL & MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_M… in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() 237 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() 249 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] \|= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() [all …]
D	Clock_Ip_DividerTrigger.c	133 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() 137 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() 155 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG = MC_CGM_MUX_DIV_TRIG_TRIGGER(CLOCK_IP_TRIG… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat() 161 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
D	Clock_Ip_Data.c	`2613 Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_MUXS_CO… variable`
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/include/
D	Clock_Ip_Specific.h	`304 extern Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_…`
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
D	Clock_Ip_Specific.h	`455 extern Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM…`

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