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Searched refs:CfgIndex (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Platform/src/
DMru_Ip.c128 uint8 CfgIndex = 0u; in Mru_Ip_Init() local
142 for(CfgIndex = 0u; CfgIndex < HWUnitConfigPtr->NumChannel; CfgIndex++) in Mru_Ip_Init()
144 if(NULL_PTR != HWUnitConfigPtr->ChannelCfg[CfgIndex].MBLinkReceiveChCfg) in Mru_Ip_Init()
147 *HWUnitConfigPtr->ChannelCfg[CfgIndex].ChCFG0Add = MRU_IP_CH_CFG0_CHE_MASK; in Mru_Ip_Init()
149 … *HWUnitConfigPtr->ChannelCfg[CfgIndex].ChCFG1Add = HWUnitConfigPtr->ChannelCfg[CfgIndex].ChCFG1; in Mru_Ip_Init()
151 …*HWUnitConfigPtr->ChannelCfg[CfgIndex].ChCFG0Add = HWUnitConfigPtr->ChannelCfg[CfgIndex].ChCFG0 | … in Mru_Ip_Init()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_ProgFreqSwitch.c138 uint32 CfgIndex
167 uint32 CfgIndex in Clock_Ip_CgmXPcfsSdurDivcDiveDivs() argument
198 …if (HashPfs[CfgIndex] != ((((uint32)Config->ClockSourceFrequency) ^ ((uint32)Config->MaxAllowableI… in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
200 …HashPfs[CfgIndex] = ((((uint32)Config->ClockSourceFrequency) ^ ((uint32)Config->MaxAllowableIDDcha… in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
284 (void)CfgIndex; in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_ProgFreqSwitch.c135 …tic void Clock_Ip_CgmXPcfsSdurDivcDiveDivs(Clock_Ip_PcfsConfigType const *Config, uint32 CfgIndex);
160 …atic void Clock_Ip_CgmXPcfsSdurDivcDiveDivs(Clock_Ip_PcfsConfigType const *Config, uint32 CfgIndex) in Clock_Ip_CgmXPcfsSdurDivcDiveDivs() argument
185 …if (HashPfs[CfgIndex] != ((((uint32)Config->ClockSourceFrequency) ^ ((uint32)Config->MaxAllowableI… in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()
187 …HashPfs[CfgIndex] = ((((uint32)Config->ClockSourceFrequency) ^ ((uint32)Config->MaxAllowableIDDcha… in Clock_Ip_CgmXPcfsSdurDivcDiveDivs()