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Searched refs:CTIMER_MCR_MR0I_MASK (Results 1 – 25 of 56) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/ctimer/
Dfsl_ctimer.c216 …((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) in CTIMER_SetupPwm()
222 …reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U)… in CTIMER_SetupPwm()
306 …)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) in CTIMER_SetupPwmPeriod()
312 …reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U)… in CTIMER_SetupPwmPeriod()
392 …)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) in CTIMER_SetupMatch()
Dfsl_ctimer.h89 kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */
382 …base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_M… in CTIMER_EnableInterrupts()
407 …base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER… in CTIMER_DisableInterrupts()
436 …base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_… in CTIMER_GetEnabledInterrupts()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC802/
DLPC802.h1282 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1286 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC804/
DLPC804.h1664 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1668 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC844/
DLPC844.h1366 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1370 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC845/
DLPC845.h1772 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1776 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h1398 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1402 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h1354 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1358 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
DLPC54114_cm4.h1365 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1369 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h1366 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1370 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h1583 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1587 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h1584 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1588 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h1587 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1591 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h1991 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
1995 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h3128 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3132 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h2847 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
2850 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h3053 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3057 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h3126 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3130 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h3126 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3130 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h3126 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3130 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h6428 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
6432 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h3049 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3053 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h3534 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3538 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h3212 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3215 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h3124 #define CTIMER_MCR_MR0I_MASK (0x1U) macro
3128 … (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)

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