1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_AES_ACCEL.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_AES_ACCEL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_AES_ACCEL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_AES_ACCEL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- AES_ACCEL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup AES_ACCEL_Peripheral_Access_Layer AES_ACCEL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** AES_ACCEL - Size of Registers Arrays */ 72 #define AES_ACCEL_ACCEL_COUNT 8u 73 74 /** AES_ACCEL - Register Layout Typedef */ 75 typedef struct { 76 struct { /* offset: 0x0, array step: 0x1000 */ 77 __IO uint32_t LEN; /**< LEN register, array offset: 0x0, array step: 0x1000 */ 78 __IO uint32_t AILEN; /**< AAD/IV length register, array offset: 0x4, array step: 0x1000 */ 79 __IO uint32_t CRYPT; /**< CRYPT register, array offset: 0x8, array step: 0x1000 */ 80 __I uint32_t OWNSTAT; /**< OWN_Status register, array offset: 0xC, array step: 0x1000 */ 81 __IO uint32_t TLVAL; /**< Timer Load Value Register, array offset: 0x10, array step: 0x1000 */ 82 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x14, array step: 0x1000 */ 83 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x18, array step: 0x1000 */ 84 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x1C, array step: 0x1000 */ 85 __IO uint32_t FEEDINTMAP; /**< FEEDINTMAP register, array offset: 0x20, array step: 0x1000 */ 86 __IO uint32_t RESULTINTMAP; /**< RESULTINTMAP register, array offset: 0x24, array step: 0x1000 */ 87 uint8_t RESERVED_0[4056]; 88 } ACCEL[AES_ACCEL_ACCEL_COUNT]; 89 } AES_ACCEL_Type, *AES_ACCEL_MemMapPtr; 90 91 /** Number of instances of the AES_ACCEL module. */ 92 #define AES_ACCEL_INSTANCE_COUNT (1u) 93 94 /* AES_ACCEL - Peripheral instance base addresses */ 95 /** Peripheral AES__AES_ACCEL base address */ 96 #define IP_AES__AES_ACCEL_BASE (0x472A0000u) 97 /** Peripheral AES__AES_ACCEL base pointer */ 98 #define IP_AES__AES_ACCEL ((AES_ACCEL_Type *)IP_AES__AES_ACCEL_BASE) 99 /** Array initializer of AES_ACCEL peripheral base addresses */ 100 #define IP_AES_ACCEL_BASE_ADDRS { IP_AES__AES_ACCEL_BASE } 101 /** Array initializer of AES_ACCEL peripheral base pointers */ 102 #define IP_AES_ACCEL_BASE_PTRS { IP_AES__AES_ACCEL } 103 104 /* ---------------------------------------------------------------------------- 105 -- AES_ACCEL Register Masks 106 ---------------------------------------------------------------------------- */ 107 108 /*! 109 * @addtogroup AES_ACCEL_Register_Masks AES_ACCEL Register Masks 110 * @{ 111 */ 112 113 /*! @name LEN - LEN register */ 114 /*! @{ */ 115 116 #define AES_ACCEL_LEN_TLEN_MASK (0x7FFFFU) 117 #define AES_ACCEL_LEN_TLEN_SHIFT (0U) 118 #define AES_ACCEL_LEN_TLEN_WIDTH (19U) 119 #define AES_ACCEL_LEN_TLEN(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_LEN_TLEN_SHIFT)) & AES_ACCEL_LEN_TLEN_MASK) 120 /*! @} */ 121 122 /*! @name AILEN - AAD/IV length register */ 123 /*! @{ */ 124 125 #define AES_ACCEL_AILEN_AAD_MASK (0x7FFFFU) 126 #define AES_ACCEL_AILEN_AAD_SHIFT (0U) 127 #define AES_ACCEL_AILEN_AAD_WIDTH (19U) 128 #define AES_ACCEL_AILEN_AAD(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_AILEN_AAD_SHIFT)) & AES_ACCEL_AILEN_AAD_MASK) 129 130 #define AES_ACCEL_AILEN_IVLEN_MASK (0x7F000000U) 131 #define AES_ACCEL_AILEN_IVLEN_SHIFT (24U) 132 #define AES_ACCEL_AILEN_IVLEN_WIDTH (7U) 133 #define AES_ACCEL_AILEN_IVLEN(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_AILEN_IVLEN_SHIFT)) & AES_ACCEL_AILEN_IVLEN_MASK) 134 /*! @} */ 135 136 /*! @name CRYPT - CRYPT register */ 137 /*! @{ */ 138 139 #define AES_ACCEL_CRYPT_MASK_MASK (0x7FU) 140 #define AES_ACCEL_CRYPT_MASK_SHIFT (0U) 141 #define AES_ACCEL_CRYPT_MASK_WIDTH (7U) 142 #define AES_ACCEL_CRYPT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_CRYPT_MASK_SHIFT)) & AES_ACCEL_CRYPT_MASK_MASK) 143 144 #define AES_ACCEL_CRYPT_CMODE_MASK (0xF00U) 145 #define AES_ACCEL_CRYPT_CMODE_SHIFT (8U) 146 #define AES_ACCEL_CRYPT_CMODE_WIDTH (4U) 147 #define AES_ACCEL_CRYPT_CMODE(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_CRYPT_CMODE_SHIFT)) & AES_ACCEL_CRYPT_CMODE_MASK) 148 149 #define AES_ACCEL_CRYPT_CO_MASK (0x3000U) 150 #define AES_ACCEL_CRYPT_CO_SHIFT (12U) 151 #define AES_ACCEL_CRYPT_CO_WIDTH (2U) 152 #define AES_ACCEL_CRYPT_CO(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_CRYPT_CO_SHIFT)) & AES_ACCEL_CRYPT_CO_MASK) 153 154 #define AES_ACCEL_CRYPT_KSLOT_MASK (0xFF0000U) 155 #define AES_ACCEL_CRYPT_KSLOT_SHIFT (16U) 156 #define AES_ACCEL_CRYPT_KSLOT_WIDTH (8U) 157 #define AES_ACCEL_CRYPT_KSLOT(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_CRYPT_KSLOT_SHIFT)) & AES_ACCEL_CRYPT_KSLOT_MASK) 158 /*! @} */ 159 160 /*! @name OWNSTAT - OWN_Status register */ 161 /*! @{ */ 162 163 #define AES_ACCEL_OWNSTAT_DID_MASK (0xFU) 164 #define AES_ACCEL_OWNSTAT_DID_SHIFT (0U) 165 #define AES_ACCEL_OWNSTAT_DID_WIDTH (4U) 166 #define AES_ACCEL_OWNSTAT_DID(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_OWNSTAT_DID_SHIFT)) & AES_ACCEL_OWNSTAT_DID_MASK) 167 168 #define AES_ACCEL_OWNSTAT_NS_MASK (0x40U) 169 #define AES_ACCEL_OWNSTAT_NS_SHIFT (6U) 170 #define AES_ACCEL_OWNSTAT_NS_WIDTH (1U) 171 #define AES_ACCEL_OWNSTAT_NS(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_OWNSTAT_NS_SHIFT)) & AES_ACCEL_OWNSTAT_NS_MASK) 172 173 #define AES_ACCEL_OWNSTAT_PRIV_MASK (0x80U) 174 #define AES_ACCEL_OWNSTAT_PRIV_SHIFT (7U) 175 #define AES_ACCEL_OWNSTAT_PRIV_WIDTH (1U) 176 #define AES_ACCEL_OWNSTAT_PRIV(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_OWNSTAT_PRIV_SHIFT)) & AES_ACCEL_OWNSTAT_PRIV_MASK) 177 /*! @} */ 178 179 /*! @name TLVAL - Timer Load Value Register */ 180 /*! @{ */ 181 182 #define AES_ACCEL_TLVAL_TSV_MASK (0xFFFFU) 183 #define AES_ACCEL_TLVAL_TSV_SHIFT (0U) 184 #define AES_ACCEL_TLVAL_TSV_WIDTH (16U) 185 #define AES_ACCEL_TLVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_TLVAL_TSV_SHIFT)) & AES_ACCEL_TLVAL_TSV_MASK) 186 /*! @} */ 187 188 /*! @name CVAL - Current Timer Value Register */ 189 /*! @{ */ 190 191 #define AES_ACCEL_CVAL_TVL_MASK (0xFFFFU) 192 #define AES_ACCEL_CVAL_TVL_SHIFT (0U) 193 #define AES_ACCEL_CVAL_TVL_WIDTH (16U) 194 #define AES_ACCEL_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_CVAL_TVL_SHIFT)) & AES_ACCEL_CVAL_TVL_MASK) 195 /*! @} */ 196 197 /*! @name TCTRL - Timer Control Register */ 198 /*! @{ */ 199 200 #define AES_ACCEL_TCTRL_TEN_MASK (0x1U) 201 #define AES_ACCEL_TCTRL_TEN_SHIFT (0U) 202 #define AES_ACCEL_TCTRL_TEN_WIDTH (1U) 203 #define AES_ACCEL_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_TCTRL_TEN_SHIFT)) & AES_ACCEL_TCTRL_TEN_MASK) 204 205 #define AES_ACCEL_TCTRL_TIE_MASK (0x2U) 206 #define AES_ACCEL_TCTRL_TIE_SHIFT (1U) 207 #define AES_ACCEL_TCTRL_TIE_WIDTH (1U) 208 #define AES_ACCEL_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_TCTRL_TIE_SHIFT)) & AES_ACCEL_TCTRL_TIE_MASK) 209 210 #define AES_ACCEL_TCTRL_FRZ_MASK (0x4U) 211 #define AES_ACCEL_TCTRL_FRZ_SHIFT (2U) 212 #define AES_ACCEL_TCTRL_FRZ_WIDTH (1U) 213 #define AES_ACCEL_TCTRL_FRZ(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_TCTRL_FRZ_SHIFT)) & AES_ACCEL_TCTRL_FRZ_MASK) 214 /*! @} */ 215 216 /*! @name TFLG - Timer Flag Register */ 217 /*! @{ */ 218 219 #define AES_ACCEL_TFLG_TIF_MASK (0x1U) 220 #define AES_ACCEL_TFLG_TIF_SHIFT (0U) 221 #define AES_ACCEL_TFLG_TIF_WIDTH (1U) 222 #define AES_ACCEL_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_TFLG_TIF_SHIFT)) & AES_ACCEL_TFLG_TIF_MASK) 223 /*! @} */ 224 225 /*! @name FEEDINTMAP - FEEDINTMAP register */ 226 /*! @{ */ 227 228 #define AES_ACCEL_FEEDINTMAP_FIEN0_MASK (0x1U) 229 #define AES_ACCEL_FEEDINTMAP_FIEN0_SHIFT (0U) 230 #define AES_ACCEL_FEEDINTMAP_FIEN0_WIDTH (1U) 231 #define AES_ACCEL_FEEDINTMAP_FIEN0(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN0_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN0_MASK) 232 233 #define AES_ACCEL_FEEDINTMAP_FIEN1_MASK (0x2U) 234 #define AES_ACCEL_FEEDINTMAP_FIEN1_SHIFT (1U) 235 #define AES_ACCEL_FEEDINTMAP_FIEN1_WIDTH (1U) 236 #define AES_ACCEL_FEEDINTMAP_FIEN1(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN1_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN1_MASK) 237 238 #define AES_ACCEL_FEEDINTMAP_FIEN2_MASK (0x4U) 239 #define AES_ACCEL_FEEDINTMAP_FIEN2_SHIFT (2U) 240 #define AES_ACCEL_FEEDINTMAP_FIEN2_WIDTH (1U) 241 #define AES_ACCEL_FEEDINTMAP_FIEN2(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN2_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN2_MASK) 242 243 #define AES_ACCEL_FEEDINTMAP_FIEN3_MASK (0x8U) 244 #define AES_ACCEL_FEEDINTMAP_FIEN3_SHIFT (3U) 245 #define AES_ACCEL_FEEDINTMAP_FIEN3_WIDTH (1U) 246 #define AES_ACCEL_FEEDINTMAP_FIEN3(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN3_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN3_MASK) 247 248 #define AES_ACCEL_FEEDINTMAP_FIEN4_MASK (0x10U) 249 #define AES_ACCEL_FEEDINTMAP_FIEN4_SHIFT (4U) 250 #define AES_ACCEL_FEEDINTMAP_FIEN4_WIDTH (1U) 251 #define AES_ACCEL_FEEDINTMAP_FIEN4(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN4_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN4_MASK) 252 253 #define AES_ACCEL_FEEDINTMAP_FIEN5_MASK (0x20U) 254 #define AES_ACCEL_FEEDINTMAP_FIEN5_SHIFT (5U) 255 #define AES_ACCEL_FEEDINTMAP_FIEN5_WIDTH (1U) 256 #define AES_ACCEL_FEEDINTMAP_FIEN5(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN5_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN5_MASK) 257 258 #define AES_ACCEL_FEEDINTMAP_FIEN6_MASK (0x40U) 259 #define AES_ACCEL_FEEDINTMAP_FIEN6_SHIFT (6U) 260 #define AES_ACCEL_FEEDINTMAP_FIEN6_WIDTH (1U) 261 #define AES_ACCEL_FEEDINTMAP_FIEN6(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN6_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN6_MASK) 262 263 #define AES_ACCEL_FEEDINTMAP_FIEN7_MASK (0x80U) 264 #define AES_ACCEL_FEEDINTMAP_FIEN7_SHIFT (7U) 265 #define AES_ACCEL_FEEDINTMAP_FIEN7_WIDTH (1U) 266 #define AES_ACCEL_FEEDINTMAP_FIEN7(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN7_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN7_MASK) 267 268 #define AES_ACCEL_FEEDINTMAP_FIEN8_MASK (0x100U) 269 #define AES_ACCEL_FEEDINTMAP_FIEN8_SHIFT (8U) 270 #define AES_ACCEL_FEEDINTMAP_FIEN8_WIDTH (1U) 271 #define AES_ACCEL_FEEDINTMAP_FIEN8(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN8_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN8_MASK) 272 273 #define AES_ACCEL_FEEDINTMAP_FIEN9_MASK (0x200U) 274 #define AES_ACCEL_FEEDINTMAP_FIEN9_SHIFT (9U) 275 #define AES_ACCEL_FEEDINTMAP_FIEN9_WIDTH (1U) 276 #define AES_ACCEL_FEEDINTMAP_FIEN9(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN9_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN9_MASK) 277 278 #define AES_ACCEL_FEEDINTMAP_FIEN10_MASK (0x400U) 279 #define AES_ACCEL_FEEDINTMAP_FIEN10_SHIFT (10U) 280 #define AES_ACCEL_FEEDINTMAP_FIEN10_WIDTH (1U) 281 #define AES_ACCEL_FEEDINTMAP_FIEN10(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN10_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN10_MASK) 282 283 #define AES_ACCEL_FEEDINTMAP_FIEN11_MASK (0x800U) 284 #define AES_ACCEL_FEEDINTMAP_FIEN11_SHIFT (11U) 285 #define AES_ACCEL_FEEDINTMAP_FIEN11_WIDTH (1U) 286 #define AES_ACCEL_FEEDINTMAP_FIEN11(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN11_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN11_MASK) 287 288 #define AES_ACCEL_FEEDINTMAP_FIEN12_MASK (0x1000U) 289 #define AES_ACCEL_FEEDINTMAP_FIEN12_SHIFT (12U) 290 #define AES_ACCEL_FEEDINTMAP_FIEN12_WIDTH (1U) 291 #define AES_ACCEL_FEEDINTMAP_FIEN12(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN12_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN12_MASK) 292 293 #define AES_ACCEL_FEEDINTMAP_FIEN13_MASK (0x2000U) 294 #define AES_ACCEL_FEEDINTMAP_FIEN13_SHIFT (13U) 295 #define AES_ACCEL_FEEDINTMAP_FIEN13_WIDTH (1U) 296 #define AES_ACCEL_FEEDINTMAP_FIEN13(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN13_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN13_MASK) 297 298 #define AES_ACCEL_FEEDINTMAP_FIEN14_MASK (0x4000U) 299 #define AES_ACCEL_FEEDINTMAP_FIEN14_SHIFT (14U) 300 #define AES_ACCEL_FEEDINTMAP_FIEN14_WIDTH (1U) 301 #define AES_ACCEL_FEEDINTMAP_FIEN14(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN14_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN14_MASK) 302 303 #define AES_ACCEL_FEEDINTMAP_FIEN15_MASK (0x8000U) 304 #define AES_ACCEL_FEEDINTMAP_FIEN15_SHIFT (15U) 305 #define AES_ACCEL_FEEDINTMAP_FIEN15_WIDTH (1U) 306 #define AES_ACCEL_FEEDINTMAP_FIEN15(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN15_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN15_MASK) 307 308 #define AES_ACCEL_FEEDINTMAP_FIEN16_MASK (0x10000U) 309 #define AES_ACCEL_FEEDINTMAP_FIEN16_SHIFT (16U) 310 #define AES_ACCEL_FEEDINTMAP_FIEN16_WIDTH (1U) 311 #define AES_ACCEL_FEEDINTMAP_FIEN16(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN16_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN16_MASK) 312 313 #define AES_ACCEL_FEEDINTMAP_FIEN17_MASK (0x20000U) 314 #define AES_ACCEL_FEEDINTMAP_FIEN17_SHIFT (17U) 315 #define AES_ACCEL_FEEDINTMAP_FIEN17_WIDTH (1U) 316 #define AES_ACCEL_FEEDINTMAP_FIEN17(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN17_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN17_MASK) 317 318 #define AES_ACCEL_FEEDINTMAP_FIEN18_MASK (0x40000U) 319 #define AES_ACCEL_FEEDINTMAP_FIEN18_SHIFT (18U) 320 #define AES_ACCEL_FEEDINTMAP_FIEN18_WIDTH (1U) 321 #define AES_ACCEL_FEEDINTMAP_FIEN18(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN18_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN18_MASK) 322 323 #define AES_ACCEL_FEEDINTMAP_FIEN19_MASK (0x80000U) 324 #define AES_ACCEL_FEEDINTMAP_FIEN19_SHIFT (19U) 325 #define AES_ACCEL_FEEDINTMAP_FIEN19_WIDTH (1U) 326 #define AES_ACCEL_FEEDINTMAP_FIEN19(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN19_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN19_MASK) 327 328 #define AES_ACCEL_FEEDINTMAP_FIEN20_MASK (0x100000U) 329 #define AES_ACCEL_FEEDINTMAP_FIEN20_SHIFT (20U) 330 #define AES_ACCEL_FEEDINTMAP_FIEN20_WIDTH (1U) 331 #define AES_ACCEL_FEEDINTMAP_FIEN20(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN20_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN20_MASK) 332 333 #define AES_ACCEL_FEEDINTMAP_FIEN21_MASK (0x200000U) 334 #define AES_ACCEL_FEEDINTMAP_FIEN21_SHIFT (21U) 335 #define AES_ACCEL_FEEDINTMAP_FIEN21_WIDTH (1U) 336 #define AES_ACCEL_FEEDINTMAP_FIEN21(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN21_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN21_MASK) 337 338 #define AES_ACCEL_FEEDINTMAP_FIEN22_MASK (0x400000U) 339 #define AES_ACCEL_FEEDINTMAP_FIEN22_SHIFT (22U) 340 #define AES_ACCEL_FEEDINTMAP_FIEN22_WIDTH (1U) 341 #define AES_ACCEL_FEEDINTMAP_FIEN22(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN22_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN22_MASK) 342 343 #define AES_ACCEL_FEEDINTMAP_FIEN23_MASK (0x800000U) 344 #define AES_ACCEL_FEEDINTMAP_FIEN23_SHIFT (23U) 345 #define AES_ACCEL_FEEDINTMAP_FIEN23_WIDTH (1U) 346 #define AES_ACCEL_FEEDINTMAP_FIEN23(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_FEEDINTMAP_FIEN23_SHIFT)) & AES_ACCEL_FEEDINTMAP_FIEN23_MASK) 347 /*! @} */ 348 349 /*! @name RESULTINTMAP - RESULTINTMAP register */ 350 /*! @{ */ 351 352 #define AES_ACCEL_RESULTINTMAP_RIEN0_MASK (0x1U) 353 #define AES_ACCEL_RESULTINTMAP_RIEN0_SHIFT (0U) 354 #define AES_ACCEL_RESULTINTMAP_RIEN0_WIDTH (1U) 355 #define AES_ACCEL_RESULTINTMAP_RIEN0(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN0_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN0_MASK) 356 357 #define AES_ACCEL_RESULTINTMAP_RIEN1_MASK (0x2U) 358 #define AES_ACCEL_RESULTINTMAP_RIEN1_SHIFT (1U) 359 #define AES_ACCEL_RESULTINTMAP_RIEN1_WIDTH (1U) 360 #define AES_ACCEL_RESULTINTMAP_RIEN1(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN1_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN1_MASK) 361 362 #define AES_ACCEL_RESULTINTMAP_RIEN2_MASK (0x4U) 363 #define AES_ACCEL_RESULTINTMAP_RIEN2_SHIFT (2U) 364 #define AES_ACCEL_RESULTINTMAP_RIEN2_WIDTH (1U) 365 #define AES_ACCEL_RESULTINTMAP_RIEN2(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN2_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN2_MASK) 366 367 #define AES_ACCEL_RESULTINTMAP_RIEN3_MASK (0x8U) 368 #define AES_ACCEL_RESULTINTMAP_RIEN3_SHIFT (3U) 369 #define AES_ACCEL_RESULTINTMAP_RIEN3_WIDTH (1U) 370 #define AES_ACCEL_RESULTINTMAP_RIEN3(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN3_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN3_MASK) 371 372 #define AES_ACCEL_RESULTINTMAP_RIEN4_MASK (0x10U) 373 #define AES_ACCEL_RESULTINTMAP_RIEN4_SHIFT (4U) 374 #define AES_ACCEL_RESULTINTMAP_RIEN4_WIDTH (1U) 375 #define AES_ACCEL_RESULTINTMAP_RIEN4(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN4_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN4_MASK) 376 377 #define AES_ACCEL_RESULTINTMAP_RIEN5_MASK (0x20U) 378 #define AES_ACCEL_RESULTINTMAP_RIEN5_SHIFT (5U) 379 #define AES_ACCEL_RESULTINTMAP_RIEN5_WIDTH (1U) 380 #define AES_ACCEL_RESULTINTMAP_RIEN5(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN5_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN5_MASK) 381 382 #define AES_ACCEL_RESULTINTMAP_RIEN6_MASK (0x40U) 383 #define AES_ACCEL_RESULTINTMAP_RIEN6_SHIFT (6U) 384 #define AES_ACCEL_RESULTINTMAP_RIEN6_WIDTH (1U) 385 #define AES_ACCEL_RESULTINTMAP_RIEN6(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN6_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN6_MASK) 386 387 #define AES_ACCEL_RESULTINTMAP_RIEN7_MASK (0x80U) 388 #define AES_ACCEL_RESULTINTMAP_RIEN7_SHIFT (7U) 389 #define AES_ACCEL_RESULTINTMAP_RIEN7_WIDTH (1U) 390 #define AES_ACCEL_RESULTINTMAP_RIEN7(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN7_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN7_MASK) 391 392 #define AES_ACCEL_RESULTINTMAP_RIEN8_MASK (0x100U) 393 #define AES_ACCEL_RESULTINTMAP_RIEN8_SHIFT (8U) 394 #define AES_ACCEL_RESULTINTMAP_RIEN8_WIDTH (1U) 395 #define AES_ACCEL_RESULTINTMAP_RIEN8(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN8_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN8_MASK) 396 397 #define AES_ACCEL_RESULTINTMAP_RIEN9_MASK (0x200U) 398 #define AES_ACCEL_RESULTINTMAP_RIEN9_SHIFT (9U) 399 #define AES_ACCEL_RESULTINTMAP_RIEN9_WIDTH (1U) 400 #define AES_ACCEL_RESULTINTMAP_RIEN9(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN9_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN9_MASK) 401 402 #define AES_ACCEL_RESULTINTMAP_RIEN10_MASK (0x400U) 403 #define AES_ACCEL_RESULTINTMAP_RIEN10_SHIFT (10U) 404 #define AES_ACCEL_RESULTINTMAP_RIEN10_WIDTH (1U) 405 #define AES_ACCEL_RESULTINTMAP_RIEN10(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN10_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN10_MASK) 406 407 #define AES_ACCEL_RESULTINTMAP_RIEN11_MASK (0x800U) 408 #define AES_ACCEL_RESULTINTMAP_RIEN11_SHIFT (11U) 409 #define AES_ACCEL_RESULTINTMAP_RIEN11_WIDTH (1U) 410 #define AES_ACCEL_RESULTINTMAP_RIEN11(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN11_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN11_MASK) 411 412 #define AES_ACCEL_RESULTINTMAP_RIEN12_MASK (0x1000U) 413 #define AES_ACCEL_RESULTINTMAP_RIEN12_SHIFT (12U) 414 #define AES_ACCEL_RESULTINTMAP_RIEN12_WIDTH (1U) 415 #define AES_ACCEL_RESULTINTMAP_RIEN12(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN12_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN12_MASK) 416 417 #define AES_ACCEL_RESULTINTMAP_RIEN13_MASK (0x2000U) 418 #define AES_ACCEL_RESULTINTMAP_RIEN13_SHIFT (13U) 419 #define AES_ACCEL_RESULTINTMAP_RIEN13_WIDTH (1U) 420 #define AES_ACCEL_RESULTINTMAP_RIEN13(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN13_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN13_MASK) 421 422 #define AES_ACCEL_RESULTINTMAP_RIEN14_MASK (0x4000U) 423 #define AES_ACCEL_RESULTINTMAP_RIEN14_SHIFT (14U) 424 #define AES_ACCEL_RESULTINTMAP_RIEN14_WIDTH (1U) 425 #define AES_ACCEL_RESULTINTMAP_RIEN14(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN14_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN14_MASK) 426 427 #define AES_ACCEL_RESULTINTMAP_RIEN15_MASK (0x8000U) 428 #define AES_ACCEL_RESULTINTMAP_RIEN15_SHIFT (15U) 429 #define AES_ACCEL_RESULTINTMAP_RIEN15_WIDTH (1U) 430 #define AES_ACCEL_RESULTINTMAP_RIEN15(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN15_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN15_MASK) 431 432 #define AES_ACCEL_RESULTINTMAP_RIEN16_MASK (0x10000U) 433 #define AES_ACCEL_RESULTINTMAP_RIEN16_SHIFT (16U) 434 #define AES_ACCEL_RESULTINTMAP_RIEN16_WIDTH (1U) 435 #define AES_ACCEL_RESULTINTMAP_RIEN16(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN16_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN16_MASK) 436 437 #define AES_ACCEL_RESULTINTMAP_RIEN17_MASK (0x20000U) 438 #define AES_ACCEL_RESULTINTMAP_RIEN17_SHIFT (17U) 439 #define AES_ACCEL_RESULTINTMAP_RIEN17_WIDTH (1U) 440 #define AES_ACCEL_RESULTINTMAP_RIEN17(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN17_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN17_MASK) 441 442 #define AES_ACCEL_RESULTINTMAP_RIEN18_MASK (0x40000U) 443 #define AES_ACCEL_RESULTINTMAP_RIEN18_SHIFT (18U) 444 #define AES_ACCEL_RESULTINTMAP_RIEN18_WIDTH (1U) 445 #define AES_ACCEL_RESULTINTMAP_RIEN18(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN18_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN18_MASK) 446 447 #define AES_ACCEL_RESULTINTMAP_RIEN19_MASK (0x80000U) 448 #define AES_ACCEL_RESULTINTMAP_RIEN19_SHIFT (19U) 449 #define AES_ACCEL_RESULTINTMAP_RIEN19_WIDTH (1U) 450 #define AES_ACCEL_RESULTINTMAP_RIEN19(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN19_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN19_MASK) 451 452 #define AES_ACCEL_RESULTINTMAP_RIEN20_MASK (0x100000U) 453 #define AES_ACCEL_RESULTINTMAP_RIEN20_SHIFT (20U) 454 #define AES_ACCEL_RESULTINTMAP_RIEN20_WIDTH (1U) 455 #define AES_ACCEL_RESULTINTMAP_RIEN20(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN20_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN20_MASK) 456 457 #define AES_ACCEL_RESULTINTMAP_RIEN21_MASK (0x200000U) 458 #define AES_ACCEL_RESULTINTMAP_RIEN21_SHIFT (21U) 459 #define AES_ACCEL_RESULTINTMAP_RIEN21_WIDTH (1U) 460 #define AES_ACCEL_RESULTINTMAP_RIEN21(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN21_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN21_MASK) 461 462 #define AES_ACCEL_RESULTINTMAP_RIEN22_MASK (0x400000U) 463 #define AES_ACCEL_RESULTINTMAP_RIEN22_SHIFT (22U) 464 #define AES_ACCEL_RESULTINTMAP_RIEN22_WIDTH (1U) 465 #define AES_ACCEL_RESULTINTMAP_RIEN22(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN22_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN22_MASK) 466 467 #define AES_ACCEL_RESULTINTMAP_RIEN23_MASK (0x800000U) 468 #define AES_ACCEL_RESULTINTMAP_RIEN23_SHIFT (23U) 469 #define AES_ACCEL_RESULTINTMAP_RIEN23_WIDTH (1U) 470 #define AES_ACCEL_RESULTINTMAP_RIEN23(x) (((uint32_t)(((uint32_t)(x)) << AES_ACCEL_RESULTINTMAP_RIEN23_SHIFT)) & AES_ACCEL_RESULTINTMAP_RIEN23_MASK) 471 /*! @} */ 472 473 /*! 474 * @} 475 */ /* end of group AES_ACCEL_Register_Masks */ 476 477 /*! 478 * @} 479 */ /* end of group AES_ACCEL_Peripheral_Access_Layer */ 480 481 #endif /* #if !defined(S32Z2_AES_ACCEL_H_) */ 482
