Home
last modified time | relevance | path

Searched refs:CLOCK_IP_GATE (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Data.c100 #define CLOCK_IP_GATE 1U macro
1080 /* ADC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1081 /* ADC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1083 /* ADC2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1086 /* ADC3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1089 /* ADC4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1092 /* ADC5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1095 /* ADC6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1098 /* ADCBIST_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
1101 /* AES_ACCEL_CLK clock */ {0U, CLOCK_IP_GATE, 0U, …
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Data.c101 #define CLOCK_IP_GATE 1U macro
768 /* ADC0_CLK clock */ {0U, CLOCK_IP_GATE, …
769 /* ADC1_CLK clock */ {0U, CLOCK_IP_GATE, …
770 /* CE_EDMA_CLK clock */ {0U, CLOCK_IP_GATE, …
771 /* CE_PIT0_CLK clock */ {0U, CLOCK_IP_GATE, …
772 /* CE_PIT1_CLK clock */ {0U, CLOCK_IP_GATE, …
773 /* CE_PIT2_CLK clock */ {0U, CLOCK_IP_GATE, …
774 /* CE_PIT3_CLK clock */ {0U, CLOCK_IP_GATE, …
775 /* CE_PIT4_CLK clock */ {0U, CLOCK_IP_GATE, …
776 /* CE_PIT5_CLK clock */ {0U, CLOCK_IP_GATE, …
[all …]