1 /* 2 * Copyright 2021-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 /** 7 * @file Clock_Ip_Data.c 8 * @version 0.9.0 9 * 10 * @brief CLOCK driver implementations. 11 * @details CLOCK driver implementations. 12 * 13 * @addtogroup CLOCK_DRIVER Clock Driver 14 * @{ 15 */ 16 17 18 #ifdef __cplusplus 19 extern "C"{ 20 #endif 21 22 23 /*================================================================================================== 24 * INCLUDE FILES 25 * 1) system and project includes 26 * 2) needed interfaces from external units 27 * 3) internal and external interfaces from this unit 28 ==================================================================================================*/ 29 30 31 #include "Clock_Ip_Private.h" 32 33 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT)) 34 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) 35 #define USER_MODE_REG_PROT_ENABLED (STD_ON) 36 #include "RegLockMacros.h" 37 #endif 38 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */ 39 40 /*================================================================================================== 41 SOURCE FILE VERSION INFORMATION 42 ==================================================================================================*/ 43 #define CLOCK_IP_DATA_VENDOR_ID_C 43 44 #define CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C 4 45 #define CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C 7 46 #define CLOCK_IP_DATA_AR_RELEASE_REVISION_VERSION_C 0 47 #define CLOCK_IP_DATA_SW_MAJOR_VERSION_C 0 48 #define CLOCK_IP_DATA_SW_MINOR_VERSION_C 9 49 #define CLOCK_IP_DATA_SW_PATCH_VERSION_C 0 50 51 /*================================================================================================== 52 * FILE VERSION CHECKS 53 ==================================================================================================*/ 54 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same vendor */ 55 #if (CLOCK_IP_DATA_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID) 56 #error "Clock_Ip_Data.c and Clock_Ip_Private.h have different vendor ids" 57 #endif 58 59 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same Autosar version */ 60 #if ((CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \ 61 (CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \ 62 (CLOCK_IP_DATA_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \ 63 ) 64 #error "AutoSar Version Numbers of Clock_Ip_Data.c and Clock_Ip_Private.h are different" 65 #endif 66 67 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same Software version */ 68 #if ((CLOCK_IP_DATA_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \ 69 (CLOCK_IP_DATA_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \ 70 (CLOCK_IP_DATA_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \ 71 ) 72 #error "Software Version Numbers of Clock_Ip_Data.c and Clock_Ip_Private.h are different" 73 #endif 74 75 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT)) 76 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) 77 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 78 /* Check if Clock_Ip_Data.c file and RegLockMacros.h file are of the same Autosar version */ 79 #if ((CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \ 80 (CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION)) 81 #error "AutoSar Version Numbers of Clock_Ip_Data.c and RegLockMacros.h are different" 82 #endif 83 #endif 84 #endif 85 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */ 86 87 /*================================================================================================== 88 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) 89 ==================================================================================================*/ 90 91 /*================================================================================================== 92 * LOCAL MACROS 93 ==================================================================================================*/ 94 95 96 97 #define CLOCK_IP_NO_CALLBACK 0U 98 #define CLOCK_IP_HWMUX_DIV_CMU 1U 99 #define CLOCK_IP_PCFS_DFS 1U 100 #define CLOCK_IP_PLL_MOD 1U 101 #define CLOCK_IP_GATE 1U 102 #define CLOCK_IP_HWMUX_CMU 2U 103 #define CLOCK_IP_PCFS_PLL_OUT 2U 104 #define CLOCK_IP_PLL 2U 105 #define CLOCK_IP_DFS 2U 106 #define CLOCK_IP_HWMUX_CMU_GATE 3U 107 #define CLOCK_IP_PLL_OUT 3U 108 #define CLOCK_IP_LFASTPLL 3U 109 #define CLOCK_IP_CMU 4U 110 #define CLOCK_IP_HWMUX 4U 111 #define CLOCK_IP_FAST_XOSC_CMU 5U 112 #define CLOCK_IP_HWMUX_DIV 5U 113 #define CLOCK_IP_HWMUX_AE 6U 114 #define CLOCK_IP_HWMUX_DIV_TRIGGER 7U 115 #define CLOCK_IP_SWMUX_DIV 8U 116 #define CLOCK_IP_CLKOUT 9U 117 #define CLOCK_IP_CLKOUT_CMU 9U 118 119 120 #define CLOCK_IP_DDR_EXTENSION 0U 121 #define CLOCK_IP_P0_SYS_EXTENSION 1U 122 #define CLOCK_IP_P1_SYS_EXTENSION 2U 123 #define CLOCK_IP_P1_SYS_DIV2_EXTENSION 3U 124 #define CLOCK_IP_P1_SYS_DIV4_EXTENSION 4U 125 #define CLOCK_IP_P2_SYS_EXTENSION 5U 126 #define CLOCK_IP_CORE_M33_EXTENSION 6U 127 #define CLOCK_IP_P2_SYS_DIV2_EXTENSION 7U 128 #define CLOCK_IP_P2_SYS_DIV4_EXTENSION 8U 129 #define CLOCK_IP_P3_SYS_EXTENSION 9U 130 #define CLOCK_IP_CE_SYS_DIV2_EXTENSION 10U 131 #define CLOCK_IP_CE_SYS_DIV4_EXTENSION 11U 132 #define CLOCK_IP_P3_SYS_DIV2_NOC_EXTENSION 12U 133 #define CLOCK_IP_P3_SYS_DIV4_EXTENSION 13U 134 #define CLOCK_IP_P4_SYS_EXTENSION 14U 135 #define CLOCK_IP_P4_SYS_DIV2_EXTENSION 15U 136 #define CLOCK_IP_HSE_SYS_DIV2_EXTENSION 16U 137 #define CLOCK_IP_P5_SYS_EXTENSION 17U 138 #define CLOCK_IP_P5_SYS_DIV2_EXTENSION 18U 139 #define CLOCK_IP_P5_SYS_DIV4_EXTENSION 19U 140 #define CLOCK_IP_P2_MATH_EXTENSION 20U 141 #define CLOCK_IP_P2_MATH_DIV3_EXTENSION 21U 142 #define CLOCK_IP_GLB_LBIST_EXTENSION 22U 143 #define CLOCK_IP_RTU0_CORE_EXTENSION 23U 144 #define CLOCK_IP_RTU0_CORE_DIV2_EXTENSION 24U 145 #define CLOCK_IP_RTU1_CORE_EXTENSION 25U 146 #define CLOCK_IP_RTU1_CORE_DIV2_EXTENSION 26U 147 #define CLOCK_IP_P0_PSI5_S_UTIL_EXTENSION 27U 148 #define CLOCK_IP_P4_PSI5_S_UTIL_EXTENSION 28U 149 #define CLOCK_IP_CLKOUT0_EXTENSION 29U 150 #define CLOCK_IP_CLKOUT1_EXTENSION 30U 151 #define CLOCK_IP_CLKOUT2_EXTENSION 31U 152 #define CLOCK_IP_CLKOUT3_EXTENSION 32U 153 #define CLOCK_IP_CLKOUT4_EXTENSION 33U 154 #define CLOCK_IP_ETH0_TX_MII_EXTENSION 34U 155 #define CLOCK_IP_P3_CAN_PE_EXTENSION 35U 156 #define CLOCK_IP_P0_FR_PE_EXTENSION 36U 157 #define CLOCK_IP_P0_LIN_BAUD_EXTENSION 37U 158 #define CLOCK_IP_P1_LIN_BAUD_EXTENSION 38U 159 #define CLOCK_IP_P4_LIN_BAUD_EXTENSION 39U 160 #define CLOCK_IP_P5_LIN_BAUD_EXTENSION 40U 161 #define CLOCK_IP_P0_CLKOUT_SRC_EXTENSION 41U 162 #define CLOCK_IP_P0_CTU_PER_EXTENSION 42U 163 #define CLOCK_IP_P0_DSPI_MSC_EXTENSION 43U 164 #define CLOCK_IP_P0_EMIOS_LCU_EXTENSION 44U 165 #define CLOCK_IP_P0_GTM_EXTENSION 45U 166 #define CLOCK_IP_P0_GTM_NOC_EXTENSION 46U 167 #define CLOCK_IP_P0_GTM_TS_EXTENSION 47U 168 #define CLOCK_IP_P0_LIN_EXTENSION 48U 169 #define CLOCK_IP_P0_NANO_EXTENSION 49U 170 #define CLOCK_IP_P0_PSI5_125K_EXTENSION 50U 171 #define CLOCK_IP_P0_PSI5_189K_EXTENSION 51U 172 #define CLOCK_IP_P0_PSI5_S_BAUD_EXTENSION 52U 173 #define CLOCK_IP_P0_PSI5_S_CORE_EXTENSION 53U 174 #define CLOCK_IP_P0_PSI5_S_TRIG0_EXTENSION 54U 175 #define CLOCK_IP_P0_PSI5_S_TRIG1_EXTENSION 55U 176 #define CLOCK_IP_P0_PSI5_S_TRIG2_EXTENSION 56U 177 #define CLOCK_IP_P0_PSI5_S_TRIG3_EXTENSION 57U 178 #define CLOCK_IP_P0_PSI5_S_UART_EXTENSION 58U 179 #define CLOCK_IP_P0_PSI5_S_WDOG0_EXTENSION 59U 180 #define CLOCK_IP_P0_PSI5_S_WDOG1_EXTENSION 60U 181 #define CLOCK_IP_P0_PSI5_S_WDOG2_EXTENSION 61U 182 #define CLOCK_IP_P0_PSI5_S_WDOG3_EXTENSION 62U 183 #define CLOCK_IP_P0_REG_INTF_2X_EXTENSION 63U 184 #define CLOCK_IP_P0_REG_INTF_EXTENSION 64U 185 #define CLOCK_IP_P1_CLKOUT_SRC_EXTENSION 65U 186 #define CLOCK_IP_P1_DSPI60_EXTENSION 66U 187 #define CLOCK_IP_P1_LFAST0_REF_EXTENSION 67U 188 #define CLOCK_IP_P1_LFAST1_REF_EXTENSION 68U 189 #define CLOCK_IP_P1_LFAST_DFT_EXTENSION 69U 190 #define CLOCK_IP_P1_NETC_AXI_EXTENSION 70U 191 #define CLOCK_IP_P1_LIN_EXTENSION 71U 192 #define CLOCK_IP_ETH_TS_EXTENSION 72U 193 #define CLOCK_IP_ETH_TS_DIV4_EXTENSION 73U 194 #define CLOCK_IP_ETH0_REF_RMII_EXTENSION 74U 195 #define CLOCK_IP_ETH0_RX_MII_EXTENSION 75U 196 #define CLOCK_IP_ETH0_RX_RGMII_EXTENSION 76U 197 #define CLOCK_IP_ETH0_TX_RGMII_EXTENSION 77U 198 #define CLOCK_IP_ETH0_TX_RGMII_LPBK_EXTENSION 78U 199 #define CLOCK_IP_ETH1_REF_RMII_EXTENSION 79U 200 #define CLOCK_IP_ETH1_RX_MII_EXTENSION 80U 201 #define CLOCK_IP_ETH1_RX_RGMII_EXTENSION 81U 202 #define CLOCK_IP_ETH1_TX_MII_EXTENSION 82U 203 #define CLOCK_IP_ETH1_TX_RGMII_EXTENSION 83U 204 #define CLOCK_IP_ETH1_TX_RGMII_LPBK_EXTENSION 84U 205 #define CLOCK_IP_P1_REG_INTF_EXTENSION 85U 206 #define CLOCK_IP_P2_DBG_ATB_EXTENSION 86U 207 #define CLOCK_IP_P2_REG_INTF_EXTENSION 87U 208 #define CLOCK_IP_P3_AES_EXTENSION 88U 209 #define CLOCK_IP_P3_CLKOUT_SRC_EXTENSION 89U 210 #define CLOCK_IP_P3_DBG_TS_EXTENSION 90U 211 #define CLOCK_IP_P3_REG_INTF_EXTENSION 91U 212 #define CLOCK_IP_P4_CLKOUT_SRC_EXTENSION 92U 213 #define CLOCK_IP_P4_DSPI60_EXTENSION 93U 214 #define CLOCK_IP_P4_EMIOS_LCU_EXTENSION 94U 215 #define CLOCK_IP_P4_LIN_EXTENSION 95U 216 #define CLOCK_IP_P4_PSI5_125K_EXTENSION 96U 217 #define CLOCK_IP_P4_PSI5_189K_EXTENSION 97U 218 #define CLOCK_IP_P4_PSI5_S_BAUD_EXTENSION 98U 219 #define CLOCK_IP_P4_PSI5_S_CORE_EXTENSION 99U 220 #define CLOCK_IP_P4_PSI5_S_TRIG0_EXTENSION 100U 221 #define CLOCK_IP_P4_PSI5_S_TRIG1_EXTENSION 101U 222 #define CLOCK_IP_P4_PSI5_S_TRIG2_EXTENSION 102U 223 #define CLOCK_IP_P4_PSI5_S_TRIG3_EXTENSION 103U 224 #define CLOCK_IP_P4_PSI5_S_UART_EXTENSION 104U 225 #define CLOCK_IP_P4_PSI5_S_WDOG0_EXTENSION 105U 226 #define CLOCK_IP_P4_PSI5_S_WDOG1_EXTENSION 106U 227 #define CLOCK_IP_P4_PSI5_S_WDOG2_EXTENSION 107U 228 #define CLOCK_IP_P4_PSI5_S_WDOG3_EXTENSION 108U 229 #define CLOCK_IP_P4_QSPI0_2X_EXTENSION 109U 230 #define CLOCK_IP_P4_QSPI0_1X_EXTENSION 110U 231 #define CLOCK_IP_P4_QSPI1_2X_EXTENSION 111U 232 #define CLOCK_IP_P4_QSPI1_1X_EXTENSION 112U 233 #define CLOCK_IP_P4_REG_INTF_2X_EXTENSION 113U 234 #define CLOCK_IP_P4_REG_INTF_EXTENSION 114U 235 #define CLOCK_IP_P4_SDHC_IP_EXTENSION 115U 236 #define CLOCK_IP_P4_SDHC_IP_DIV2_EXTENSION 116U 237 #define CLOCK_IP_P5_AE_EXTENSION 117U 238 #define CLOCK_IP_P5_CANXL_PE_EXTENSION 118U 239 #define CLOCK_IP_P5_CANXL_CHI_EXTENSION 119U 240 #define CLOCK_IP_P5_CLKOUT_SRC_EXTENSION 120U 241 #define CLOCK_IP_P5_LIN_EXTENSION 121U 242 #define CLOCK_IP_P5_REG_INTF_EXTENSION 122U 243 #define CLOCK_IP_P6_REG_INTF_EXTENSION 123U 244 #define CLOCK_IP_P0_PSI5_1US_EXTENSION 124U 245 #define CLOCK_IP_P4_PSI5_1US_EXTENSION 125U 246 #define CLOCK_IP_RTU0_REG_INTF_EXTENSION 126U 247 #define CLOCK_IP_RTU1_REG_INTF_EXTENSION 127U 248 #define CLOCK_IP_P4_SDHC_EXTENSION 128U 249 #define CLOCK_IP_P0_DSPI_EXTENSION 129U 250 #define CLOCK_IP_P1_DSPI_EXTENSION 130U 251 #define CLOCK_IP_P4_DSPI_EXTENSION 131U 252 #define CLOCK_IP_P5_DSPI_EXTENSION 132U 253 254 #define CLOCK_IP_COREPLL_INSTANCE 0U 255 #define CLOCK_IP_PERIPHPLL_INSTANCE 1U 256 #define CLOCK_IP_DDRPLL_INSTANCE 2U 257 258 #define CLOCK_IP_COREDFS_INSTANCE 0U 259 #define CLOCK_IP_PERIPHDFS_INSTANCE 1U 260 261 #define CLOCK_IP_LFAST0_PLL_INSTANCE 0U 262 #define CLOCK_IP_LFAST1_PLL_INSTANCE 1U 263 264 #define CLOCK_IP_CGM0_INSTANCE 0U 265 #define CLOCK_IP_CGM1_INSTANCE 1U 266 #define CLOCK_IP_CGM2_INSTANCE 2U 267 #define CLOCK_IP_CGM3_INSTANCE 3U 268 #define CLOCK_IP_CGM4_INSTANCE 4U 269 #define CLOCK_IP_CGM5_INSTANCE 5U 270 #define CLOCK_IP_CGM6_INSTANCE 6U 271 #define CLOCK_IP_CGM7_INSTANCE 7U 272 #define CLOCK_IP_CGM8_INSTANCE 8U 273 #define CLOCK_IP_CGM_AE_INSTANCE 9U 274 275 #define CLOCK_IP_GPR0_INSTANCE 0U 276 #define CLOCK_IP_GPR1_INSTANCE 1U 277 #define CLOCK_IP_GPR3_INSTANCE 3U 278 #define CLOCK_IP_GPR4_INSTANCE 4U 279 #define CLOCK_IP_GPR5_INSTANCE 5U 280 281 #define CLOCK_IP_SMU_CMU_FC_INSTANCE 0U 282 #define CLOCK_IP_CMU_FC_0_INSTANCE 1U 283 #define CLOCK_IP_CMU_FC_1_INSTANCE 2U 284 #define CLOCK_IP_CMU_FC_2A_INSTANCE 3U 285 #define CLOCK_IP_CMU_FC_2B_INSTANCE 4U 286 #define CLOCK_IP_CMU_FC_2C_INSTANCE 5U 287 #define CLOCK_IP_CMU_FC_2D_INSTANCE 6U 288 #define CLOCK_IP_CMU_FC_3_INSTANCE 7U 289 #define CLOCK_IP_CMU_FC_4_INSTANCE 8U 290 #define CLOCK_IP_CMU_FC_5_INSTANCE 9U 291 #define CLOCK_IP_CMU_FC_6_INSTANCE 10U 292 #define CLOCK_IP_CE_CMU_FC_0_INSTANCE 11U 293 #define CLOCK_IP_CE_CMU_FC_1_INSTANCE 12U 294 #define CLOCK_IP_CE_CMU_FC_2_INSTANCE 13U 295 #define CLOCK_IP_RTU0_CMU_FC_0_INSTANCE 14U 296 #define CLOCK_IP_RTU0_CMU_FC_1_INSTANCE 15U 297 #define CLOCK_IP_RTU0_CMU_FC_2_INSTANCE 16U 298 #define CLOCK_IP_RTU0_CMU_FC_3_INSTANCE 17U 299 #define CLOCK_IP_RTU0_CMU_FC_4_INSTANCE 18U 300 #define CLOCK_IP_RTU1_CMU_FC_0_INSTANCE 19U 301 #define CLOCK_IP_RTU1_CMU_FC_1_INSTANCE 20U 302 #define CLOCK_IP_RTU1_CMU_FC_2_INSTANCE 21U 303 #define CLOCK_IP_RTU1_CMU_FC_3_INSTANCE 22U 304 #define CLOCK_IP_RTU1_CMU_FC_4_INSTANCE 23U 305 #define CLOCK_IP_CMU_FC_DEBUG_1_INSTANCE 24U 306 #define CLOCK_IP_CMU_FC_DEBUG_2_INSTANCE 25U 307 #define CLOCK_IP_CMU_FC_AE_1_INSTANCE 26U 308 #define CLOCK_IP_CMU_FC_AE_2_INSTANCE 27U 309 310 #define CLOCK_IP_P6_GROUP_0_BIT0_INDEX 0U 311 #define CLOCK_IP_P0_GROUP_13_BIT0_INDEX 1U 312 #define CLOCK_IP_P0_GROUP_12_BIT0_INDEX 2U 313 #define CLOCK_IP_P3_GROUP_1_BIT0_INDEX 3U 314 #define CLOCK_IP_P3_GROUP_27_BIT0_INDEX 4U 315 #define CLOCK_IP_P3_GROUP_28_BIT0_INDEX 5U 316 #define CLOCK_IP_P3_GROUP_29_BIT0_INDEX 6U 317 #define CLOCK_IP_P3_GROUP_30_BIT0_INDEX 7U 318 #define CLOCK_IP_P3_GROUP_31_BIT0_INDEX 8U 319 #define CLOCK_IP_P3_GROUP_32_BIT0_INDEX 9U 320 #define CLOCK_IP_P0_GROUP_20_BIT0_INDEX 10U 321 #define CLOCK_IP_P0_GROUP_5_BIT1_INDEX 11U 322 #define CLOCK_IP_P1_GROUP_1_BIT1_INDEX 12U 323 #define CLOCK_IP_P4_GROUP_2_BIT1_INDEX 13U 324 #define CLOCK_IP_P5_GROUP_0_BIT1_INDEX 14U 325 #define CLOCK_IP_P0_GROUP_5_BIT2_INDEX 15U 326 #define CLOCK_IP_P1_GROUP_1_BIT2_INDEX 16U 327 #define CLOCK_IP_P4_GROUP_2_BIT2_INDEX 17U 328 #define CLOCK_IP_P5_GROUP_0_BIT2_INDEX 18U 329 #define CLOCK_IP_P0_GROUP_5_BIT0_INDEX 19U 330 #define CLOCK_IP_P1_GROUP_1_BIT0_INDEX 20U 331 #define CLOCK_IP_P3_GROUP_0_BIT0_INDEX 21U 332 #define CLOCK_IP_P4_GROUP_2_BIT0_INDEX 22U 333 #define CLOCK_IP_P5_GROUP_0_BIT0_INDEX 23U 334 #define CLOCK_IP_P1_GROUP_12_BIT0_INDEX 24U 335 #define CLOCK_IP_P3_GROUP_3_BIT0_INDEX 25U 336 #define CLOCK_IP_P3_GROUP_4_BIT0_INDEX 26U 337 #define CLOCK_IP_P3_GROUP_5_BIT0_INDEX 27U 338 #define CLOCK_IP_P3_GROUP_6_BIT0_INDEX 28U 339 #define CLOCK_IP_P3_GROUP_7_BIT0_INDEX 29U 340 #define CLOCK_IP_P3_GROUP_8_BIT0_INDEX 30U 341 #define CLOCK_IP_P3_GROUP_9_BIT0_INDEX 31U 342 #define CLOCK_IP_P3_GROUP_10_BIT0_INDEX 32U 343 #define CLOCK_IP_P3_GROUP_11_BIT0_INDEX 33U 344 #define CLOCK_IP_P3_GROUP_12_BIT0_INDEX 34U 345 #define CLOCK_IP_P3_GROUP_13_BIT0_INDEX 35U 346 #define CLOCK_IP_P3_GROUP_14_BIT0_INDEX 36U 347 #define CLOCK_IP_P3_GROUP_15_BIT0_INDEX 37U 348 #define CLOCK_IP_P3_GROUP_16_BIT0_INDEX 38U 349 #define CLOCK_IP_P3_GROUP_17_BIT0_INDEX 39U 350 #define CLOCK_IP_P3_GROUP_18_BIT0_INDEX 40U 351 #define CLOCK_IP_P3_GROUP_19_BIT0_INDEX 41U 352 #define CLOCK_IP_P3_GROUP_20_BIT0_INDEX 42U 353 #define CLOCK_IP_P3_GROUP_21_BIT0_INDEX 43U 354 #define CLOCK_IP_P3_GROUP_22_BIT0_INDEX 44U 355 #define CLOCK_IP_P3_GROUP_23_BIT0_INDEX 45U 356 #define CLOCK_IP_P3_GROUP_24_BIT0_INDEX 46U 357 #define CLOCK_IP_P3_GROUP_25_BIT0_INDEX 47U 358 #define CLOCK_IP_P3_GROUP_26_BIT0_INDEX 48U 359 #define CLOCK_IP_P0_GROUP_2_BIT0_INDEX 49U 360 #define CLOCK_IP_P0_GROUP_3_BIT0_INDEX 50U 361 #define CLOCK_IP_P0_GROUP_22_BIT0_INDEX 51U 362 #define CLOCK_IP_P0_GROUP_4_BIT0_INDEX 52U 363 #define CLOCK_IP_P1_GROUP_0_BIT0_INDEX 53U 364 #define CLOCK_IP_P4_GROUP_11_BIT0_INDEX 54U 365 #define CLOCK_IP_P0_GROUP_8_BIT0_INDEX 55U 366 #define CLOCK_IP_P0_GROUP_9_BIT0_INDEX 56U 367 #define CLOCK_IP_P0_GROUP_10_BIT0_INDEX 57U 368 #define CLOCK_IP_P1_GROUP_5_BIT0_INDEX 58U 369 #define CLOCK_IP_P1_GROUP_6_BIT0_INDEX 59U 370 #define CLOCK_IP_P1_GROUP_7_BIT0_INDEX 60U 371 #define CLOCK_IP_P4_GROUP_6_BIT0_INDEX 61U 372 #define CLOCK_IP_P4_GROUP_7_BIT0_INDEX 62U 373 #define CLOCK_IP_P4_GROUP_8_BIT0_INDEX 63U 374 #define CLOCK_IP_P5_GROUP_3_BIT0_INDEX 64U 375 #define CLOCK_IP_P5_GROUP_4_BIT0_INDEX 65U 376 #define CLOCK_IP_P5_GROUP_5_BIT0_INDEX 66U 377 #define CLOCK_IP_P0_GROUP_6_BIT0_INDEX 67U 378 #define CLOCK_IP_P0_GROUP_11_BIT0_INDEX 68U 379 #define CLOCK_IP_P0_GROUP_22_BIT1_INDEX 69U 380 #define CLOCK_IP_P0_GROUP_5_BIT3_INDEX 70U 381 #define CLOCK_IP_P1_GROUP_1_BIT3_INDEX 71U 382 #define CLOCK_IP_P4_GROUP_2_BIT3_INDEX 72U 383 #define CLOCK_IP_P5_GROUP_0_BIT3_INDEX 73U 384 #define CLOCK_IP_P0_GROUP_19_BIT0_INDEX 74U 385 #define CLOCK_IP_P4_GROUP_12_BIT0_INDEX 75U 386 #define CLOCK_IP_P0_GROUP_23_BIT0_INDEX 76U 387 #define CLOCK_IP_P4_GROUP_14_BIT0_INDEX 77U 388 #define CLOCK_IP_P4_GROUP_0_BIT0_INDEX 78U 389 #define CLOCK_IP_P4_GROUP_1_BIT0_INDEX 79U 390 #define CLOCK_IP_P3_GROUP_33_BIT0_INDEX 80U 391 #define CLOCK_IP_P4_GROUP_9_BIT0_INDEX 81U 392 #define CLOCK_IP_P0_GROUP_24_BIT0_INDEX 82U 393 #define CLOCK_IP_P1_GROUP_8_BIT0_INDEX 83U 394 #define CLOCK_IP_P1_GROUP_9_BIT0_INDEX 84U 395 #define CLOCK_IP_P0_GROUP_21_BIT0_INDEX 85U 396 #define CLOCK_IP_P1_GROUP_14_BIT0_INDEX 86U 397 #define CLOCK_IP_P4_GROUP_13_BIT0_INDEX 87U 398 #define CLOCK_IP_P5_GROUP_6_BIT0_INDEX 88U 399 #define CLOCK_IP_P0_GROUP_1_BIT0_INDEX 89U 400 #define CLOCK_IP_P0_GROUP_7_BIT0_INDEX 90U 401 #define CLOCK_IP_P1_GROUP_2_BIT0_INDEX 91U 402 #define CLOCK_IP_P1_GROUP_3_BIT0_INDEX 92U 403 #define CLOCK_IP_P1_GROUP_4_BIT0_INDEX 93U 404 #define CLOCK_IP_P4_GROUP_3_BIT0_INDEX 94U 405 #define CLOCK_IP_P4_GROUP_4_BIT0_INDEX 95U 406 #define CLOCK_IP_P4_GROUP_5_BIT0_INDEX 96U 407 #define CLOCK_IP_P5_GROUP_1_BIT0_INDEX 97U 408 #define CLOCK_IP_P5_GROUP_2_BIT0_INDEX 98U 409 #define CLOCK_IP_P1_GROUP_10_BIT0_INDEX 99U 410 #define CLOCK_IP_P4_GROUP_10_BIT0_INDEX 100U 411 412 #define CLOCK_IP_GATE_0_INDEX 0U 413 #define CLOCK_IP_GATE_1_INDEX 1U 414 #define CLOCK_IP_GATE_2_INDEX 2U 415 #define CLOCK_IP_GATE_3_INDEX 3U 416 #define CLOCK_IP_GATE_4_INDEX 4U 417 #define CLOCK_IP_GATE_5_INDEX 5U 418 #define CLOCK_IP_GATE_6_INDEX 6U 419 #define CLOCK_IP_GATE_7_INDEX 7U 420 #define CLOCK_IP_GATE_8_INDEX 8U 421 #define CLOCK_IP_GATE_9_INDEX 9U 422 #define CLOCK_IP_GATE_10_INDEX 10U 423 #define CLOCK_IP_GATE_11_INDEX 11U 424 #define CLOCK_IP_GATE_12_INDEX 12U 425 #define CLOCK_IP_GATE_13_INDEX 13U 426 #define CLOCK_IP_GATE_14_INDEX 14U 427 #define CLOCK_IP_GATE_15_INDEX 15U 428 #define CLOCK_IP_GATE_16_INDEX 16U 429 #define CLOCK_IP_GATE_17_INDEX 17U 430 #define CLOCK_IP_GATE_18_INDEX 18U 431 #define CLOCK_IP_GATE_19_INDEX 19U 432 #define CLOCK_IP_GATE_20_INDEX 20U 433 #define CLOCK_IP_GATE_21_INDEX 21U 434 #define CLOCK_IP_GATE_22_INDEX 22U 435 #define CLOCK_IP_GATE_23_INDEX 23U 436 #define CLOCK_IP_GATE_24_INDEX 24U 437 #define CLOCK_IP_GATE_25_INDEX 25U 438 #define CLOCK_IP_GATE_26_INDEX 26U 439 #define CLOCK_IP_GATE_27_INDEX 27U 440 #define CLOCK_IP_GATE_28_INDEX 28U 441 #define CLOCK_IP_GATE_29_INDEX 29U 442 #define CLOCK_IP_GATE_30_INDEX 30U 443 #define CLOCK_IP_GATE_31_INDEX 31U 444 #define CLOCK_IP_GATE_32_INDEX 32U 445 #define CLOCK_IP_GATE_33_INDEX 33U 446 447 #define CLOCK_IP_GROUP_0_INDEX 0U 448 #define CLOCK_IP_GROUP_1_INDEX 1U 449 #define CLOCK_IP_GROUP_3_INDEX 3U 450 #define CLOCK_IP_GROUP_4_INDEX 4U 451 #define CLOCK_IP_GROUP_5_INDEX 5U 452 #define CLOCK_IP_GROUP_6_INDEX 6U 453 454 #define CLOCK_IP_DIV_0_INDEX 0U 455 #define CLOCK_IP_DIV_1_INDEX 1U 456 #define CLOCK_IP_DIV_2_INDEX 2U 457 #define CLOCK_IP_DIV_3_INDEX 3U 458 #define CLOCK_IP_DIV_4_INDEX 4U 459 #define CLOCK_IP_DIV_5_INDEX 5U 460 #define CLOCK_IP_DIV_6_INDEX 6U 461 #define CLOCK_IP_DIV_7_INDEX 7U 462 463 #define CLOCK_IP_GATE_PCTL_0 0U 464 #define CLOCK_IP_GATE_PCTL_1 1U 465 #define CLOCK_IP_GATE_PCTL_2 2U 466 #define CLOCK_IP_GATE_PCTL_3 3U 467 468 469 #define CLOCK_IP_SEL_0_INDEX 0U 470 #define CLOCK_IP_SEL_1_INDEX 1U 471 #define CLOCK_IP_SEL_2_INDEX 2U 472 #define CLOCK_IP_SEL_3_INDEX 3U 473 #define CLOCK_IP_SEL_4_INDEX 4U 474 #define CLOCK_IP_SEL_5_INDEX 5U 475 #define CLOCK_IP_SEL_6_INDEX 6U 476 #define CLOCK_IP_SEL_7_INDEX 7U 477 #define CLOCK_IP_SEL_8_INDEX 8U 478 #define CLOCK_IP_SEL_9_INDEX 9U 479 #define CLOCK_IP_SEL_10_INDEX 10 480 #define CLOCK_IP_SEL_11_INDEX 11 481 #define CLOCK_IP_SEL_12_INDEX 12 482 #define CLOCK_IP_SEL_13_INDEX 13 483 #define CLOCK_IP_SEL_14_INDEX 14 484 485 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 486 #define CLOCK_IP_PCFS_1_INDEX 1U 487 #endif 488 #define CLOCK_IP_PCFS_2_INDEX 2U 489 #define CLOCK_IP_PCFS_9_INDEX 9U 490 #define CLOCK_IP_PCFS_10_INDEX 10U 491 #define CLOCK_IP_PCFS_11_INDEX 11U 492 #define CLOCK_IP_PCFS_14_INDEX 14U 493 #define CLOCK_IP_PCFS_39_INDEX 39U 494 495 #if defined(IP_RTU0__MC_CGM) 496 #define CLOCK_IP_RTU0__MC_CGM IP_RTU0__MC_CGM 497 #endif 498 #if defined(IP_RTU1__MC_CGM) 499 #define CLOCK_IP_RTU1__MC_CGM IP_RTU1__MC_CGM 500 #endif 501 502 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 503 #define CLOCK_IP_SAFE_POWER_MODE 0U 504 #endif 505 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 506 #define CLOCK_IP_DRUN_POWER_MODE 1U 507 #endif 508 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 509 #define CLOCK_IP_RUN0_POWER_MODE 2U 510 #endif 511 512 #define CLOCK_IP_COREPLL_DIVIDER_COUNT 1U 513 #define CLOCK_IP_PERIPHPLL_DIVIDER_COUNT 7U 514 #define CLOCK_IP_DDRPLL_DIVIDER_COUNT 1U 515 /*================================================================================================== 516 LOCAL CONSTANTS 517 ==================================================================================================*/ 518 519 520 /*================================================================================================== 521 LOCAL VARIABLES 522 ==================================================================================================*/ 523 524 525 /*================================================================================================== 526 GLOBAL CONSTANTS 527 ==================================================================================================*/ 528 529 /* Clock start constant section data */ 530 #define MCU_START_SEC_CONST_8 531 #include "Mcu_MemMap.h" 532 533 const uint8 Clock_Ip_au8DividerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 534 CLOCK_IP_NO_CALLBACK, /* No callback */ 535 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_HWMUX_DIV_CMU */ 536 CLOCK_IP_PLLDIG_PLL0DIV_DE_DIV_OUTPUT, /* CLOCK_IP_PCFS_PLL_OUT */ 537 CLOCK_IP_PLLDIG_PLL0DIV_DE_DIV_OUTPUT, /* CLOCK_IP_PLL_OUT */ 538 CLOCK_IP_NO_CALLBACK, /* No callback */ 539 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_HWMUX_DIV */ 540 CLOCK_IP_NO_CALLBACK, /* No callback */ 541 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE_WITH_TRIGGER, /* CLOCK_IP_HWMUX_DIV_TRIGGER */ 542 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /*CLOCK_IP_SWMUX_DIV */ 543 CLOCK_IP_NO_CALLBACK, /* No callback */ 544 }; 545 const uint8 Clock_Ip_au8DividerTriggerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 546 CLOCK_IP_NO_CALLBACK, /* No callback */ 547 CLOCK_IP_NO_CALLBACK, /* No callback */ 548 CLOCK_IP_NO_CALLBACK, /* No callback */ 549 CLOCK_IP_NO_CALLBACK, /* No callback */ 550 CLOCK_IP_NO_CALLBACK, /* No callback */ 551 CLOCK_IP_NO_CALLBACK, /* No callback */ 552 CLOCK_IP_NO_CALLBACK, /* No callback */ 553 CLOCK_IP_CGM_X_DIV_TRIG_CTRL_TCTL_HHEN_UPD_STAT, /* CLOCK_IP_HWMUX_DIV_TRIGGER */ 554 CLOCK_IP_NO_CALLBACK, /* No callback */ 555 CLOCK_IP_NO_CALLBACK, /* No callback */ 556 }; 557 const uint8 Clock_Ip_au8XoscCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 558 CLOCK_IP_NO_CALLBACK, /* No callback */ 559 CLOCK_IP_NO_CALLBACK, /* No callback */ 560 CLOCK_IP_NO_CALLBACK, /* No callback */ 561 CLOCK_IP_NO_CALLBACK, /* No callback */ 562 CLOCK_IP_NO_CALLBACK, /* No callback */ 563 CLOCK_IP_FXOSC_OSCON_BYP_EOCV_GM_SEL, /* CLOCK_IP_FAST_XOSC_CMU */ 564 CLOCK_IP_NO_CALLBACK, /* No callback */ 565 CLOCK_IP_NO_CALLBACK, /* No callback */ 566 CLOCK_IP_NO_CALLBACK, /* No callback */ 567 CLOCK_IP_NO_CALLBACK, /* No callback */ 568 }; 569 const uint8 Clock_Ip_au8IrcoscCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 570 CLOCK_IP_NO_CALLBACK, /* No callback */ 571 CLOCK_IP_NO_CALLBACK, /* No callback */ 572 CLOCK_IP_NO_CALLBACK, /* No callback */ 573 CLOCK_IP_NO_CALLBACK, /* No callback */ 574 CLOCK_IP_NO_CALLBACK, /* No callback */ 575 CLOCK_IP_NO_CALLBACK, /* No callback */ 576 CLOCK_IP_NO_CALLBACK, /* No callback */ 577 CLOCK_IP_NO_CALLBACK, /* No callback */ 578 CLOCK_IP_NO_CALLBACK, /* No callback */ 579 CLOCK_IP_NO_CALLBACK, /* No callback */ 580 }; 581 const uint8 Clock_Ip_au8GateCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 582 CLOCK_IP_NO_CALLBACK, /* No callback */ 583 CLOCK_IP_CONTROL_ENABLE_GPR_PCTL, /* CLOCK_IP_GATE */ 584 CLOCK_IP_NO_CALLBACK, /* No callback */ 585 CLOCK_IP_CONTROL_ENABLE_GPR_PCTL, /* CLOCK_IP_HWMUX_CMU_GATE */ 586 CLOCK_IP_NO_CALLBACK, /* No callback */ 587 CLOCK_IP_NO_CALLBACK, /* No callback */ 588 CLOCK_IP_NO_CALLBACK, /* No callback */ 589 CLOCK_IP_NO_CALLBACK, /* No callback */ 590 CLOCK_IP_NO_CALLBACK, /* No callback */ 591 CLOCK_IP_NO_CALLBACK, /* No callback */ 592 }; 593 const uint8 Clock_Ip_au8FractionalDividerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 594 CLOCK_IP_NO_CALLBACK, /* No callback */ 595 CLOCK_IP_DFS_MFI_MFN, /* CLOCK_IP_PCFS_DFS */ 596 CLOCK_IP_DFS_MFI_MFN, /* CLOCK_IP_DFS */ 597 CLOCK_IP_NO_CALLBACK, /* No callback */ 598 CLOCK_IP_NO_CALLBACK, /* No callback */ 599 CLOCK_IP_NO_CALLBACK, /* No callback */ 600 CLOCK_IP_NO_CALLBACK, /* No callback */ 601 CLOCK_IP_NO_CALLBACK, /* No callback */ 602 CLOCK_IP_NO_CALLBACK, /* No callback */ 603 CLOCK_IP_NO_CALLBACK, /* No callback */ 604 }; 605 const uint8 Clock_Ip_au8PllCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 606 CLOCK_IP_NO_CALLBACK, /* No callback */ 607 CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE,/* CLOCK_IP_PLL_MOD */ 608 CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN, /* CLOCK_IP_PLL */ 609 CLOCK_IP_LFASTPLL_ENABLE, /* CLOCK_IP_LFASTPLL */ 610 CLOCK_IP_NO_CALLBACK, /* No callback */ 611 CLOCK_IP_NO_CALLBACK, /* No callback */ 612 CLOCK_IP_NO_CALLBACK, /* No callback */ 613 CLOCK_IP_NO_CALLBACK, /* No callback */ 614 CLOCK_IP_NO_CALLBACK, /* No callback */ 615 CLOCK_IP_NO_CALLBACK, /* No callback */ 616 }; 617 const uint8 Clock_Ip_au8SelectorCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 618 CLOCK_IP_NO_CALLBACK, /* No callback */ 619 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_DIV_CMU */ 620 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_CMU */ 621 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_CMU_GATE */ 622 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX */ 623 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_DIV */ 624 #if defined(CLOCK_IP_MC_ME_AE_GS_S_SYSCLK) 625 CLOCK_IP_MC_ME_AE_GS_S_SYSCLK, /* CLOCK_IP_HWMUX_AE */ 626 #else 627 CLOCK_IP_NO_CALLBACK, /* No callback */ 628 #endif 629 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_DIV_TRIGGER */ 630 CLOCK_IP_CGM_X_CSC_CSS_CS_GRIP, /* CLOCK_IP_SWMUX_DIV */ 631 CLOCK_IP_GPR_X_CLKOUT_SEL_MUXSEL, /* CLOCK_IP_CLKOUT */ 632 }; 633 const uint8 Clock_Ip_au8PcfsCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 634 CLOCK_IP_NO_CALLBACK, /* No callback */ 635 CLOCK_IP_CGM_X_PCFS_SDUR_DIVC_DIVE_DIVS, /* CLOCK_IP_PCFS_DFS */ 636 CLOCK_IP_CGM_X_PCFS_SDUR_DIVC_DIVE_DIVS, /* CLOCK_IP_PCFS_PLL_OUT */ 637 CLOCK_IP_NO_CALLBACK, /* No callback */ 638 CLOCK_IP_NO_CALLBACK, /* No callback */ 639 CLOCK_IP_NO_CALLBACK, /* No callback */ 640 CLOCK_IP_NO_CALLBACK, /* No callback */ 641 CLOCK_IP_NO_CALLBACK, /* No callback */ 642 CLOCK_IP_NO_CALLBACK, /* No callback */ 643 CLOCK_IP_NO_CALLBACK, /* No callback */ 644 }; 645 const uint8 Clock_Ip_au8CmuCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 646 CLOCK_IP_NO_CALLBACK, /* No callback */ 647 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_HWMUX_DIV_CMU */ 648 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_HWMUX_CMU */ 649 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_HWMUX_CMU_GATE */ 650 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_CMU */ 651 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_FAST_XOSC_CMU */ 652 CLOCK_IP_NO_CALLBACK, /* No callback */ 653 CLOCK_IP_NO_CALLBACK, /* No callback */ 654 CLOCK_IP_NO_CALLBACK, /* No callback */ 655 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_CLKOUT_CMU */ 656 }; 657 658 659 660 661 /* Clock features mapping */ 662 const uint8 Clock_Ip_au8ClockFeatures[CLOCK_IP_NAMES_NO][CLOCK_IP_FEATURES_NO] = 663 /* \ 664 *************************************************************************************************************************************************************************************************************************************************************************************************************************************** \ 665 ************************************ ****************************** ******************************** E ******************************** ************* ********************** *********************** **************************** ********************** **************************** \ 666 ************************************ I ****************************** C ******************************** X ******************************** ************* S ********************** D *********************** **************************** ********************** **************************** \ 667 ************************************ N ****************************** A ******************************** T ******************************** P ************* E ********************** I *********************** G **************************** P ********************** **************************** \ 668 ************************************ S ****************************** L ******************************** E ******************************** O ************* L ********************** V *********************** A **************************** C ********************** C **************************** \ 669 ************************************ T ****************************** L ******************************** N ******************************** W ************* E ********************** I *********************** T **************************** F ********************** M **************************** \ 670 ************************************ A ****************************** B ******************************** S ******************************** E ************* C ********************** D *********************** E **************************** S ********************** U **************************** \ 671 ************************************ N ****************************** A ******************************** I ******************************** R ************* T ********************** E *********************** **************************** ********************** **************************** \ 672 ************************************ C ****************************** C ******************************** O ******************************** ************* O ********************** R *********************** **************************** ********************** **************************** \ 673 ************************************ E ****************************** K ******************************** N ******************************** ************* R ********************** *********************** **************************** ********************** **************************** \ 674 ************************************ ****************************** ******************************** ******************************* ************* ********************** *********************** **************************** ********************** **************************** \ 675 ***************************************************************************************************************************************************************************************************************************************************************************************************************************************/ 676 { 677 /* CLOCK_IS_OFF clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* CLOCK_IS_OFF */ 678 /* FIRC_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_2A_INSTANCE}, /* FIRC_CLK clock */ 679 /* FXOSC_CLK clock */ {0U, CLOCK_IP_FAST_XOSC_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_2B_INSTANCE}, /* FXOSC_CLK clock */ 680 /* SIRC_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* SIRC_CLK clock */ 681 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 682 /* FIRC_AE_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_PCFS_1_INDEX, CLOCK_IP_CMU_FC_2A_INSTANCE}, /* FIRC_AE_CLK clock */ 683 #endif 684 /* COREPLL_CLK clock */ {CLOCK_IP_COREPLL_INSTANCE, CLOCK_IP_PLL_MOD, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* COREPLL_CLK clock */ 685 /* PERIPHPLL_CLK clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* PERIPHPLL_CLK clock */ 686 /* DDRPLL_CLK clock */ {CLOCK_IP_DDRPLL_INSTANCE, CLOCK_IP_PLL_MOD, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* DDRPLL_CLK clock */ 687 /* LFAST0_PLL_CLK clock */ {CLOCK_IP_LFAST0_PLL_INSTANCE, CLOCK_IP_LFASTPLL, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST0_PLL_CLK clock */ 688 /* LFAST1_PLL_CLK clock */ {CLOCK_IP_LFAST1_PLL_INSTANCE, CLOCK_IP_LFASTPLL, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST1_PLL_CLK clock */ 689 /* COREPLL_PHI0 clock */ {CLOCK_IP_COREPLL_INSTANCE, CLOCK_IP_PCFS_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_9_INDEX, 0U}, /* COREPLL_PHI0 clock */ 690 /* COREPLL_DFS0 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_PCFS_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_10_INDEX, 0U}, /* COREPLL_DFS0 clock */ 691 /* COREPLL_DFS1 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_PCFS_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_1_INDEX, 0U, CLOCK_IP_PCFS_11_INDEX, 0U}, /* COREPLL_DFS1 clock */ 692 /* COREPLL_DFS2 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* COREPLL_DFS2 clock */ 693 /* COREPLL_DFS3 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* COREPLL_DFS3 clock */ 694 /* COREPLL_DFS4 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_PCFS_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_4_INDEX, 0U, CLOCK_IP_PCFS_14_INDEX, 0U}, /* COREPLL_DFS4 clock */ 695 /* COREPLL_DFS5 clock */ {CLOCK_IP_COREDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* COREPLL_DFS5 clock */ 696 /* PERIPHPLL_PHI0 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI0 clock */ 697 /* PERIPHPLL_PHI1 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI1 clock */ 698 /* PERIPHPLL_PHI2 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI2 clock */ 699 /* PERIPHPLL_PHI3 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI3 clock */ 700 /* PERIPHPLL_PHI4 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI4 clock */ 701 /* PERIPHPLL_PHI5 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI5 clock */ 702 /* PERIPHPLL_PHI6 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_6_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_PHI6 clock */ 703 /* PERIPHPLL_DFS0 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS0 clock */ 704 /* PERIPHPLL_DFS1 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS1 clock */ 705 /* PERIPHPLL_DFS2 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS2 clock */ 706 /* PERIPHPLL_DFS3 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS3 clock */ 707 /* PERIPHPLL_DFS4 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS4 clock */ 708 /* PERIPHPLL_DFS5 clock */ {CLOCK_IP_PERIPHDFS_INSTANCE, CLOCK_IP_DFS, 0U, 0U, 0U, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* PERIPHPLL_DFS5 clock */ 709 /* DDRPLL_PHI0 clock */ {CLOCK_IP_DDRPLL_INSTANCE, CLOCK_IP_PCFS_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_39_INDEX, 0U}, /* DDRPLL_PHI0 clock */ 710 /* LFAST0_PLL_PH0_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST0_PLL_PH0_CLK clock */ 711 /* LFAST0_PLL_PH0_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST0_PLL_PH0_CLK clock */ 712 /* eth_rgmii_ref clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth_rgmii_ref clock */ 713 /* eth_ext_ts clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth_ext_ts clock */ 714 /* eth0_ext_rx clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth0_ext_rx clock */ 715 /* eth0_ext_tx clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth0_ext_tx clock */ 716 /* eth1_ext_rx clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth1_ext_rx clock */ 717 /* eth1_ext_tx clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* eth1_ext_tx clock */ 718 /* lfast0_ext_ref clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* lfast0_ext_ref clock */ 719 /* lfast1_ext_ref clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* lfast1_ext_ref clock */ 720 /* DDR_CLK clock */ {CLOCK_IP_CGM6_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_DDR_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_P6_GROUP_0_BIT0_INDEX, 0U, CLOCK_IP_CMU_FC_6_INSTANCE}, /* DDR_CLK clock */ 721 /* P0_SYS_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P0_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P0_SYS_CLK clock */ 722 /* P1_SYS_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P1_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P1_SYS_CLK clock */ 723 /* P1_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P1_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P1_SYS_DIV2_CLK clock */ 724 /* P1_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P1_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P1_SYS_DIV4_CLK clock */ 725 /* P2_SYS_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_HWMUX_CMU, CLOCK_IP_P2_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, CLOCK_IP_SMU_CMU_FC_INSTANCE}, /* P2_SYS_CLK clock */ 726 /* CORE_M33_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_CORE_M33_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* CORE_M33_CLK clock */ 727 /* P2_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P2_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P2_SYS_DIV2_CLK clock */ 728 /* P2_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P2_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P2_SYS_DIV4_CLK clock */ 729 /* P3_SYS_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P3_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P3_SYS_CLK clock */ 730 /* CE_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_CMU, CLOCK_IP_CE_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, CLOCK_IP_CE_CMU_FC_2_INSTANCE}, /* CE_SYS_DIV2_CLK clock */ 731 /* CE_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_CE_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* CE_SYS_DIV4_CLK clock */ 732 /* P3_SYS_DIV2_NOC_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P3_SYS_DIV2_NOC_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P3_SYS_DIV2_NOC_CLK clock */ 733 /* P3_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P3_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P3_SYS_DIV4_CLK clock */ 734 /* P4_SYS_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P4_SYS_CLK clock */ 735 /* P4_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P4_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P4_SYS_DIV2_CLK clock */ 736 /* HSE_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_HSE_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* HSE_SYS_DIV2_CLK clock */ 737 /* P5_SYS_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_SYS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P5_SYS_CLK clock */ 738 /* P5_SYS_DIV2_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P5_SYS_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P5_SYS_DIV2_CLK clock */ 739 /* P5_SYS_DIV4_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P5_SYS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* P5_SYS_DIV4_CLK clock */ 740 /* P2_MATH_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_HWMUX_CMU, CLOCK_IP_P2_MATH_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, CLOCK_IP_CMU_FC_2C_INSTANCE}, /* P2_MATH_CLK clock */ 741 /* P2_MATH_DIV3_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_P2_MATH_DIV3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P2_MATH_DIV3_CLK clock */ 742 /* GLB_LBIST_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_GLB_LBIST_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* GLB_LBIST_CLK clock */ 743 /* RTU0_CORE_CLK clock */ {CLOCK_IP_CGM7_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_RTU0_CORE_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* RTU0_CORE_CLK clock */ 744 /* RTU0_CORE_DIV2_CLK clock */ {CLOCK_IP_CGM7_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_RTU0_CORE_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* RTU0_CORE_DIV2_CLK clock */ 745 /* RTU1_CORE_CLK clock */ {CLOCK_IP_CGM8_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_RTU1_CORE_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* RTU1_CORE_CLK clock */ 746 /* RTU1_CORE_DIV2_CLK clock */ {CLOCK_IP_CGM8_INSTANCE, CLOCK_IP_NO_CALLBACK, CLOCK_IP_RTU1_CORE_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* RTU1_CORE_DIV2_CLK clock */ 747 /* P0_PSI5_S_UTIL_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_UTIL_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_UTIL_CLK clock */ 748 /* P4_PSI5_S_UTIL_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_UTIL_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_UTIL_CLK clock */ 749 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 750 /* SYSTEM_DRUN_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_HWMUX_AE, 0U, CLOCK_IP_DRUN_POWER_MODE,0U, 0U, 0U, 0U, 0U}, /* SYSTEM_DRUN_CLK clock */ 751 #endif 752 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 753 /* SYSTEM_RUN0_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_HWMUX_AE, 0U, CLOCK_IP_RUN0_POWER_MODE,0U, 0U, 0U, 0U, 0U}, /* SYSTEM_RUN0_CLK clock */ 754 #endif 755 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 756 /* SYSTEM_SAFE_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_HWMUX_AE, 0U, CLOCK_IP_SAFE_POWER_MODE,0U, 0U, 0U, 0U, 0U}, /* SYSTEM_SAFE_CLK clock */ 757 #endif 758 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 759 /* SYSTEM_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* SYSTEM_CLK clock */ 760 #endif 761 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 762 /* SYSTEM_DIV2_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_AE_1_INSTANCE}, /* SYSTEM_DIV2_CLK clock */ 763 #endif 764 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 765 /* SYSTEM_DIV4_CLK clock */ {CLOCK_IP_CGM_AE_INSTANCE, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_AE_1_INSTANCE}, /* SYSTEM_DIV4_CLK clock */ 766 #endif 767 /* THE_LAST_PRODUCER_CLK */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* THE_LAST_PRODUCER_CLK */ 768 /* ADC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_13_BIT0_INDEX, 0U, 0U}, /* ADC0_CLK clock */ 769 /* ADC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_12_BIT0_INDEX, 0U, 0U}, /* ADC1_CLK clock */ 770 /* CE_EDMA_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_1_BIT0_INDEX, 0U, 0U}, /* CE_EDMA_CLK clock */ 771 /* CE_PIT0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_27_BIT0_INDEX, 0U, 0U}, /* CE_PIT0_CLK clock */ 772 /* CE_PIT1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_28_BIT0_INDEX, 0U, 0U}, /* CE_PIT1_CLK clock */ 773 /* CE_PIT2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_29_BIT0_INDEX, 0U, 0U}, /* CE_PIT2_CLK clock */ 774 /* CE_PIT3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_30_BIT0_INDEX, 0U, 0U}, /* CE_PIT3_CLK clock */ 775 /* CE_PIT4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_31_BIT0_INDEX, 0U, 0U}, /* CE_PIT4_CLK clock */ 776 /* CE_PIT5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_32_BIT0_INDEX, 0U, 0U}, /* CE_PIT5_CLK clock */ 777 /* CLKOUT0_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT0_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT0_CLK clock */ 778 /* CLKOUT1_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT1_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT1_CLK clock */ 779 /* CLKOUT2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT2_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT2_CLK clock */ 780 /* CLKOUT3_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT3_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT3_CLK clock */ 781 /* CLKOUT4_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT4_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT4_CLK clock */ 782 /* CTU_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_20_BIT0_INDEX, 0U, 0U}, /* CTU_CLK clock */ 783 /* DMACRC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_5_BIT1_INDEX, 0U, 0U}, /* DMACRC0_CLK clock */ 784 /* DMACRC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_1_BIT1_INDEX, 0U, 0U}, /* DMACRC1_CLK clock */ 785 /* DMACRC4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_2_BIT1_INDEX, 0U, 0U}, /* DMACRC4_CLK clock */ 786 /* DMACRC5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_0_BIT1_INDEX, 0U, 0U}, /* DMACRC5_CLK clock */ 787 /* DMAMUX0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_5_BIT2_INDEX, 0U, 0U}, /* DMAMUX0_CLK clock */ 788 /* DMAMUX1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_1_BIT2_INDEX, 0U, 0U}, /* DMAMUX1_CLK clock */ 789 /* DMAMUX4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_2_BIT2_INDEX, 0U, 0U}, /* DMAMUX4_CLK clock */ 790 /* DMAMUX5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_0_BIT2_INDEX, 0U, 0U}, /* DMAMUX5_CLK clock */ 791 /* EDMA0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_5_BIT0_INDEX, 0U, 0U}, /* EDMA0_CLK clock */ 792 /* EDMA1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_1_BIT0_INDEX, 0U, 0U}, /* EDMA1_CLK clock */ 793 /* EDMA3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_0_BIT0_INDEX, 0U, 0U}, /* EDMA3_CLK clock */ 794 /* EDMA4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_2_BIT0_INDEX, 0U, 0U}, /* EDMA4_CLK clock */ 795 /* EDMA5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_0_BIT0_INDEX, 0U, 0U}, /* EDMA5_CLK clock */ 796 /* ETH0_TX_MII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_TX_MII_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH0_TX_MII_CLK clock */ 797 /* ENET0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_12_BIT0_INDEX, 0U, 0U}, /* ENET0_CLK clock */ 798 /* P3_CAN_PE_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P3_CAN_PE_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P3_CAN_PE_CLK clock */ 799 /* FLEXCAN0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_3_BIT0_INDEX, 0U, 0U}, /* FLEXCAN0_CLK clock */ 800 /* FLEXCAN1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_4_BIT0_INDEX, 0U, 0U}, /* FLEXCAN1_CLK clock */ 801 /* FLEXCAN2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_5_BIT0_INDEX, 0U, 0U}, /* FLEXCAN2_CLK clock */ 802 /* FLEXCAN3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_6_BIT0_INDEX, 0U, 0U}, /* FLEXCAN3_CLK clock */ 803 /* FLEXCAN4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_7_BIT0_INDEX, 0U, 0U}, /* FLEXCAN4_CLK clock */ 804 /* FLEXCAN5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_8_BIT0_INDEX, 0U, 0U}, /* FLEXCAN5_CLK clock */ 805 /* FLEXCAN6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_9_BIT0_INDEX, 0U, 0U}, /* FLEXCAN6_CLK clock */ 806 /* FLEXCAN7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_10_BIT0_INDEX, 0U, 0U}, /* FLEXCAN7_CLK clock */ 807 /* FLEXCAN8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_11_BIT0_INDEX, 0U, 0U}, /* FLEXCAN8_CLK clock */ 808 /* FLEXCAN9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_12_BIT0_INDEX, 0U, 0U}, /* FLEXCAN9_CLK clock */ 809 /* FLEXCAN10_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_13_BIT0_INDEX, 0U, 0U}, /* FLEXCAN10_CLK clock */ 810 /* FLEXCAN11_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_14_BIT0_INDEX, 0U, 0U}, /* FLEXCAN11_CLK clock */ 811 /* FLEXCAN12_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_15_BIT0_INDEX, 0U, 0U}, /* FLEXCAN12_CLK clock */ 812 /* FLEXCAN13_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_16_BIT0_INDEX, 0U, 0U}, /* FLEXCAN13_CLK clock */ 813 /* FLEXCAN14_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_17_BIT0_INDEX, 0U, 0U}, /* FLEXCAN14_CLK clock */ 814 /* FLEXCAN15_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_18_BIT0_INDEX, 0U, 0U}, /* FLEXCAN15_CLK clock */ 815 /* FLEXCAN16_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_19_BIT0_INDEX, 0U, 0U}, /* FLEXCAN16_CLK clock */ 816 /* FLEXCAN17_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_20_BIT0_INDEX, 0U, 0U}, /* FLEXCAN17_CLK clock */ 817 /* FLEXCAN18_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_21_BIT0_INDEX, 0U, 0U}, /* FLEXCAN18_CLK clock */ 818 /* FLEXCAN19_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_22_BIT0_INDEX, 0U, 0U}, /* FLEXCAN19_CLK clock */ 819 /* FLEXCAN20_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_23_BIT0_INDEX, 0U, 0U}, /* FLEXCAN20_CLK clock */ 820 /* FLEXCAN21_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_24_BIT0_INDEX, 0U, 0U}, /* FLEXCAN21_CLK clock */ 821 /* FLEXCAN22_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_25_BIT0_INDEX, 0U, 0U}, /* FLEXCAN22_CLK clock */ 822 /* FLEXCAN23_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_26_BIT0_INDEX, 0U, 0U}, /* FLEXCAN23_CLK clock */ 823 /* P0_FR_PE_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_FR_PE_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, 0U, 0U, 0U, 0U}, /* P0_FR_PE_CLK clock */ 824 /* FRAY0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_2_BIT0_INDEX, 0U, 0U}, /* FRAY0_CLK clock */ 825 /* FRAY1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_3_BIT0_INDEX, 0U, 0U}, /* FRAY1_CLK clock */ 826 /* GTM_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_22_BIT0_INDEX, 0U, 0U}, /* GTM_CLK clock */ 827 /* IIIC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_4_BIT0_INDEX, 0U, 0U}, /* IIIC0_CLK clock */ 828 /* IIIC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_0_BIT0_INDEX, 0U, 0U}, /* IIIC1_CLK clock */ 829 /* IIIC2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_11_BIT0_INDEX, 0U, 0U}, /* IIIC2_CLK clock */ 830 /* P0_LIN_BAUD_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_LIN_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P0_LIN_BAUD_CLK clock */ 831 /* LIN0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_8_BIT0_INDEX, 0U, 0U}, /* LIN0_CLK clock */ 832 /* LIN1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_9_BIT0_INDEX, 0U, 0U}, /* LIN1_CLK clock */ 833 /* LIN2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_10_BIT0_INDEX, 0U, 0U}, /* LIN2_CLK clock */ 834 /* P1_LIN_BAUD_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LIN_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P1_LIN_BAUD_CLK clock */ 835 /* LIN3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_5_BIT0_INDEX, 0U, 0U}, /* LIN3_CLK clock */ 836 /* LIN4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_6_BIT0_INDEX, 0U, 0U}, /* LIN4_CLK clock */ 837 /* LIN5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_7_BIT0_INDEX, 0U, 0U}, /* LIN5_CLK clock */ 838 /* P4_LIN_BAUD_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_LIN_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, 0U, 0U, 0U, 0U}, /* P4_LIN_BAUD_CLK clock */ 839 /* LIN6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_6_BIT0_INDEX, 0U, 0U}, /* LIN6_CLK clock */ 840 /* LIN7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_7_BIT0_INDEX, 0U, 0U}, /* LIN7_CLK clock */ 841 /* LIN8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_8_BIT0_INDEX, 0U, 0U}, /* LIN8_CLK clock */ 842 /* P5_LIN_BAUD_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_LIN_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P5_LIN_BAUD_CLK clock */ 843 /* LIN9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_3_BIT0_INDEX, 0U, 0U}, /* LIN9_CLK clock */ 844 /* LIN10_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_4_BIT0_INDEX, 0U, 0U}, /* LIN10_CLK clock */ 845 /* LIN11_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_5_BIT0_INDEX, 0U, 0U}, /* LIN11_CLK clock */ 846 /* MSCDSPI_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_6_BIT0_INDEX, 0U, 0U}, /* MSCDSPI_CLK clock */ 847 /* MSCLIN_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_11_BIT0_INDEX, 0U, 0U}, /* MSCLIN_CLK clock */ 848 /* NANO_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_22_BIT1_INDEX, 0U, 0U}, /* NANO_CLK clock */ 849 /* P0_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR0_INSTANCE, CLOCK_IP_CLKOUT_CMU, CLOCK_IP_P0_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, CLOCK_IP_CMU_FC_DEBUG_1_INSTANCE}, /* P0_CLKOUT_SRC_CLK clock */ 850 /* P0_CTU_PER_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_CTU_PER_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P0_CTU_PER_CLK clock */ 851 /* P0_DSPI_MSC_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV_TRIGGER, CLOCK_IP_P0_DSPI_MSC_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P0_DSPI_MSC_CLK clock */ 852 /* P0_EMIOS_LCU_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P0_EMIOS_LCU_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, 0U, 0U, 0U, 0U}, /* P0_EMIOS_LCU_CLK clock */ 853 /* P0_GTM_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV_TRIGGER, CLOCK_IP_P0_GTM_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P0_GTM_CLK clock */ 854 /* P0_GTM_NOC_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_GTM_NOC_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P0_GTM_NOC_CLK clock */ 855 /* P0_GTM_TS_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_GTM_TS_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P0_GTM_TS_CLK clock */ 856 /* P0_LIN_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_LIN_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P0_LIN_CLK clock */ 857 /* P0_NANO_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P0_NANO_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P0_NANO_CLK clock */ 858 /* P0_PSI5_125K_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_125K_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P0_PSI5_125K_CLK clock */ 859 /* P0_PSI5_189K_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_189K_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P0_PSI5_189K_CLK clock */ 860 /* P0_PSI5_S_BAUD_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_BAUD_CLK clock */ 861 /* P0_PSI5_S_CORE_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_CORE_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P0_PSI5_S_CORE_CLK clock */ 862 /* P0_PSI5_S_TRIG0_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_TRIG0_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_TRIG0_CLK clock */ 863 /* P0_PSI5_S_TRIG1_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_TRIG1_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_TRIG1_CLK clock */ 864 /* P0_PSI5_S_TRIG2_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_TRIG2_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_TRIG2_CLK clock */ 865 /* P0_PSI5_S_TRIG3_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_TRIG3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_TRIG3_CLK clock */ 866 /* P0_PSI5_S_UART_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_UART_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_UART_CLK clock */ 867 /* P0_PSI5_S_WDOG0_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_WDOG0_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_WDOG0_CLK clock */ 868 /* P0_PSI5_S_WDOG1_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_WDOG1_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_WDOG1_CLK clock */ 869 /* P0_PSI5_S_WDOG2_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_WDOG2_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_6_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_WDOG2_CLK clock */ 870 /* P0_PSI5_S_WDOG3_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_S_WDOG3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_7_INDEX, 0U, 0U, 0U}, /* P0_PSI5_S_WDOG3_CLK clock */ 871 /* P0_REG_INTF_2X_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_REG_INTF_2X_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P0_REG_INTF_2X_CLK clock */ 872 /* P0_REG_INTF_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_P0_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_FC_0_INSTANCE}, /* P0_REG_INTF_CLK clock */ 873 /* P1_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR1_INSTANCE, CLOCK_IP_CLKOUT_CMU, CLOCK_IP_P1_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, 0U, 0U, 0U, CLOCK_IP_CMU_FC_DEBUG_2_INSTANCE}, /* P1_CLKOUT_SRC_CLK clock */ 874 /* P1_DSPI60_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P1_DSPI60_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P1_DSPI60_CLK clock */ 875 /* ETH_TS_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH_TS_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH_TS_CLK clock */ 876 /* ETH_TS_DIV4_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH_TS_DIV4_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, 0U, 0U, 0U, 0U}, /* ETH_TS_DIV4_CLK clock */ 877 /* ETH0_REF_RMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_REF_RMII_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* ETH0_REF_RMII_CLK clock */ 878 /* ETH0_RX_MII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_RX_MII_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH0_RX_MII_CLK clock */ 879 /* ETH0_RX_RGMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_RX_RGMII_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH0_RX_RGMII_CLK clock */ 880 /* ETH0_TX_RGMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_TX_RGMII_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH0_TX_RGMII_CLK clock */ 881 /* ETH0_TX_RGMII_LPBK_CLK */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH0_TX_RGMII_LPBK_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH0_TX_RGMII_LPBK_CLK */ 882 /* ETH1_REF_RMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_REF_RMII_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* ETH1_REF_RMII_CLK clock */ 883 /* ETH1_RX_MII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_RX_MII_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH1_RX_MII_CLK clock */ 884 /* ETH1_RX_RGMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_RX_RGMII_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH1_RX_RGMII_CLK clock */ 885 /* ETH1_TX_MII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_TX_MII_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* ETH1_TX_MII_CLK clock */ 886 /* ETH1_TX_RGMII_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_TX_RGMII_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH1_TX_RGMII_CLK clock */ 887 /* ETH1_TX_RGMII_LPBK_CLK */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_ETH1_TX_RGMII_LPBK_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* ETH1_TX_RGMII_LPBK_CLK */ 888 /* P1_LFAST0_REF_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LFAST0_REF_EXTENSION, 0U, CLOCK_IP_SEL_11_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P1_LFAST0_REF_CLK clock */ 889 /* P1_LFAST1_REF_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LFAST1_REF_EXTENSION, 0U, CLOCK_IP_SEL_12_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P1_LFAST1_REF_CLK clock */ 890 /* P1_LFAST_DFT_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LFAST_DFT_EXTENSION, 0U, CLOCK_IP_SEL_13_INDEX, 0U, 0U, 0U, 0U}, /* P1_LFAST_DFT_CLK clock */ 891 /* P1_NETC_AXI_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_NETC_AXI_EXTENSION, 0U, CLOCK_IP_SEL_14_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P1_NETC_AXI_CLK clock */ 892 /* P1_LIN_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P1_LIN_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P1_LIN_CLK clock */ 893 /* P1_REG_INTF_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_P1_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_FC_1_INSTANCE}, /* P1_REG_INTF_CLK clock */ 894 /* P2_DBG_ATB_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P2_DBG_ATB_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P2_DBG_ATB_CLK clock */ 895 /* P2_REG_INTF_CLK clock */ {CLOCK_IP_CGM2_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P2_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P2_REG_INTF_CLK clock */ 896 /* P3_AES_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P3_AES_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P3_AES_CLK clock */ 897 /* P3_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR3_INSTANCE, CLOCK_IP_CLKOUT, CLOCK_IP_P3_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P3_CLKOUT_SRC_CLK clock */ 898 /* P3_DBG_TS_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P3_DBG_TS_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P3_DBG_TS_CLK clock */ 899 /* P3_REG_INTF_CLK clock */ {CLOCK_IP_CGM3_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P3_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P3_REG_INTF_CLK clock */ 900 /* P3_SYS_MON1_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_FC_3_INSTANCE}, /* P3_SYS_MON1_CLK clock */ 901 /* P3_SYS_MON2_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CE_CMU_FC_0_INSTANCE}, /* P3_SYS_MON2_CLK clock */ 902 /* P3_SYS_MON3_CLK clock */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CE_CMU_FC_1_INSTANCE}, /* P3_SYS_MON3_CLK clock */ 903 /* P4_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR4_INSTANCE, CLOCK_IP_CLKOUT, CLOCK_IP_P4_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P4_CLKOUT_SRC_CLK clock */ 904 /* P4_DSPI60_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_DSPI60_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, 0U, 0U, 0U, 0U}, /* P4_DSPI60_CLK clock */ 905 /* P4_EMIOS_LCU_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_EMIOS_LCU_EXTENSION, 0U, CLOCK_IP_SEL_11_INDEX, 0U, 0U, 0U, 0U}, /* P4_EMIOS_LCU_CLK clock */ 906 /* P4_LIN_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_LIN_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, 0U, 0U, 0U, 0U}, /* P4_LIN_CLK clock */ 907 /* P4_PSI5_125K_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_125K_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_PSI5_125K_CLK clock */ 908 /* P4_PSI5_189K_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_189K_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P4_PSI5_189K_CLK clock */ 909 /* P4_PSI5_S_BAUD_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_BAUD_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_BAUD_CLK clock */ 910 /* P4_PSI5_S_CORE_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_CORE_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P4_PSI5_S_CORE_CLK clock */ 911 /* P4_PSI5_S_TRIG0_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_TRIG0_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_TRIG0_CLK clock */ 912 /* P4_PSI5_S_TRIG1_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_TRIG1_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_TRIG1_CLK clock */ 913 /* P4_PSI5_S_TRIG2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_TRIG2_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_TRIG2_CLK clock */ 914 /* P4_PSI5_S_TRIG3_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_TRIG3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_TRIG3_CLK clock */ 915 /* P4_PSI5_S_UART_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_UART_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_UART_CLK clock */ 916 /* P4_PSI5_S_WDOG0_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_WDOG0_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_WDOG0_CLK clock */ 917 /* P4_PSI5_S_WDOG1_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_WDOG1_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_WDOG1_CLK clock */ 918 /* P4_PSI5_S_WDOG2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_WDOG2_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_6_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_WDOG2_CLK clock */ 919 /* P4_PSI5_S_WDOG3_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_S_WDOG3_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_7_INDEX, 0U, 0U, 0U}, /* P4_PSI5_S_WDOG3_CLK clock */ 920 /* P4_QSPI0_2X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_QSPI0_2X_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P4_QSPI0_2X_CLK clock */ 921 /* P4_QSPI0_1X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_QSPI0_1X_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, 0U, 0U, 0U, 0U}, /* P4_QSPI0_1X_CLK clock */ 922 /* P4_QSPI1_2X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_QSPI1_2X_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_QSPI1_2X_CLK clock */ 923 /* P4_QSPI1_1X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_QSPI1_1X_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_QSPI1_1X_CLK clock */ 924 /* P4_REG_INTF_2X_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_REG_INTF_2X_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P4_REG_INTF_2X_CLK clock */ 925 /* P4_REG_INTF_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_P4_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_FC_4_INSTANCE}, /* P4_REG_INTF_CLK clock */ 926 /* P4_SDHC_IP_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_SDHC_IP_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, 0U, 0U, 0U, 0U}, /* P4_SDHC_IP_CLK clock */ 927 /* P4_SDHC_IP_DIV2_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_SDHC_IP_DIV2_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, 0U, 0U, 0U, 0U}, /* P4_SDHC_IP_DIV2_CLK clock */ 928 /* P5_DIPORT_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P5_AE_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, 0U, 0U, 0U, 0U}, /* P5_DIPORT_CLK clock */ 929 /* P5_AE_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_AE_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_2_INDEX, 0U}, /* P5_AE_CLK clock */ 930 /* P5_CANXL_PE_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_CANXL_PE_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* P5_CANXL_PE_CLK clock */ 931 /* P5_CANXL_CHI_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_CANXL_CHI_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* P5_CANXL_CHI_CLK clock */ 932 /* P5_CLKOUT_SRC_CLK clock */ {CLOCK_IP_GPR5_INSTANCE, CLOCK_IP_CLKOUT, CLOCK_IP_P5_CLKOUT_SRC_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P5_CLKOUT_SRC_CLK clock */ 933 /* P5_LIN_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P5_LIN_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P5_LIN_CLK clock */ 934 /* P5_REG_INTF_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX_DIV_CMU, CLOCK_IP_P5_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_FC_5_INSTANCE}, /* P5_REG_INTF_CLK clock */ 935 /* P6_REG_INTF_CLK clock */ {CLOCK_IP_CGM6_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P6_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P6_REG_INTF_CLK clock */ 936 /* PIT0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_5_BIT3_INDEX, 0U, 0U}, /* PIT0_CLK clock */ 937 /* PIT1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_1_BIT3_INDEX, 0U, 0U}, /* PIT1_CLK clock */ 938 /* PIT4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_2_BIT3_INDEX, 0U, 0U}, /* PIT4_CLK clock */ 939 /* PIT5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_0_BIT3_INDEX, 0U, 0U}, /* PIT5_CLK clock */ 940 /* P0_PSI5_1US_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P0_PSI5_1US_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P0_PSI5_1US_CLK clock */ 941 /* PSI5_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_19_BIT0_INDEX, 0U, 0U}, /* PSI5_0_CLK clock */ 942 /* P4_PSI5_1US_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_PSI5_1US_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P4_PSI5_1US_CLK clock */ 943 /* PSI5_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_12_BIT0_INDEX, 0U, 0U}, /* PSI5_1_CLK clock */ 944 /* PSI5S_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_23_BIT0_INDEX, 0U, 0U}, /* PSI5S_0_CLK clock */ 945 /* PSI5S_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_14_BIT0_INDEX, 0U, 0U}, /* PSI5S_1_CLK clock */ 946 /* QSPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_0_BIT0_INDEX, 0U, 0U}, /* QSPI0_CLK clock */ 947 /* QSPI1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_1_BIT0_INDEX, 0U, 0U}, /* QSPI1_CLK clock */ 948 /* RTU0_CORE_MON1_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_0_INSTANCE}, /* RTU0_CORE_MON1_CLK */ 949 /* RTU0_CORE_MON2_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_3_INSTANCE}, /* RTU0_CORE_MON2_CLK */ 950 /* RTU0_CORE_DIV2_MON1_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_1_INSTANCE}, /* RTU0_CORE_DIV2_MON1_CLK */ 951 /* RTU0_CORE_DIV2_MON2_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_2_INSTANCE}, /* RTU0_CORE_DIV2_MON2_CLK */ 952 /* RTU0_CORE_DIV2_MON3_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU0_CMU_FC_4_INSTANCE}, /* RTU0_CORE_DIV2_MON3_CLK */ 953 /* RTU0_REG_INTF_CLK clock */ {CLOCK_IP_CGM7_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_RTU0_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, 0U, 0U, 0U, 0U}, /* RTU0_REG_INTF_CLK clock */ 954 /* RTU1_CORE_MON1_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_0_INSTANCE}, /* RTU1_CORE_MON1_CLK */ 955 /* RTU1_CORE_MON2_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_3_INSTANCE}, /* RTU1_CORE_MON2_CLK */ 956 /* RTU1_CORE_DIV2_MON1_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_1_INSTANCE}, /* RTU1_CORE_DIV2_MON1_CLK */ 957 /* RTU1_CORE_DIV2_MON2_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_2_INSTANCE}, /* RTU1_CORE_DIV2_MON2_CLK */ 958 /* RTU1_CORE_DIV2_MON3_CLK */ {0U, CLOCK_IP_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_RTU1_CMU_FC_4_INSTANCE}, /* RTU1_CORE_DIV2_MON3_CLK */ 959 /* RTU1_REG_INTF_CLK clock */ {CLOCK_IP_CGM8_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_RTU1_REG_INTF_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* RTU1_REG_INTF_CLK clock */ 960 /* P4_SDHC_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_P4_SDHC_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* P4_SDHC_CLK clock */ 961 /* RXLUT_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P3_GROUP_33_BIT0_INDEX, 0U, 0U}, /* RXLUT_CLK clock */ 962 /* SDHC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_9_BIT0_INDEX, 0U, 0U}, /* SDHC0_CLK clock */ 963 /* SINC_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_24_BIT0_INDEX, 0U, 0U}, /* SINC_CLK clock */ 964 /* SIPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_8_BIT0_INDEX, 0U, 0U}, /* SIPI0_CLK clock */ 965 /* SIPI1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_9_BIT0_INDEX, 0U, 0U}, /* SIPI1_CLK clock */ 966 /* SIUL2_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_21_BIT0_INDEX, 0U, 0U}, /* SIUL2_0_CLK clock */ 967 /* SIUL2_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_14_BIT0_INDEX, 0U, 0U}, /* SIUL2_1_CLK clock */ 968 /* SIUL2_4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_13_BIT0_INDEX, 0U, 0U}, /* SIUL2_4_CLK clock */ 969 /* SIUL2_5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_6_BIT0_INDEX, 0U, 0U}, /* SIUL2_5_CLK clock */ 970 /* P0_DSPI_CLK clock */ {CLOCK_IP_CGM0_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P0_DSPI_EXTENSION, 0U, CLOCK_IP_SEL_5_INDEX, 0U, 0U, 0U, 0U}, /* P0_DSPI_CLK clock */ 971 /* SPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_1_BIT0_INDEX, 0U, 0U}, /* SPI0_CLK clock */ 972 /* SPI1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P0_GROUP_7_BIT0_INDEX, 0U, 0U}, /* SPI1_CLK clock */ 973 /* P1_DSPI_CLK clock */ {CLOCK_IP_CGM1_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P1_DSPI_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, 0U, 0U, 0U, 0U}, /* P1_DSPI_CLK clock */ 974 /* SPI2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_2_BIT0_INDEX, 0U, 0U}, /* SPI2_CLK clock */ 975 /* SPI3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_3_BIT0_INDEX, 0U, 0U}, /* SPI3_CLK clock */ 976 /* SPI4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_4_BIT0_INDEX, 0U, 0U}, /* SPI4_CLK clock */ 977 /* P4_DSPI_CLK clock */ {CLOCK_IP_CGM4_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P4_DSPI_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, 0U, 0U, 0U, 0U}, /* P4_DSPI_CLK clock */ 978 /* SPI5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_3_BIT0_INDEX, 0U, 0U}, /* SPI5_CLK clock */ 979 /* SPI6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_4_BIT0_INDEX, 0U, 0U}, /* SPI6_CLK clock */ 980 /* SPI7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_5_BIT0_INDEX, 0U, 0U}, /* SPI7_CLK clock */ 981 /* P5_DSPI_CLK clock */ {CLOCK_IP_CGM5_INSTANCE, CLOCK_IP_HWMUX, CLOCK_IP_P5_DSPI_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, 0U, 0U, 0U, 0U}, /* P5_DSPI_CLK clock */ 982 /* SPI8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_1_BIT0_INDEX, 0U, 0U}, /* SPI8_CLK clock */ 983 /* SPI9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P5_GROUP_2_BIT0_INDEX, 0U, 0U}, /* SPI9_CLK clock */ 984 /* SRX0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P1_GROUP_10_BIT0_INDEX, 0U, 0U}, /* SRX0_CLK clock */ 985 /* SRX1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_P4_GROUP_10_BIT0_INDEX, 0U, 0U}, /* SRX1_CLK clock */ 986 /* CORE_PLL_REFCLKOUT clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* CORE_PLL_REFCLKOUT clock */ 987 /* CORE_PLL_FBCLKOUT clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* CORE_PLL_FBCLKOUT clock */ 988 /* PERIPH_PLL_REFCLKOUT clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* PERIPH_PLL_REFCLKOUT clock */ 989 /* PERIPH_PLL_FBCLKOUT clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* PERIPH_PLL_FBCLKOUT clock */ 990 }; 991 992 993 /*! 994 * @brief Converts a clock name to a selector entry clkout hardware value 995 */ 996 const uint8 Clock_Ip_au8SoftwareMuxResetValue[CLOCK_IP_NAMES_NO] = { 997 0U, /*!< CLOCK_IS_OFF */ 998 0U, /*!< FIRC_CLK */ 999 0U, /*!< FXOSC_CLK */ 1000 0U, /*!< SIRC_CLK */ 1001 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 1002 0U, /*!< FIRC_AE_CLK */ 1003 #endif 1004 0U, /*!< COREPLL_CLK */ 1005 0U, /*!< PERIPHPLL_CLK */ 1006 0U, /*!< DDRPLL_CLK */ 1007 0U, /*!< LFAST0_PLL_CLK */ 1008 0U, /*!< LFAST1_PLL_CLK */ 1009 0U, /*!< COREPLL_PHI0_CLK */ 1010 0U, /*!< COREPLL_DFS0_CLK */ 1011 0U, /*!< COREPLL_DFS1_CLK */ 1012 0U, /*!< COREPLL_DFS2_CLK */ 1013 0U, /*!< COREPLL_DFS3_CLK */ 1014 0U, /*!< COREPLL_DFS4_CLK */ 1015 0U, /*!< COREPLL_DFS5_CLK */ 1016 0U, /*!< PERIPHPLL_PHI0_CLK */ 1017 0U, /*!< PERIPHPLL_PHI1_CLK */ 1018 0U, /*!< PERIPHPLL_PHI2_CLK */ 1019 0U, /*!< PERIPHPLL_PHI3_CLK */ 1020 0U, /*!< PERIPHPLL_PHI4_CLK */ 1021 0U, /*!< PERIPHPLL_PHI5_CLK */ 1022 0U, /*!< PERIPHPLL_PHI6_CLK */ 1023 0U, /*!< PERIPHPLL_DFS0_CLK */ 1024 0U, /*!< PERIPHPLL_DFS1_CLK */ 1025 0U, /*!< PERIPHPLL_DFS2_CLK */ 1026 0U, /*!< PERIPHPLL_DFS3_CLK */ 1027 0U, /*!< PERIPHPLL_DFS4_CLK */ 1028 0U, /*!< PERIPHPLL_DFS5_CLK */ 1029 0U, /*!< DDRPLL_PHI0_CLK */ 1030 0U, /*!< LFAST0_PLL_PH0_CLK */ 1031 0U, /*!< LFAST1_PLL_PH0_CLK */ 1032 0U, /*!< ETH_RGMII_REF_CLK */ 1033 0U, /*!< ETH_EXT_TS_CLK */ 1034 0U, /*!< ETH0_EXT_RX_CLK */ 1035 0U, /*!< ETH0_EXT_TX_CLK */ 1036 0U, /*!< ETH1_EXT_RX_CLK */ 1037 0U, /*!< ETH1_EXT_TX_CLK */ 1038 0U, /*!< LFAST0_EXT_REF_CLK */ 1039 0U, /*!< LFAST1_EXT_REF_CLK */ 1040 0U, /*!< DDR_CLK */ 1041 0U, /*!< P0_SYS_CLK */ 1042 0U, /*!< P1_SYS_CLK */ 1043 0U, /*!< P1_SYS_DIV2_CLK */ 1044 0U, /*!< P1_SYS_DIV4_CLK */ 1045 0U, /*!< P2_SYS_CLK */ 1046 0U, /*!< CORE_M33_CLK */ 1047 0U, /*!< P2_SYS_DIV2_CLK */ 1048 0U, /*!< P2_SYS_DIV4_CLK */ 1049 0U, /*!< P3_SYS_CLK */ 1050 0U, /*!< CE_SYS_DIV2_CLK */ 1051 0U, /*!< CE_SYS_DIV4_CLK */ 1052 0U, /*!< P3_SYS_DIV2_NOC_CLK */ 1053 0U, /*!< P3_SYS_DIV4_CLK */ 1054 0U, /*!< P4_SYS_CLK */ 1055 0U, /*!< P4_SYS_DIV2_CLK */ 1056 0U, /*!< HSE_SYS_DIV2_CLK */ 1057 0U, /*!< P5_SYS_CLK */ 1058 0U, /*!< P5_SYS_DIV2_CLK */ 1059 0U, /*!< P5_SYS_DIV4_CLK */ 1060 0U, /*!< P2_MATH_CLK */ 1061 0U, /*!< P2_MATH_DIV3_CLK */ 1062 0U, /*!< GLB_LBIST_CLK */ 1063 0U, /*!< RTU0_CORE_CLK */ 1064 0U, /*!< RTU0_CORE_DIV2_CLK */ 1065 0U, /*!< RTU1_CORE_CLK */ 1066 0U, /*!< RTU1_CORE_DIV2_CLK */ 1067 0U, /*!< P0_PSI5_S_UTIL_CLK */ 1068 0U, /*!< P4_PSI5_S_UTIL_CLK */ 1069 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 1070 0U, /*!< SYSTEM_DRUN_CLK */ 1071 #endif 1072 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 1073 0U, /*!< SYSTEM_CLK */ 1074 #endif 1075 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 1076 0U, /*!< SYSTEM_DIV2_CLK */ 1077 #endif 1078 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 1079 0U, /*!< SYSTEM_DIV4_CLK */ 1080 #endif 1081 0U, /*!< THE_LAST_PRODUCER_CLK */ 1082 0U, /*!< ADC0_CLK */ 1083 0U, /*!< ADC1_CLK */ 1084 0U, /*!< CE_EDMA_CLK */ 1085 0U, /*!< CE_PIT0_CLK */ 1086 0U, /*!< CE_PIT1_CLK */ 1087 0U, /*!< CE_PIT2_CLK */ 1088 0U, /*!< CE_PIT3_CLK */ 1089 0U, /*!< CE_PIT4_CLK */ 1090 0U, /*!< CE_PIT5_CLK */ 1091 0U, /*!< CLKOUT0_CLK */ 1092 0U, /*!< CLKOUT1_CLK */ 1093 0U, /*!< CLKOUT2_CLK */ 1094 0U, /*!< CLKOUT3_CLK */ 1095 0U, /*!< CLKOUT4_CLK */ 1096 0U, /*!< CTU_CLK */ 1097 0U, /*!< DMACRC0_CLK */ 1098 0U, /*!< DMACRC1_CLK */ 1099 0U, /*!< DMACRC4_CLK */ 1100 0U, /*!< DMACRC5_CLK */ 1101 0U, /*!< DMAMUX0_CLK */ 1102 0U, /*!< DMAMUX1_CLK */ 1103 0U, /*!< DMAMUX4_CLK */ 1104 0U, /*!< DMAMUX5_CLK */ 1105 0U, /*!< EDMA0_CLK */ 1106 0U, /*!< EDMA1_CLK */ 1107 0U, /*!< EDMA3_CLK */ 1108 0U, /*!< EDMA4_CLK */ 1109 0U, /*!< EDMA5_CLK */ 1110 0U, /*!< ETH0_TX_MII_CLK */ 1111 0U, /*!< ENET0_CLK */ 1112 0U, /*!< P3_CAN_PE_CLK */ 1113 0U, /*!< FLEXCAN0_CLK */ 1114 0U, /*!< FLEXCAN1_CLK */ 1115 0U, /*!< FLEXCAN2_CLK */ 1116 0U, /*!< FLEXCAN3_CLK */ 1117 0U, /*!< FLEXCAN4_CLK */ 1118 0U, /*!< FLEXCAN5_CLK */ 1119 0U, /*!< FLEXCAN6_CLK */ 1120 0U, /*!< FLEXCAN7_CLK */ 1121 0U, /*!< FLEXCAN8_CLK */ 1122 0U, /*!< FLEXCAN9_CLK */ 1123 0U, /*!< FLEXCAN10_CLK */ 1124 0U, /*!< FLEXCAN11_CLK */ 1125 0U, /*!< FLEXCAN12_CLK */ 1126 0U, /*!< FLEXCAN13_CLK */ 1127 0U, /*!< FLEXCAN14_CLK */ 1128 0U, /*!< FLEXCAN15_CLK */ 1129 0U, /*!< FLEXCAN16_CLK */ 1130 0U, /*!< FLEXCAN17_CLK */ 1131 0U, /*!< FLEXCAN18_CLK */ 1132 0U, /*!< FLEXCAN19_CLK */ 1133 0U, /*!< FLEXCAN20_CLK */ 1134 0U, /*!< FLEXCAN21_CLK */ 1135 0U, /*!< FLEXCAN22_CLK */ 1136 0U, /*!< FLEXCAN23_CLK */ 1137 0U, /*!< P0_FR_PE_CLK */ 1138 0U, /*!< FRAY0_CLK */ 1139 0U, /*!< FRAY1_CLK */ 1140 0U, /*!< GTM_CLK */ 1141 0U, /*!< IIIC0_CLK */ 1142 0U, /*!< IIIC1_CLK */ 1143 0U, /*!< IIIC2_CLK */ 1144 0U, /*!< P0_LIN_BAUD_CLK */ 1145 0U, /*!< LIN0_CLK */ 1146 0U, /*!< LIN1_CLK */ 1147 0U, /*!< LIN2_CLK */ 1148 0U, /*!< P1_LIN_BAUD_CLK */ 1149 0U, /*!< LIN3_CLK */ 1150 0U, /*!< LIN4_CLK */ 1151 0U, /*!< LIN5_CLK */ 1152 0U, /*!< P4_LIN_BAUD_CLK */ 1153 0U, /*!< LIN6_CLK */ 1154 0U, /*!< LIN7_CLK */ 1155 0U, /*!< LIN8_CLK */ 1156 0U, /*!< P5_LIN_BAUD_CLK */ 1157 0U, /*!< LIN9_CLK */ 1158 0U, /*!< LIN10_CLK */ 1159 0U, /*!< LIN11_CLK */ 1160 0U, /*!< MSCDSPI_CLK */ 1161 0U, /*!< MSCLIN_CLK */ 1162 0U, /*!< NANO_CLK */ 1163 0U, /*!< P0_CLKOUT_SRC_CLK */ 1164 0U, /*!< P0_CTU_PER_CLK */ 1165 0U, /*!< P0_DSPI_MSC_CLK */ 1166 0U, /*!< P0_EMIOS_LCU_CLK */ 1167 0U, /*!< P0_GTM_CLK */ 1168 0U, /*!< P0_GTM_NOC_CLK */ 1169 0U, /*!< P0_GTM_TS_CLK */ 1170 0U, /*!< P0_LIN_CLK */ 1171 0U, /*!< P0_NANO_CLK */ 1172 0U, /*!< P0_PSI5_125K_CLK */ 1173 0U, /*!< P0_PSI5_189K_CLK */ 1174 0U, /*!< P0_PSI5_S_BAUD_CLK */ 1175 0U, /*!< P0_PSI5_S_CORE_CLK */ 1176 0U, /*!< P0_PSI5_S_TRIG0_CLK */ 1177 0U, /*!< P0_PSI5_S_TRIG1_CLK */ 1178 0U, /*!< P0_PSI5_S_TRIG2_CLK */ 1179 0U, /*!< P0_PSI5_S_TRIG3_CLK */ 1180 0U, /*!< P0_PSI5_S_UART_CLK */ 1181 0U, /*!< P0_PSI5_S_WDOG0_CLK */ 1182 0U, /*!< P0_PSI5_S_WDOG1_CLK */ 1183 0U, /*!< P0_PSI5_S_WDOG2_CLK */ 1184 0U, /*!< P0_PSI5_S_WDOG3_CLK */ 1185 0U, /*!< P0_REG_INTF_2X_CLK */ 1186 0U, /*!< P0_REG_INTF_CLK */ 1187 0U, /*!< P1_CLKOUT_SRC_CLK */ 1188 0U, /*!< P1_DSPI60_CLK */ 1189 0U, /*!< ETH_TS_CLK */ 1190 0U, /*!< ETH_TS_DIV4_CLK */ 1191 0U, /*!< ETH0_REF_RMII_CLK */ 1192 0U, /*!< ETH0_RX_MII_CLK */ 1193 0U, /*!< ETH0_RX_RGMII_CLK */ 1194 0U, /*!< ETH0_TX_RGMII_CLK */ 1195 0U, /*!< ETH0_TX_RGMII_LPBK_CLK */ 1196 0U, /*!< ETH1_REF_RMII_CLK */ 1197 0U, /*!< ETH1_RX_MII_CLK */ 1198 0U, /*!< ETH1_RX_RGMII_CLK */ 1199 0U, /*!< ETH1_TX_MII_CLK */ 1200 0U, /*!< ETH1_TX_RGMII_CLK */ 1201 0U, /*!< ETH1_TX_RGMII_LPBK_CLK */ 1202 0U, /*!< P1_LFAST0_REF_CLK */ 1203 0U, /*!< P1_LFAST1_REF_CLK */ 1204 0U, /*!< P1_LFAST_DFT_CLK */ 1205 0U, /*!< P1_NETC_AXI_CLK */ 1206 0U, /*!< P1_LIN_CLK */ 1207 0U, /*!< P1_REG_INTF_CLK */ 1208 0U, /*!< P2_DBG_ATB_CLK */ 1209 0U, /*!< P2_REG_INTF_CLK */ 1210 0U, /*!< P3_AES_CLK */ 1211 0U, /*!< P3_CLKOUT_SRC_CLK */ 1212 0U, /*!< P3_DBG_TS_CLK */ 1213 0U, /*!< P3_REG_INTF_CLK */ 1214 0U, /*!< P3_SYS_MON1_CLK */ 1215 0U, /*!< P3_SYS_MON2_CLK */ 1216 0U, /*!< P3_SYS_MON3_CLK */ 1217 0U, /*!< P4_CLKOUT_SRC_CLK */ 1218 0U, /*!< P4_DSPI60_CLK */ 1219 0U, /*!< P4_EMIOS_LCU_CLK */ 1220 0U, /*!< P4_LIN_CLK */ 1221 0U, /*!< P4_PSI5_125K_CLK */ 1222 0U, /*!< P4_PSI5_189K_CLK */ 1223 0U, /*!< P4_PSI5_S_BAUD_CLK */ 1224 0U, /*!< P4_PSI5_S_CORE_CLK */ 1225 0U, /*!< P4_PSI5_S_TRIG0_CLK */ 1226 0U, /*!< P4_PSI5_S_TRIG1_CLK */ 1227 0U, /*!< P4_PSI5_S_TRIG2_CLK */ 1228 0U, /*!< P4_PSI5_S_TRIG3_CLK */ 1229 0U, /*!< P4_PSI5_S_UART_CLK */ 1230 0U, /*!< P4_PSI5_S_WDOG0_CLK */ 1231 0U, /*!< P4_PSI5_S_WDOG1_CLK */ 1232 0U, /*!< P4_PSI5_S_WDOG2_CLK */ 1233 0U, /*!< P4_PSI5_S_WDOG3_CLK */ 1234 0U, /*!< P4_QSPI0_2X_CLK */ 1235 0U, /*!< P4_QSPI0_1X_CLK */ 1236 0U, /*!< P4_QSPI1_2X_CLK */ 1237 0U, /*!< P4_QSPI1_1X_CLK */ 1238 0U, /*!< P4_REG_INTF_2X_CLK */ 1239 0U, /*!< P4_REG_INTF_CLK */ 1240 0U, /*!< P4_SDHC_IP_CLK */ 1241 0U, /*!< P4_SDHC_IP_DIV2_CLK */ 1242 0U, /*!< P5_DIPORT_CLK */ 1243 0U, /*!< P5_AE_CLK */ 1244 0U, /*!< P5_CANXL_PE_CLK */ 1245 0U, /*!< P5_CANXL_CHI_CLK */ 1246 0U, /*!< P5_CLKOUT_SRC_CLK */ 1247 0U, /*!< P5_LIN_CLK */ 1248 0U, /*!< P5_REG_INTF_CLK */ 1249 0U, /*!< P6_REG_INTF_CLK */ 1250 0U, /*!< PIT0_CLK */ 1251 0U, /*!< PIT1_CLK */ 1252 0U, /*!< PIT4_CLK */ 1253 0U, /*!< PIT5_CLK */ 1254 0U, /*!< P0_PSI5_1US_CLK */ 1255 0U, /*!< PSI5_0_CLK */ 1256 0U, /*!< P4_PSI5_1US_CLK */ 1257 0U, /*!< PSI5_1_CLK */ 1258 0U, /*!< PSI5S_0_CLK */ 1259 0U, /*!< PSI5S_1_CLK */ 1260 0U, /*!< QSPI0_CLK */ 1261 0U, /*!< QSPI1_CLK */ 1262 0U, /*!< RTU0_CORE_MON1_CLK */ 1263 0U, /*!< RTU0_CORE_MON2_CLK */ 1264 0U, /*!< RTU0_CORE_DIV2_MON1_CLK */ 1265 0U, /*!< RTU0_CORE_DIV2_MON2_CLK */ 1266 0U, /*!< RTU0_CORE_DIV2_MON3_CLK */ 1267 0U, /*!< RTU0_REG_INTF_CLK */ 1268 0U, /*!< RTU1_CORE_MON1_CLK */ 1269 0U, /*!< RTU1_CORE_MON2_CLK */ 1270 0U, /*!< RTU1_CORE_DIV2_MON1_CLK */ 1271 0U, /*!< RTU1_CORE_DIV2_MON2_CLK */ 1272 0U, /*!< RTU1_CORE_DIV2_MON3_CLK */ 1273 0U, /*!< RTU1_REG_INTF_CLK */ 1274 0U, /*!< P4_SDHC_CLK */ 1275 0U, /*!< RXLUT_CLK */ 1276 0U, /*!< SDHC0_CLK */ 1277 0U, /*!< SINC_CLK */ 1278 0U, /*!< SIPI0_CLK */ 1279 0U, /*!< SIPI1_CLK */ 1280 0U, /*!< SIUL2_0_CLK */ 1281 0U, /*!< SIUL2_1_CLK */ 1282 0U, /*!< SIUL2_4_CLK */ 1283 0U, /*!< SIUL2_5_CLK */ 1284 0U, /*!< P0_DSPI_CLK */ 1285 0U, /*!< SPI0_CLK */ 1286 0U, /*!< SPI1_CLK */ 1287 0U, /*!< P1_DSPI_CLK */ 1288 0U, /*!< SPI2_CLK */ 1289 0U, /*!< SPI3_CLK */ 1290 0U, /*!< SPI4_CLK */ 1291 0U, /*!< P4_DSPI_CLK */ 1292 0U, /*!< SPI5_CLK */ 1293 0U, /*!< SPI6_CLK */ 1294 0U, /*!< SPI7_CLK */ 1295 0U, /*!< P5_DSPI_CLK */ 1296 0U, /*!< SPI8_CLK */ 1297 0U, /*!< SPI9_CLK */ 1298 0U, /*!< SRX0_CLK */ 1299 0U, /*!< SRX1_CLK */ 1300 0U, /*!< CORE_PLL_REFCLKOUT clock */ 1301 0U, /*!< CORE_PLL_FBCLKOUT clock */ 1302 0U, /*!< PERIPH_PLL_REFCLKOUT clock */ 1303 0U, /*!< PERIPH_PLL_FBCLKOUT clock */ 1304 }; 1305 1306 1307 /* Clock stop constant section data */ 1308 #define MCU_STOP_SEC_CONST_8 1309 #include "Mcu_MemMap.h" 1310 1311 1312 1313 1314 /* Clock start constant section data */ 1315 #define MCU_START_SEC_CONST_16 1316 #include "Mcu_MemMap.h" 1317 /*! 1318 * @brief Converts a clock name to a selector entry hardware value 1319 */ 1320 const uint16 Clock_Ip_au16SelectorEntryHardwareValue[CLOCK_IP_NAMES_NO] = { 1321 0U, /*!< CLOCK_IS_OFF */ 1322 0U, /*!< FIRC_CLK */ 1323 2U, /*!< FXOSC_CLK */ 1324 1U, /*!< SIRC_CLK */ 1325 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 1326 0U, /*!< FIRC_AE_CLK */ 1327 #endif 1328 0U, /*!< COREPLL_CLK */ 1329 0U, /*!< PERIPHPLL_CLK */ 1330 0U, /*!< DDRPLL_CLK */ 1331 0U, /*!< LFAST0_PLL_CLK */ 1332 0U, /*!< LFAST1_PLL_CLK */ 1333 10U, /*!< CORE_PLL_PHI0_CLK */ 1334 11U, /*!< CORE_PLL_DFS0_CLK */ 1335 12U, /*!< CORE_PLL_DFS1_CLK */ 1336 13U, /*!< CORE_PLL_DFS2_CLK */ 1337 14U, /*!< CORE_PLL_DFS3_CLK */ 1338 15U, /*!< CORE_PLL_DFS4_CLK */ 1339 16U, /*!< CORE_PLL_DFS5_CLK */ 1340 20U, /*!< PERIPH_PLL_PHI0_CLK */ 1341 21U, /*!< PERIPH_PLL_PHI1_CLK */ 1342 22U, /*!< PERIPH_PLL_PHI2_CLK */ 1343 23U, /*!< PERIPH_PLL_PHI3_CLK */ 1344 24U, /*!< PERIPH_PLL_PHI4_CLK */ 1345 25U, /*!< PERIPH_PLL_PHI5_CLK */ 1346 26U, /*!< PERIPH_PLL_PHI6_CLK */ 1347 30U, /*!< PERIPH_PLL_DFS0_CLK */ 1348 31U, /*!< PERIPH_PLL_DFS1_CLK */ 1349 32U, /*!< PERIPH_PLL_DFS2_CLK */ 1350 33U, /*!< PERIPH_PLL_DFS3_CLK */ 1351 34U, /*!< PERIPH_PLL_DFS4_CLK */ 1352 35U, /*!< PERIPH_PLL_DFS5_CLK */ 1353 40U, /*!< DDR_PLL_PHI0_CLK */ 1354 0U, /*!< LFAST0_PLL_PH0_CLK */ 1355 0U, /*!< LFAST1_PLL_PH0_CLK */ 1356 47U, /*!< ENET_EXT_REF_CLK */ 1357 48U, /*!< ENET_EXT_TS_CLK */ 1358 49U, /*!< ENET0_EXT_RX_CLK */ 1359 50U, /*!< ENET0_EXT_TX_CLK */ 1360 51U, /*!< ENET1_EXT_RX_CLK */ 1361 52U, /*!< ENET1_EXT_TX_CLK */ 1362 59U, /*!< LFAST0_EXT_TX_CLK */ 1363 60U, /*!< LFAST1_EXT_TX_CLK */ 1364 0U, /*!< DDR_CLK */ 1365 0U, /*!< P0_SYS_CLK */ 1366 0U, /*!< P1_SYS_CLK */ 1367 0U, /*!< P1_SYS_DIV2_CLK */ 1368 0U, /*!< P1_SYS_DIV4_CLK */ 1369 0U, /*!< P2_SYS_CLK */ 1370 0U, /*!< CORE_M33_CLK */ 1371 0U, /*!< P2_SYS_DIV2_CLK */ 1372 0U, /*!< P2_SYS_DIV4_CLK */ 1373 0U, /*!< P3_SYS_CLK */ 1374 0U, /*!< CE_SYS_DIV2_CLK */ 1375 0U, /*!< CE_SYS_DIV4_CLK */ 1376 0U, /*!< P3_SYS_DIV2_NOC_CLK */ 1377 0U, /*!< P3_SYS_DIV4_CLK */ 1378 0U, /*!< P4_SYS_CLK */ 1379 0U, /*!< P4_SYS_DIV2_CLK */ 1380 0U, /*!< HSE_SYS_DIV2_CLK */ 1381 0U, /*!< P5_SYS_CLK */ 1382 0U, /*!< P5_SYS_DIV2_CLK */ 1383 0U, /*!< P5_SYS_DIV4_CLK */ 1384 0U, /*!< P2_MATH_CLK */ 1385 0U, /*!< P2_MATH_DIV3_CLK */ 1386 0U, /*!< GLB_LBIST_CLK */ 1387 0U, /*!< RTU0_CORE_CLK */ 1388 0U, /*!< RTU0_CORE_DIV2_CLK */ 1389 0U, /*!< RTU1_CORE_CLK */ 1390 0U, /*!< RTU1_CORE_DIV2_CLK */ 1391 62U, /*!< P0_PSI5_S_UTIL_CLK */ 1392 62U, /*!< P4_PSI5_S_UTIL_CLK */ 1393 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 1394 0U, /*!< SYSTEM_DRUN_CLK */ 1395 #endif 1396 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 1397 0U, /*!< SYSTEM_RUN0_CLK */ 1398 #endif 1399 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 1400 0U, /*!< SYSTEM_SAFE_CLK */ 1401 #endif 1402 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 1403 0U, /*!< SYSTEM_CLK */ 1404 #endif 1405 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 1406 0U, /*!< SYSTEM_DIV2_CL */ 1407 #endif 1408 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 1409 0U, /*!< SYSTEM_DIV4_CLK */ 1410 #endif 1411 0U, /*!< THE_LAST_PRODUCER_CLK */ 1412 0U, /*!< ADC0_CLK clock */ 1413 0U, /*!< ADC1_CLK clock */ 1414 0U, /*!< CE_EDMA_CLK clock */ 1415 0U, /*!< CE_PIT0_CLK clock */ 1416 0U, /*!< CE_PIT1_CLK clock */ 1417 0U, /*!< CE_PIT2_CLK clock */ 1418 0U, /*!< CE_PIT3_CLK clock */ 1419 0U, /*!< CE_PIT4_CLK clock */ 1420 0U, /*!< CE_PIT5_CLK clock */ 1421 0U, /*!< CLKOUT0_CLK clock */ 1422 0U, /*!< CLKOUT1_CLK clock */ 1423 0U, /*!< CLKOUT2_CLK clock */ 1424 0U, /*!< CLKOUT3_CLK clock */ 1425 0U, /*!< CLKOUT4_CLK clock */ 1426 0U, /*!< CTU_CLK clock */ 1427 0U, /*!< DMACRC0_CLK clock */ 1428 0U, /*!< DMACRC1_CLK clock */ 1429 0U, /*!< DMACRC4_CLK clock */ 1430 0U, /*!< DMACRC5_CLK clock */ 1431 0U, /*!< DMAMUX0_CLK clock */ 1432 0U, /*!< DMAMUX1_CLK clock */ 1433 0U, /*!< DMAMUX4_CLK clock */ 1434 0U, /*!< DMAMUX5_CLK clock */ 1435 0U, /*!< EDMA0_CLK clock */ 1436 0U, /*!< EDMA1_CLK clock */ 1437 0U, /*!< EDMA3_CLK clock */ 1438 0U, /*!< EDMA4_CLK clock */ 1439 0U, /*!< EDMA5_CLK clock */ 1440 0U, /*!< ETH0_TX_MII_CLK clock */ 1441 0U, /*!< ENET0_CLK clock */ 1442 0U, /*!< P3_CAN_PE_CLK clock */ 1443 0U, /*!< FLEXCAN0_CLK clock */ 1444 0U, /*!< FLEXCAN1_CLK clock */ 1445 0U, /*!< FLEXCAN2_CLK clock */ 1446 0U, /*!< FLEXCAN3_CLK clock */ 1447 0U, /*!< FLEXCAN4_CLK clock */ 1448 0U, /*!< FLEXCAN5_CLK clock */ 1449 0U, /*!< FLEXCAN6_CLK clock */ 1450 0U, /*!< FLEXCAN7_CLK clock */ 1451 0U, /*!< FLEXCAN8_CLK clock */ 1452 0U, /*!< FLEXCAN9_CLK clock */ 1453 0U, /*!< FLEXCAN10_CLK clock */ 1454 0U, /*!< FLEXCAN11_CLK clock */ 1455 0U, /*!< FLEXCAN12_CLK clock */ 1456 0U, /*!< FLEXCAN13_CLK clock */ 1457 0U, /*!< FLEXCAN14_CLK clock */ 1458 0U, /*!< FLEXCAN15_CLK clock */ 1459 0U, /*!< FLEXCAN16_CLK clock */ 1460 0U, /*!< FLEXCAN17_CLK clock */ 1461 0U, /*!< FLEXCAN18_CLK clock */ 1462 0U, /*!< FLEXCAN19_CLK clock */ 1463 0U, /*!< FLEXCAN20_CLK clock */ 1464 0U, /*!< FLEXCAN21_CLK clock */ 1465 0U, /*!< FLEXCAN22_CLK clock */ 1466 0U, /*!< FLEXCAN23_CLK clock */ 1467 0U, /*!< P0_FR_PE_CLK clock */ 1468 0U, /*!< FRAY0_CLK clock */ 1469 0U, /*!< FRAY1_CLK clock */ 1470 0U, /*!< GTM_CLK clock */ 1471 0U, /*!< IIIC0_CLK clock */ 1472 0U, /*!< IIIC1_CLK clock */ 1473 0U, /*!< IIIC2_CLK clock */ 1474 0U, /*!< P0_LIN_BAUD_CLK clock */ 1475 0U, /*!< LIN0_CLK clock */ 1476 0U, /*!< LIN1_CLK clock */ 1477 0U, /*!< LIN2_CLK clock */ 1478 0U, /*!< P1_LIN_BAUD_CLK clock */ 1479 0U, /*!< LIN3_CLK clock */ 1480 0U, /*!< LIN4_CLK clock */ 1481 0U, /*!< LIN5_CLK clock */ 1482 0U, /*!< P4_LIN_BAUD_CLK clock */ 1483 0U, /*!< LIN6_CLK clock */ 1484 0U, /*!< LIN7_CLK clock */ 1485 0U, /*!< LIN8_CLK clock */ 1486 0U, /*!< P5_LIN_BAUD_CLK clock */ 1487 0U, /*!< LIN9_CLK clock */ 1488 0U, /*!< LIN10_CLK clock */ 1489 0U, /*!< LIN11_CLK clock */ 1490 0U, /*!< MSCDSPI_CLK clock */ 1491 0U, /*!< MSCLIN_CLK clock */ 1492 0U, /*!< NANO_CLK clock */ 1493 61U, /*!< P0_CLKOUT_SRC_CLK clock */ 1494 0U, /*!< P0_CTU_PER_CLK clock */ 1495 0U, /*!< P0_DSPI_MSC_CLK clock */ 1496 0U, /*!< P0_EMIOS_LCU_CLK clock */ 1497 0U, /*!< P0_GTM_CLK clock */ 1498 0U, /*!< P0_GTM_NOC_CLK clock */ 1499 0U, /*!< P0_GTM_TS_CLK clock */ 1500 0U, /*!< P0_LIN_CLK clock */ 1501 0U, /*!< P0_NANO_CLK clock */ 1502 0U, /*!< P0_PSI5_125K_CLK clock */ 1503 0U, /*!< P0_PSI5_189K_CLK clock */ 1504 0U, /*!< P0_PSI5_S_BAUD_CLK clock */ 1505 0U, /*!< P0_PSI5_S_CORE_CLK clock */ 1506 0U, /*!< P0_PSI5_S_TRIG0_CLK clock */ 1507 0U, /*!< P0_PSI5_S_TRIG1_CLK clock */ 1508 0U, /*!< P0_PSI5_S_TRIG2_CLK clock */ 1509 0U, /*!< P0_PSI5_S_TRIG3_CLK clock */ 1510 0U, /*!< P0_PSI5_S_UART_CLK clock */ 1511 0U, /*!< P0_PSI5_S_WDOG0_CLK clock */ 1512 0U, /*!< P0_PSI5_S_WDOG1_CLK clock */ 1513 0U, /*!< P0_PSI5_S_WDOG2_CLK clock */ 1514 0U, /*!< P0_PSI5_S_WDOG3_CLK clock */ 1515 0U, /*!< P0_REG_INTF_2X_CLK clock */ 1516 0U, /*!< P0_REG_INTF_CLK clock */ 1517 61U, /*!< P1_CLKOUT_SRC_CLK clock */ 1518 0U, /*!< P1_DSPI60_CLK clock */ 1519 0U, /*!< ETH_TS_CLK clock */ 1520 0U, /*!< ETH_TS_DIV4_CLK clock */ 1521 0U, /*!< ETH0_REF_RMII_CLK clock */ 1522 0U, /*!< ETH0_RX_MII_CLK clock */ 1523 0U, /*!< ETH0_RX_RGMII_CLK clock */ 1524 0U, /*!< ETH0_TX_RGMII_CLK clock */ 1525 0U, /*!< ETH0_TX_RGMII_LPBK_CLK */ 1526 0U, /*!< ETH1_REF_RMII_CLK clock */ 1527 0U, /*!< ETH1_RX_MII_CLK clock */ 1528 0U, /*!< ETH1_RX_RGMII_CLK clock */ 1529 0U, /*!< ETH1_TX_MII_CLK clock */ 1530 0U, /*!< ETH1_TX_RGMII_CLK clock */ 1531 0U, /*!< ETH1_TX_RGMII_LPBK_CLK */ 1532 0U, /*!< P1_LFAST0_REF_CLK clock */ 1533 0U, /*!< P1_LFAST1_REF_CLK clock */ 1534 0U, /*!< P1_LFAST_DFT_CLK clock */ 1535 0U, /*!< P1_NETC_AXI_CLK clock */ 1536 0U, /*!< P1_LIN_CLK clock */ 1537 0U, /*!< P1_REG_INTF_CLK clock */ 1538 0U, /*!< P2_DBG_ATB_CLK clock */ 1539 0U, /*!< P2_REG_INTF_CLK clock */ 1540 0U, /*!< P3_AES_CLK clock */ 1541 61U, /*!< P3_CLKOUT_SRC_CLK clock */ 1542 0U, /*!< P3_DBG_TS_CLK clock */ 1543 0U, /*!< P3_REG_INTF_CLK clock */ 1544 0U, /*!< P3_SYS_MON1_CLK clock */ 1545 0U, /*!< P3_SYS_MON2_CLK clock */ 1546 0U, /*!< P3_SYS_MON3_CLK clock */ 1547 61U, /*!< P4_CLKOUT_SRC_CLK clock */ 1548 0U, /*!< P4_DSPI60_CLK clock */ 1549 0U, /*!< P4_EMIOS_LCU_CLK clock */ 1550 0U, /*!< P4_LIN_CLK clock */ 1551 0U, /*!< P4_PSI5_125K_CLK clock */ 1552 0U, /*!< P4_PSI5_189K_CLK clock */ 1553 0U, /*!< P4_PSI5_S_BAUD_CLK clock */ 1554 0U, /*!< P4_PSI5_S_CORE_CLK clock */ 1555 0U, /*!< P4_PSI5_S_TRIG0_CLK clock */ 1556 0U, /*!< P4_PSI5_S_TRIG1_CLK clock */ 1557 0U, /*!< P4_PSI5_S_TRIG2_CLK clock */ 1558 0U, /*!< P4_PSI5_S_TRIG3_CLK clock */ 1559 0U, /*!< P4_PSI5_S_UART_CLK clock */ 1560 0U, /*!< P4_PSI5_S_WDOG0_CLK clock */ 1561 0U, /*!< P4_PSI5_S_WDOG1_CLK clock */ 1562 0U, /*!< P4_PSI5_S_WDOG2_CLK clock */ 1563 0U, /*!< P4_PSI5_S_WDOG3_CLK clock */ 1564 0U, /*!< P4_QSPI0_2X_CLK clock */ 1565 0U, /*!< P4_QSPI0_1X_CLK clock */ 1566 0U, /*!< P4_QSPI1_2X_CLK clock */ 1567 0U, /*!< P4_QSPI1_1X_CLK clock */ 1568 0U, /*!< P4_REG_INTF_2X_CLK clock */ 1569 0U, /*!< P4_REG_INTF_CLK clock */ 1570 0U, /*!< P4_SDHC_IP_CLK clock */ 1571 0U, /*!< P4_SDHC_IP_DIV2_CLK clock */ 1572 0U, /*!< P5_DIPORT_CLK clock */ 1573 0U, /*!< P5_AE_CLK clock */ 1574 0U, /*!< P5_CANXL_PE_CLK clock */ 1575 0U, /*!< P5_CANXL_CHI_CLK clock */ 1576 61U, /*!< P5_CLKOUT_SRC_CLK clock */ 1577 0U, /*!< P5_LIN_CLK clock */ 1578 0U, /*!< P5_REG_INTF_CLK clock */ 1579 0U, /*!< P6_REG_INTF_CLK clock */ 1580 0U, /*!< PIT0_CLK clock */ 1581 0U, /*!< PIT1_CLK clock */ 1582 0U, /*!< PIT4_CLK clock */ 1583 0U, /*!< PIT5_CLK clock */ 1584 0U, /*!< P0_PSI5_1US_CLK clock */ 1585 0U, /*!< PSI5_0_CLK clock */ 1586 0U, /*!< P4_PSI5_1US_CLK clock */ 1587 0U, /*!< PSI5_1_CLK clock */ 1588 0U, /*!< PSI5S_0_CLK clock */ 1589 0U, /*!< PSI5S_1_CLK clock */ 1590 0U, /*!< QSPI0_CLK clock */ 1591 0U, /*!< QSPI1_CLK clock */ 1592 0U, /*!< RTU0_CORE_MON1_CLK */ 1593 0U, /*!< RTU0_CORE_MON2_CLK */ 1594 0U, /*!< RTU0_CORE_DIV2_MON1_CLK */ 1595 0U, /*!< RTU0_CORE_DIV2_MON2_CLK */ 1596 0U, /*!< RTU0_CORE_DIV2_MON3_CLK */ 1597 0U, /*!< RTU0_CORE_DIV2_MON4_CLK */ 1598 0U, /*!< RTU0_REG_INTF_CLK clock */ 1599 0U, /*!< RTU1_CORE_DIV2_MON1_CLK */ 1600 0U, /*!< RTU1_CORE_DIV2_MON2_CLK */ 1601 0U, /*!< RTU1_CORE_DIV2_MON3_CLK */ 1602 0U, /*!< RTU1_CORE_DIV2_MON4_CLK */ 1603 0U, /*!< RTU1_REG_INTF_CLK clock */ 1604 0U, /*!< P4_SDHC_CLK clock */ 1605 0U, /*!< RXLUT_CLK clock */ 1606 0U, /*!< SDHC0_CLK clock */ 1607 0U, /*!< SINC_CLK clock */ 1608 0U, /*!< SIPI0_CLK clock */ 1609 0U, /*!< SIPI1_CLK clock */ 1610 0U, /*!< SIUL2_0_CLK clock */ 1611 0U, /*!< SIUL2_1_CLK clock */ 1612 0U, /*!< SIUL2_4_CLK clock */ 1613 0U, /*!< SIUL2_5_CLK clock */ 1614 0U, /*!< P0_DSPI_CLK clock */ 1615 0U, /*!< SPI0_CLK clock */ 1616 0U, /*!< SPI1_CLK clock */ 1617 0U, /*!< P1_DSPI_CLK clock */ 1618 0U, /*!< SPI2_CLK clock */ 1619 0U, /*!< SPI3_CLK clock */ 1620 0U, /*!< SPI4_CLK clock */ 1621 0U, /*!< P4_DSPI_CLK clock */ 1622 0U, /*!< SPI5_CLK clock */ 1623 0U, /*!< SPI6_CLK clock */ 1624 0U, /*!< SPI7_CLK clock */ 1625 0U, /*!< P5_DSPI_CLK clock */ 1626 0U, /*!< SPI8_CLK clock */ 1627 0U, /*!< SPI9_CLK clock */ 1628 0U, /*!< SRX0_CLK clock */ 1629 0U, /*!< SRX1_CLK clock */ 1630 0U, /*!< CORE_PLL_REFCLKOUT clock */ 1631 0U, /*!< CORE_PLL_FBCLKOUT clock */ 1632 0U, /*!< PERIPH_PLL_REFCLKOUT clock */ 1633 0U, /*!< PERIPH_PLL_FBCLKOUT clock */ 1634 }; 1635 1636 /*! 1637 * @brief Converts a clock name to a selector entry clkout hardware value 1638 */ 1639 const uint16 Clock_Ip_au16SelectorEntryClkoutHardwareValue[CLOCK_IP_NAMES_NO] = { 1640 0U, /*!< CLOCK_IS_OFF */ 1641 1U, /*!< FIRC_CLK */ 1642 2U, /*!< FXOSC_CLK */ 1643 0U, /*!< SIRC_CLK */ 1644 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 1645 0U, /*!< FIRC_AE_CLK */ 1646 #endif 1647 0U, /*!< COREPLL_CLK */ 1648 0U, /*!< PERIPHPLL_CLK */ 1649 0U, /*!< DDRPLL_CLK */ 1650 0U, /*!< LFAST0_PLL_CLK */ 1651 0U, /*!< LFAST1_PLL_CLK */ 1652 3U, /*!< COREPLL_PHI0_CLK */ 1653 4U, /*!< COREPLL_DFS0_CLK */ 1654 5U, /*!< COREPLL_DFS1_CLK */ 1655 6U, /*!< COREPLL_DFS2_CLK */ 1656 7U, /*!< COREPLL_DFS3_CLK */ 1657 8U, /*!< COREPLL_DFS4_CLK */ 1658 9U, /*!< COREPLL_DFS5_CLK */ 1659 10U, /*!< PERIPHPLL_PHI0_CLK */ 1660 11U, /*!< PERIPHPLL_PHI1_CLK */ 1661 12U, /*!< PERIPHPLL_PHI2_CLK */ 1662 13U, /*!< PERIPHPLL_PHI3_CLK */ 1663 14U, /*!< PERIPHPLL_PHI4_CLK */ 1664 15U, /*!< PERIPHPLL_PHI5_CLK */ 1665 16U, /*!< PERIPHPLL_PHI6_CLK */ 1666 17U, /*!< PERIPHPLL_DFS0_CLK */ 1667 18U, /*!< PERIPHPLL_DFS1_CLK */ 1668 19U, /*!< PERIPHPLL_DFS2_CLK */ 1669 20U, /*!< PERIPHPLL_DFS3_CLK */ 1670 21U, /*!< PERIPHPLL_DFS4_CLK */ 1671 22U, /*!< PERIPHPLL_DFS5_CLK */ 1672 23U, /*!< DDRPLL_PHI0_CLK */ 1673 0U, /*!< LFAST0_PLL_PH0_CLK */ 1674 1U, /*!< LFAST1_PLL_PH0_CLK */ 1675 0U, /*!< ETH_RGMII_REF_CLK */ 1676 0U, /*!< ETH_EXT_TS_CLK */ 1677 0U, /*!< ETH0_EXT_RX_CLK */ 1678 0U, /*!< ETH0_EXT_TX_CLK */ 1679 0U, /*!< ETH1_EXT_RX_CLK */ 1680 0U, /*!< ETH1_EXT_TX_CLK */ 1681 0U, /*!< LFAST0_EXT_REF_CLK */ 1682 0U, /*!< LFAST1_EXT_REF_CLK */ 1683 9U, /*!< DDR_CLK */ 1684 24U, /*!< P0_SYS_CLK */ 1685 2U, /*!< P1_SYS_CLK */ 1686 3U, /*!< P1_SYS_DIV2_CLK */ 1687 4U, /*!< P1_SYS_DIV4_CLK */ 1688 6U, /*!< P2_SYS_CLK */ 1689 0U, /*!< CORE_M33_CLK */ 1690 0U, /*!< P2_SYS_DIV2_CLK */ 1691 0U, /*!< P2_SYS_DIV4_CLK */ 1692 0U, /*!< P3_SYS_CLK */ 1693 1U, /*!< CE_SYS_DIV2_CLK */ 1694 2U, /*!< CE_SYS_DIV4_CLK */ 1695 10U, /*!< P3_SYS_DIV2_NOC_CLK */ 1696 0U, /*!< P3_SYS_DIV4_CLK */ 1697 0U, /*!< P4_SYS_CLK */ 1698 1U, /*!< P4_SYS_DIV2_CLK */ 1699 2U, /*!< HSE_SYS_DIV2_CLK */ 1700 0U, /*!< P5_SYS_CLK */ 1701 1U, /*!< P5_SYS_DIV2_CLK */ 1702 2U, /*!< P5_SYS_DIV4_CLK */ 1703 0U, /*!< P2_MATH_CLK */ 1704 0U, /*!< P2_MATH_DIV3_CLK */ 1705 0U, /*!< GLB_LBIST_CLK */ 1706 0U, /*!< RTU0_CORE_CLK */ 1707 7U, /*!< RTU0_CORE_DIV2_CLK */ 1708 0U, /*!< RTU1_CORE_CLK */ 1709 8U, /*!< RTU1_CORE_DIV2_CLK */ 1710 30U, /*!< P0_PSI5_S_UTIL_CLK */ 1711 8U, /*!< P4_PSI5_S_UTIL_CLK */ 1712 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 1713 0U, /*!< SYSTEM_DRUN_CLK */ 1714 #endif 1715 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 1716 0U, /*!< SYSTEM_CLK */ 1717 #endif 1718 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 1719 0U, /*!< SYSTEM_DIV2_CLK */ 1720 #endif 1721 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 1722 0U, /*!< SYSTEM_DIV4_CLK */ 1723 #endif 1724 0U, /*!< THE_LAST_PRODUCER_CLK */ 1725 0U, /*!< ADC0_CLK */ 1726 0U, /*!< ADC1_CLK */ 1727 0U, /*!< CE_EDMA_CLK */ 1728 0U, /*!< CE_PIT0_CLK */ 1729 0U, /*!< CE_PIT1_CLK */ 1730 0U, /*!< CE_PIT2_CLK */ 1731 0U, /*!< CE_PIT3_CLK */ 1732 0U, /*!< CE_PIT4_CLK */ 1733 0U, /*!< CE_PIT5_CLK */ 1734 0U, /*!< CLKOUT0_CLK */ 1735 0U, /*!< CLKOUT1_CLK */ 1736 0U, /*!< CLKOUT2_CLK */ 1737 0U, /*!< CLKOUT3_CLK */ 1738 0U, /*!< CLKOUT4_CLK */ 1739 0U, /*!< CTU_CLK */ 1740 0U, /*!< DMACRC0_CLK */ 1741 0U, /*!< DMACRC1_CLK */ 1742 0U, /*!< DMACRC4_CLK */ 1743 0U, /*!< DMACRC5_CLK */ 1744 0U, /*!< DMAMUX0_CLK */ 1745 0U, /*!< DMAMUX1_CLK */ 1746 0U, /*!< DMAMUX4_CLK */ 1747 0U, /*!< DMAMUX5_CLK */ 1748 0U, /*!< EDMA0_CLK */ 1749 0U, /*!< EDMA1_CLK */ 1750 0U, /*!< EDMA3_CLK */ 1751 0U, /*!< EDMA4_CLK */ 1752 0U, /*!< EDMA5_CLK */ 1753 12U, /*!< ETH0_TX_MII_CLK */ 1754 0U, /*!< ENET0_CLK */ 1755 5U, /*!< P3_CAN_PE_CLK */ 1756 0U, /*!< FLEXCAN0_CLK */ 1757 0U, /*!< FLEXCAN1_CLK */ 1758 0U, /*!< FLEXCAN2_CLK */ 1759 0U, /*!< FLEXCAN3_CLK */ 1760 0U, /*!< FLEXCAN4_CLK */ 1761 0U, /*!< FLEXCAN5_CLK */ 1762 0U, /*!< FLEXCAN6_CLK */ 1763 0U, /*!< FLEXCAN7_CLK */ 1764 0U, /*!< FLEXCAN8_CLK */ 1765 0U, /*!< FLEXCAN9_CLK */ 1766 0U, /*!< FLEXCAN10_CLK */ 1767 0U, /*!< FLEXCAN11_CLK */ 1768 0U, /*!< FLEXCAN12_CLK */ 1769 0U, /*!< FLEXCAN13_CLK */ 1770 0U, /*!< FLEXCAN14_CLK */ 1771 0U, /*!< FLEXCAN15_CLK */ 1772 0U, /*!< FLEXCAN16_CLK */ 1773 0U, /*!< FLEXCAN17_CLK */ 1774 0U, /*!< FLEXCAN18_CLK */ 1775 0U, /*!< FLEXCAN19_CLK */ 1776 0U, /*!< FLEXCAN20_CLK */ 1777 0U, /*!< FLEXCAN21_CLK */ 1778 0U, /*!< FLEXCAN22_CLK */ 1779 0U, /*!< FLEXCAN23_CLK */ 1780 37U, /*!< P0_FR_PE_CLK */ 1781 0U, /*!< FRAY0_CLK */ 1782 0U, /*!< FRAY1_CLK */ 1783 0U, /*!< GTM_CLK */ 1784 0U, /*!< IIIC0_CLK */ 1785 0U, /*!< IIIC1_CLK */ 1786 0U, /*!< IIIC2_CLK */ 1787 34U, /*!< P0_LIN_BAUD_CLK */ 1788 0U, /*!< LIN0_CLK */ 1789 0U, /*!< LIN1_CLK */ 1790 0U, /*!< LIN2_CLK */ 1791 8U, /*!< P1_LIN_BAUD_CLK */ 1792 0U, /*!< LIN3_CLK */ 1793 0U, /*!< LIN4_CLK */ 1794 0U, /*!< LIN5_CLK */ 1795 16U, /*!< P4_LIN_BAUD_CLK */ 1796 0U, /*!< LIN6_CLK */ 1797 0U, /*!< LIN7_CLK */ 1798 0U, /*!< LIN8_CLK */ 1799 4U, /*!< P5_LIN_BAUD_CLK */ 1800 0U, /*!< LIN9_CLK */ 1801 0U, /*!< LIN10_CLK */ 1802 0U, /*!< LIN11_CLK */ 1803 0U, /*!< MSCDSPI_CLK */ 1804 0U, /*!< MSCLIN_CLK */ 1805 0U, /*!< NANO_CLK */ 1806 0U, /*!< P0_CLKOUT_SRC_CLK */ 1807 43U, /*!< P0_CTU_PER_CLK */ 1808 42U, /*!< P0_DSPI_MSC_CLK */ 1809 44U, /*!< P0_EMIOS_LCU_CLK */ 1810 39U, /*!< P0_GTM_CLK */ 1811 40U, /*!< P0_GTM_NOC_CLK */ 1812 41U, /*!< P0_GTM_TS_CLK */ 1813 35U, /*!< P0_LIN_CLK */ 1814 38U, /*!< P0_NANO_CLK */ 1815 28U, /*!< P0_PSI5_125K_CLK */ 1816 29U, /*!< P0_PSI5_189K_CLK */ 1817 32U, /*!< P0_PSI5_S_BAUD_CLK */ 1818 33U, /*!< P0_PSI5_S_CORE_CLK */ 1819 0U, /*!< P0_PSI5_S_TRIG0_CLK */ 1820 0U, /*!< P0_PSI5_S_TRIG1_CLK */ 1821 0U, /*!< P0_PSI5_S_TRIG2_CLK */ 1822 0U, /*!< P0_PSI5_S_TRIG3_CLK */ 1823 31U, /*!< P0_PSI5_S_UART_CLK */ 1824 0U, /*!< P0_PSI5_S_WDOG0_CLK */ 1825 0U, /*!< P0_PSI5_S_WDOG1_CLK */ 1826 0U, /*!< P0_PSI5_S_WDOG2_CLK */ 1827 0U, /*!< P0_PSI5_S_WDOG3_CLK */ 1828 26U, /*!< P0_REG_INTF_2X_CLK */ 1829 25U, /*!< P0_REG_INTF_CLK */ 1830 0U, /*!< P1_CLKOUT_SRC_CLK */ 1831 7U, /*!< P1_DSPI60_CLK */ 1832 10U, /*!< ETH_TS_CLK */ 1833 11U, /*!< ETH_TS_DIV4_CLK */ 1834 16U, /*!< ETH0_REF_RMII_CLK */ 1835 14U, /*!< ETH0_RX_MII_CLK */ 1836 15U, /*!< ETH0_RX_RGMII_CLK */ 1837 13U, /*!< ETH0_TX_RGMII_CLK */ 1838 0U, /*!< ETH0_TX_RGMII_LPBK_CLK */ 1839 21U, /*!< ETH1_REF_RMII_CLK */ 1840 19U, /*!< ETH1_RX_MII_CLK */ 1841 20U, /*!< ETH1_RX_RGMII_CLK */ 1842 17U, /*!< ETH1_TX_MII_CLK */ 1843 18U, /*!< ETH1_TX_RGMII_CLK */ 1844 0U, /*!< ETH1_TX_RGMII_LPBK_CLK */ 1845 0U, /*!< P1_LFAST0_REF_CLK */ 1846 0U, /*!< P1_LFAST1_REF_CLK */ 1847 0U, /*!< P1_LFAST_DFT_CLK */ 1848 0U, /*!< P1_NETC_AXI_CLK */ 1849 9U, /*!< P1_LIN_CLK */ 1850 5U, /*!< P1_REG_INTF_CLK */ 1851 0U, /*!< P2_DBG_ATB_CLK */ 1852 0U, /*!< P2_REG_INTF_CLK */ 1853 5U, /*!< P3_AES_CLK */ 1854 0U, /*!< P3_CLKOUT_SRC_CLK */ 1855 4U, /*!< P3_DBG_TS_CLK */ 1856 3U, /*!< P3_REG_INTF_CLK */ 1857 0U, /*!< P3_SYS_MON1_CLK */ 1858 0U, /*!< P3_SYS_MON2_CLK */ 1859 0U, /*!< P3_SYS_MON3_CLK */ 1860 0U, /*!< P4_CLKOUT_SRC_CLK */ 1861 13U, /*!< P4_DSPI60_CLK */ 1862 23U, /*!< P4_EMIOS_LCU_CLK */ 1863 17U, /*!< P4_LIN_CLK */ 1864 6U, /*!< P4_PSI5_125K_CLK */ 1865 7U, /*!< P4_PSI5_189K_CLK */ 1866 10U, /*!< P4_PSI5_S_BAUD_CLK */ 1867 11U, /*!< P4_PSI5_S_CORE_CLK */ 1868 0U, /*!< P4_PSI5_S_TRIG0_CLK */ 1869 0U, /*!< P4_PSI5_S_TRIG1_CLK */ 1870 0U, /*!< P4_PSI5_S_TRIG2_CLK */ 1871 0U, /*!< P4_PSI5_S_TRIG3_CLK */ 1872 9U, /*!< P4_PSI5_S_UART_CLK */ 1873 0U, /*!< P4_PSI5_S_WDOG0_CLK */ 1874 0U, /*!< P4_PSI5_S_WDOG1_CLK */ 1875 0U, /*!< P4_PSI5_S_WDOG2_CLK */ 1876 0U, /*!< P4_PSI5_S_WDOG3_CLK */ 1877 14U, /*!< P4_QSPI0_2X_CLK */ 1878 15U, /*!< P4_QSPI0_1X_CLK */ 1879 19U, /*!< P4_QSPI1_2X_CLK */ 1880 20U, /*!< P4_QSPI1_1X_CLK */ 1881 4U, /*!< P4_REG_INTF_2X_CLK */ 1882 3U, /*!< P4_REG_INTF_CLK */ 1883 21U, /*!< P4_SDHC_IP_CLK */ 1884 22U, /*!< P4_SDHC_IP_DIV2_CLK */ 1885 0U, /*!< P5_DIPORT_CLK */ 1886 0U, /*!< P5_AE_CLK */ 1887 0U, /*!< P5_CANXL_PE_CLK */ 1888 0U, /*!< P5_CANXL_CHI_CLK */ 1889 0U, /*!< P5_CLKOUT_SRC_CLK */ 1890 5U, /*!< P5_LIN_CLK */ 1891 3U, /*!< P5_REG_INTF_CLK */ 1892 0U, /*!< P6_REG_INTF_CLK */ 1893 0U, /*!< PIT0_CLK */ 1894 0U, /*!< PIT1_CLK */ 1895 0U, /*!< PIT4_CLK */ 1896 0U, /*!< PIT5_CLK */ 1897 27U, /*!< P0_PSI5_1US_CLK */ 1898 0U, /*!< PSI5_0_CLK */ 1899 5U, /*!< P4_PSI5_1US_CLK */ 1900 0U, /*!< PSI5_1_CLK */ 1901 0U, /*!< PSI5S_0_CLK */ 1902 0U, /*!< PSI5S_1_CLK */ 1903 0U, /*!< QSPI0_CLK */ 1904 0U, /*!< QSPI1_CLK */ 1905 0U, /*!< RTU0_CORE_MON1_CLK */ 1906 0U, /*!< RTU0_CORE_MON2_CLK */ 1907 0U, /*!< RTU0_CORE_DIV2_MON1_CLK */ 1908 0U, /*!< RTU0_CORE_DIV2_MON2_CLK */ 1909 0U, /*!< RTU0_CORE_DIV2_MON3_CLK */ 1910 0U, /*!< RTU0_REG_INTF_CLK */ 1911 0U, /*!< RTU1_CORE_MON1_CLK */ 1912 0U, /*!< RTU1_CORE_MON2_CLK */ 1913 0U, /*!< RTU1_CORE_DIV2_MON1_CLK */ 1914 0U, /*!< RTU1_CORE_DIV2_MON2_CLK */ 1915 0U, /*!< RTU1_CORE_DIV2_MON3_CLK */ 1916 0U, /*!< RTU1_REG_INTF_CLK */ 1917 18U, /*!< P4_SDHC_CLK */ 1918 0U, /*!< RXLUT_CLK */ 1919 0U, /*!< SDHC0_CLK */ 1920 0U, /*!< SINC_CLK */ 1921 0U, /*!< SIPI0_CLK */ 1922 0U, /*!< SIPI1_CLK */ 1923 0U, /*!< SIUL2_0_CLK */ 1924 0U, /*!< SIUL2_1_CLK */ 1925 0U, /*!< SIUL2_4_CLK */ 1926 0U, /*!< SIUL2_5_CLK */ 1927 36U, /*!< P0_DSPI_CLK */ 1928 0U, /*!< SPI0_CLK */ 1929 0U, /*!< SPI1_CLK */ 1930 6U, /*!< P1_DSPI_CLK */ 1931 0U, /*!< SPI2_CLK */ 1932 0U, /*!< SPI3_CLK */ 1933 0U, /*!< SPI4_CLK */ 1934 12U, /*!< P4_DSPI_CLK */ 1935 0U, /*!< SPI5_CLK */ 1936 0U, /*!< SPI6_CLK */ 1937 0U, /*!< SPI7_CLK */ 1938 6U, /*!< P5_DSPI_CLK */ 1939 0U, /*!< SPI8_CLK */ 1940 0U, /*!< SPI9_CLK */ 1941 0U, /*!< SRX0_CLK */ 1942 0U, /*!< SRX1_CLK */ 1943 45U, /*!< CORE_PLL_REFCLKOUT clock */ 1944 46U, /*!< CORE_PLL_FBCLKOUT clock */ 1945 47U, /*!< PERIPH_PLL_REFCLKOUT clock */ 1946 48U, /*!< PERIPH_PLL_FBCLKOUT clock */ 1947 }; 1948 1949 1950 #ifdef CLOCK_IP_MC_ME_AE_GS_S_SYSCLK 1951 /*! 1952 * @brief Converts a clock name to a AE selector entry hardware value 1953 */ 1954 const uint16 Clock_Ip_au16SelectorEntryAeHardwareValue[CLOCK_IP_FEATURE_NAMES_NO] = { 1955 0U, /*!< CLOCK_IS_OFF */ 1956 0U, /*!< FIRC_CLK */ 1957 0U, /*!< FXOSC_CLK */ 1958 0U, /*!< SIRC_CLK */ 1959 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 1960 0U, /*!< FIRC_AE_CLK */ 1961 #endif 1962 0U, /*!< COREPLL_CLK */ 1963 0U, /*!< PERIPHPLL_CLK */ 1964 0U, /*!< DDRPLL_CLK */ 1965 0U, /*!< LFAST0_PLL_CLK */ 1966 0U, /*!< LFAST1_PLL_CLK */ 1967 0U, /*!< CORE_PLL_PHI0_CLK */ 1968 0U, /*!< CORE_PLL_DFS0_CLK */ 1969 0U, /*!< CORE_PLL_DFS1_CLK */ 1970 0U, /*!< CORE_PLL_DFS2_CLK */ 1971 0U, /*!< CORE_PLL_DFS3_CLK */ 1972 0U, /*!< CORE_PLL_DFS4_CLK */ 1973 0U, /*!< CORE_PLL_DFS5_CLK */ 1974 0U, /*!< PERIPH_PLL_PHI0_CLK */ 1975 0U, /*!< PERIPH_PLL_PHI1_CLK */ 1976 0U, /*!< PERIPH_PLL_PHI2_CLK */ 1977 0U, /*!< PERIPH_PLL_PHI3_CLK */ 1978 0U, /*!< PERIPH_PLL_PHI4_CLK */ 1979 0U, /*!< PERIPH_PLL_PHI5_CLK */ 1980 0U, /*!< PERIPH_PLL_PHI6_CLK */ 1981 0U, /*!< PERIPH_PLL_DFS0_CLK */ 1982 0U, /*!< PERIPH_PLL_DFS1_CLK */ 1983 0U, /*!< PERIPH_PLL_DFS2_CLK */ 1984 0U, /*!< PERIPH_PLL_DFS3_CLK */ 1985 0U, /*!< PERIPH_PLL_DFS4_CLK */ 1986 0U, /*!< PERIPH_PLL_DFS5_CLK */ 1987 0U, /*!< DDR_PLL_PHI0_CLK */ 1988 0U, /*!< LFAST0_PLL_PH0_CLK */ 1989 0U, /*!< LFAST1_PLL_PH0_CLK */ 1990 0U, /*!< ENET_EXT_REF_CLK */ 1991 0U, /*!< ENET_EXT_TS_CLK */ 1992 0U, /*!< ENET0_EXT_RX_CLK */ 1993 0U, /*!< ENET0_EXT_TX_CLK */ 1994 0U, /*!< ENET1_EXT_RX_CLK */ 1995 0U, /*!< ENET1_EXT_TX_CLK */ 1996 0U, /*!< LFAST0_EXT_TX_CLK */ 1997 0U, /*!< LFAST1_EXT_TX_CLK */ 1998 0U, /*!< DDR_CLK */ 1999 0U, /*!< P0_SYS_CLK */ 2000 0U, /*!< P1_SYS_CLK */ 2001 0U, /*!< P1_SYS_DIV2_CLK */ 2002 0U, /*!< P1_SYS_DIV4_CLK */ 2003 0U, /*!< P2_SYS_CLK */ 2004 0U, /*!< CORE_M33_CLK */ 2005 0U, /*!< P2_SYS_DIV2_CLK */ 2006 0U, /*!< P2_SYS_DIV4_CLK */ 2007 0U, /*!< P3_SYS_CLK */ 2008 0U, /*!< CE_SYS_DIV2_CLK */ 2009 0U, /*!< CE_SYS_DIV4_CLK */ 2010 0U, /*!< P3_SYS_DIV2_NOC_CLK */ 2011 0U, /*!< P3_SYS_DIV4_CLK */ 2012 0U, /*!< P4_SYS_CLK */ 2013 0U, /*!< P4_SYS_DIV2_CLK */ 2014 0U, /*!< HSE_SYS_DIV2_CLK */ 2015 0U, /*!< P5_SYS_CLK */ 2016 0U, /*!< P5_SYS_DIV2_CLK */ 2017 0U, /*!< P5_SYS_DIV4_CLK */ 2018 0U, /*!< P2_MATH_CLK */ 2019 0U, /*!< P2_MATH_DIV3_CLK */ 2020 0U, /*!< GLB_LBIST_CLK */ 2021 0U, /*!< RTU0_CORE_CLK */ 2022 0U, /*!< RTU0_CORE_DIV2_CLK */ 2023 0U, /*!< RTU1_CORE_CLK */ 2024 0U, /*!< RTU1_CORE_DIV2_CLK */ 2025 0U, /*!< P0_PSI5_S_UTIL_CLK */ 2026 0U, /*!< P4_PSI5_S_UTIL_CLK */ 2027 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 2028 0U, /*!< SYSTEM_DRUN_CLK */ 2029 #endif 2030 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 2031 0U, /*!< SYSTEM_RUN0_CLK */ 2032 #endif 2033 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 2034 0U, /*!< SYSTEM_SAFE_CLK */ 2035 #endif 2036 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 2037 0U, /*!< SYSTEM_CLK */ 2038 #endif 2039 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2040 0U, /*!< SYSTEM_DIV2_CL */ 2041 #endif 2042 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 2043 0U, /*!< SYSTEM_DIV4_CLK */ 2044 #endif 2045 0U, /*!< THE_LAST_PRODUCER_CLK */ 2046 0U, /*!< ADC0_CLK clock */ 2047 0U, /*!< ADC1_CLK clock */ 2048 0U, /*!< CE_EDMA_CLK clock */ 2049 0U, /*!< CE_PIT0_CLK clock */ 2050 0U, /*!< CE_PIT1_CLK clock */ 2051 0U, /*!< CE_PIT2_CLK clock */ 2052 0U, /*!< CE_PIT3_CLK clock */ 2053 0U, /*!< CE_PIT4_CLK clock */ 2054 0U, /*!< CE_PIT5_CLK clock */ 2055 0U, /*!< CLKOUT0_CLK clock */ 2056 0U, /*!< CLKOUT1_CLK clock */ 2057 0U, /*!< CLKOUT2_CLK clock */ 2058 0U, /*!< CLKOUT3_CLK clock */ 2059 0U, /*!< CLKOUT4_CLK clock */ 2060 0U, /*!< CTU_CLK clock */ 2061 0U, /*!< DMACRC0_CLK clock */ 2062 0U, /*!< DMACRC1_CLK clock */ 2063 0U, /*!< DMACRC4_CLK clock */ 2064 0U, /*!< DMACRC5_CLK clock */ 2065 0U, /*!< DMAMUX0_CLK clock */ 2066 0U, /*!< DMAMUX1_CLK clock */ 2067 0U, /*!< DMAMUX4_CLK clock */ 2068 0U, /*!< DMAMUX5_CLK clock */ 2069 0U, /*!< EDMA0_CLK clock */ 2070 0U, /*!< EDMA1_CLK clock */ 2071 0U, /*!< EDMA3_CLK clock */ 2072 0U, /*!< EDMA4_CLK clock */ 2073 0U, /*!< EDMA5_CLK clock */ 2074 0U, /*!< ETH0_TX_MII_CLK clock */ 2075 0U, /*!< ENET0_CLK clock */ 2076 0U, /*!< P3_CAN_PE_CLK clock */ 2077 0U, /*!< FLEXCAN0_CLK clock */ 2078 0U, /*!< FLEXCAN1_CLK clock */ 2079 0U, /*!< FLEXCAN2_CLK clock */ 2080 0U, /*!< FLEXCAN3_CLK clock */ 2081 0U, /*!< FLEXCAN4_CLK clock */ 2082 0U, /*!< FLEXCAN5_CLK clock */ 2083 0U, /*!< FLEXCAN6_CLK clock */ 2084 0U, /*!< FLEXCAN7_CLK clock */ 2085 0U, /*!< FLEXCAN8_CLK clock */ 2086 0U, /*!< FLEXCAN9_CLK clock */ 2087 0U, /*!< FLEXCAN10_CLK clock */ 2088 0U, /*!< FLEXCAN11_CLK clock */ 2089 0U, /*!< FLEXCAN12_CLK clock */ 2090 0U, /*!< FLEXCAN13_CLK clock */ 2091 0U, /*!< FLEXCAN14_CLK clock */ 2092 0U, /*!< FLEXCAN15_CLK clock */ 2093 0U, /*!< FLEXCAN16_CLK clock */ 2094 0U, /*!< FLEXCAN17_CLK clock */ 2095 0U, /*!< FLEXCAN18_CLK clock */ 2096 0U, /*!< FLEXCAN19_CLK clock */ 2097 0U, /*!< FLEXCAN20_CLK clock */ 2098 0U, /*!< FLEXCAN21_CLK clock */ 2099 0U, /*!< FLEXCAN22_CLK clock */ 2100 0U, /*!< FLEXCAN23_CLK clock */ 2101 0U, /*!< P0_FR_PE_CLK clock */ 2102 0U, /*!< FRAY0_CLK clock */ 2103 0U, /*!< FRAY1_CLK clock */ 2104 0U, /*!< GTM_CLK clock */ 2105 0U, /*!< IIIC0_CLK clock */ 2106 0U, /*!< IIIC1_CLK clock */ 2107 0U, /*!< IIIC2_CLK clock */ 2108 0U, /*!< P0_LIN_BAUD_CLK clock */ 2109 0U, /*!< LIN0_CLK clock */ 2110 0U, /*!< LIN1_CLK clock */ 2111 0U, /*!< LIN2_CLK clock */ 2112 0U, /*!< P1_LIN_BAUD_CLK clock */ 2113 0U, /*!< LIN3_CLK clock */ 2114 0U, /*!< LIN4_CLK clock */ 2115 0U, /*!< LIN5_CLK clock */ 2116 0U, /*!< P4_LIN_BAUD_CLK clock */ 2117 0U, /*!< LIN6_CLK clock */ 2118 0U, /*!< LIN7_CLK clock */ 2119 0U, /*!< LIN8_CLK clock */ 2120 0U, /*!< P5_LIN_BAUD_CLK clock */ 2121 0U, /*!< LIN9_CLK clock */ 2122 0U, /*!< LIN10_CLK clock */ 2123 0U, /*!< LIN11_CLK clock */ 2124 0U, /*!< MSCDSPI_CLK clock */ 2125 0U, /*!< MSCLIN_CLK clock */ 2126 0U, /*!< NANO_CLK clock */ 2127 0U, /*!< P0_CLKOUT_SRC_CLK clock */ 2128 0U, /*!< P0_CTU_PER_CLK clock */ 2129 0U, /*!< P0_DSPI_MSC_CLK clock */ 2130 0U, /*!< P0_EMIOS_LCU_CLK clock */ 2131 0U, /*!< P0_GTM_CLK clock */ 2132 0U, /*!< P0_GTM_NOC_CLK clock */ 2133 0U, /*!< P0_GTM_TS_CLK clock */ 2134 0U, /*!< P0_LIN_CLK clock */ 2135 0U, /*!< P0_NANO_CLK clock */ 2136 0U, /*!< P0_PSI5_125K_CLK clock */ 2137 0U, /*!< P0_PSI5_189K_CLK clock */ 2138 0U, /*!< P0_PSI5_S_BAUD_CLK clock */ 2139 0U, /*!< P0_PSI5_S_CORE_CLK clock */ 2140 0U, /*!< P0_PSI5_S_TRIG0_CLK clock */ 2141 0U, /*!< P0_PSI5_S_TRIG1_CLK clock */ 2142 0U, /*!< P0_PSI5_S_TRIG2_CLK clock */ 2143 0U, /*!< P0_PSI5_S_TRIG3_CLK clock */ 2144 0U, /*!< P0_PSI5_S_UART_CLK clock */ 2145 0U, /*!< P0_PSI5_S_WDOG0_CLK clock */ 2146 0U, /*!< P0_PSI5_S_WDOG1_CLK clock */ 2147 0U, /*!< P0_PSI5_S_WDOG2_CLK clock */ 2148 0U, /*!< P0_PSI5_S_WDOG3_CLK clock */ 2149 0U, /*!< P0_REG_INTF_2X_CLK clock */ 2150 0U, /*!< P0_REG_INTF_CLK clock */ 2151 0U, /*!< P1_CLKOUT_SRC_CLK clock */ 2152 0U, /*!< P1_DSPI60_CLK clock */ 2153 0U, /*!< ETH_TS_CLK clock */ 2154 0U, /*!< ETH_TS_DIV4_CLK clock */ 2155 0U, /*!< ETH0_REF_RMII_CLK clock */ 2156 0U, /*!< ETH0_RX_MII_CLK clock */ 2157 0U, /*!< ETH0_RX_RGMII_CLK clock */ 2158 0U, /*!< ETH0_TX_RGMII_CLK clock */ 2159 0U, /*!< ETH0_TX_RGMII_LPBK_CLK */ 2160 0U, /*!< ETH1_REF_RMII_CLK clock */ 2161 0U, /*!< ETH1_RX_MII_CLK clock */ 2162 0U, /*!< ETH1_RX_RGMII_CLK clock */ 2163 0U, /*!< ETH1_TX_MII_CLK clock */ 2164 0U, /*!< ETH1_TX_RGMII_CLK clock */ 2165 0U, /*!< ETH1_TX_RGMII_LPBK_CLK */ 2166 0U, /*!< P1_LFAST0_REF_CLK clock */ 2167 0U, /*!< P1_LFAST1_REF_CLK clock */ 2168 0U, /*!< P1_LFAST_DFT_CLK clock */ 2169 0U, /*!< P1_NETC_AXI_CLK clock */ 2170 0U, /*!< P1_LIN_CLK clock */ 2171 0U, /*!< P1_REG_INTF_CLK clock */ 2172 0U, /*!< P2_DBG_ATB_CLK clock */ 2173 0U, /*!< P2_REG_INTF_CLK clock */ 2174 0U, /*!< P3_AES_CLK clock */ 2175 0U, /*!< P3_CLKOUT_SRC_CLK clock */ 2176 0U, /*!< P3_DBG_TS_CLK clock */ 2177 0U, /*!< P3_REG_INTF_CLK clock */ 2178 0U, /*!< P3_SYS_MON1_CLK clock */ 2179 0U, /*!< P3_SYS_MON2_CLK clock */ 2180 0U, /*!< P3_SYS_MON3_CLK clock */ 2181 0U, /*!< P4_CLKOUT_SRC_CLK clock */ 2182 0U, /*!< P4_DSPI60_CLK clock */ 2183 0U, /*!< P4_EMIOS_LCU_CLK clock */ 2184 0U, /*!< P4_LIN_CLK clock */ 2185 0U, /*!< P4_PSI5_125K_CLK clock */ 2186 0U, /*!< P4_PSI5_189K_CLK clock */ 2187 0U, /*!< P4_PSI5_S_BAUD_CLK clock */ 2188 0U, /*!< P4_PSI5_S_CORE_CLK clock */ 2189 0U, /*!< P4_PSI5_S_TRIG0_CLK clock */ 2190 0U, /*!< P4_PSI5_S_TRIG1_CLK clock */ 2191 0U, /*!< P4_PSI5_S_TRIG2_CLK clock */ 2192 0U, /*!< P4_PSI5_S_TRIG3_CLK clock */ 2193 0U, /*!< P4_PSI5_S_UART_CLK clock */ 2194 0U, /*!< P4_PSI5_S_WDOG0_CLK clock */ 2195 0U, /*!< P4_PSI5_S_WDOG1_CLK clock */ 2196 0U, /*!< P4_PSI5_S_WDOG2_CLK clock */ 2197 0U, /*!< P4_PSI5_S_WDOG3_CLK clock */ 2198 0U, /*!< P4_QSPI0_2X_CLK clock */ 2199 0U, /*!< P4_QSPI0_1X_CLK clock */ 2200 0U, /*!< P4_QSPI1_2X_CLK clock */ 2201 0U, /*!< P4_QSPI1_1X_CLK clock */ 2202 0U, /*!< P4_REG_INTF_2X_CLK clock */ 2203 0U, /*!< P4_REG_INTF_CLK clock */ 2204 0U, /*!< P4_SDHC_IP_CLK clock */ 2205 0U, /*!< P4_SDHC_IP_DIV2_CLK clock */ 2206 0U, /*!< P5_DIPORT_CLK clock */ 2207 1U, /*!< P5_AE_CLK clock */ 2208 0U, /*!< P5_CANXL_PE_CLK clock */ 2209 0U, /*!< P5_CANXL_CHI_CLK clock */ 2210 0U, /*!< P5_CLKOUT_SRC_CLK clock */ 2211 0U, /*!< P5_LIN_CLK clock */ 2212 0U, /*!< P5_REG_INTF_CLK clock */ 2213 0U, /*!< P6_REG_INTF_CLK clock */ 2214 0U, /*!< PIT0_CLK clock */ 2215 0U, /*!< PIT1_CLK clock */ 2216 0U, /*!< PIT4_CLK clock */ 2217 0U, /*!< PIT5_CLK clock */ 2218 0U, /*!< P0_PSI5_1US_CLK clock */ 2219 0U, /*!< PSI5_0_CLK clock */ 2220 0U, /*!< P4_PSI5_1US_CLK clock */ 2221 0U, /*!< PSI5_1_CLK clock */ 2222 0U, /*!< PSI5S_0_CLK clock */ 2223 0U, /*!< PSI5S_1_CLK clock */ 2224 0U, /*!< QSPI0_CLK clock */ 2225 0U, /*!< QSPI1_CLK clock */ 2226 0U, /*!< RTU0_CORE_MON1_CLK */ 2227 0U, /*!< RTU0_CORE_MON2_CLK */ 2228 0U, /*!< RTU0_CORE_DIV2_MON1_CLK */ 2229 0U, /*!< RTU0_CORE_DIV2_MON2_CLK */ 2230 0U, /*!< RTU0_CORE_DIV2_MON3_CLK */ 2231 0U, /*!< RTU0_CORE_DIV2_MON4_CLK */ 2232 0U, /*!< RTU0_REG_INTF_CLK clock */ 2233 0U, /*!< RTU1_CORE_DIV2_MON1_CLK */ 2234 0U, /*!< RTU1_CORE_DIV2_MON2_CLK */ 2235 0U, /*!< RTU1_CORE_DIV2_MON3_CLK */ 2236 0U, /*!< RTU1_CORE_DIV2_MON4_CLK */ 2237 0U, /*!< RTU1_REG_INTF_CLK clock */ 2238 0U, /*!< P4_SDHC_CLK clock */ 2239 0U, /*!< RXLUT_CLK clock */ 2240 0U, /*!< SDHC0_CLK clock */ 2241 0U, /*!< SINC_CLK clock */ 2242 0U, /*!< SIPI0_CLK clock */ 2243 0U, /*!< SIPI1_CLK clock */ 2244 0U, /*!< SIUL2_0_CLK clock */ 2245 0U, /*!< SIUL2_1_CLK clock */ 2246 0U, /*!< SIUL2_4_CLK clock */ 2247 0U, /*!< SIUL2_5_CLK clock */ 2248 0U, /*!< P0_DSPI_CLK clock */ 2249 0U, /*!< SPI0_CLK clock */ 2250 0U, /*!< SPI1_CLK clock */ 2251 0U, /*!< P1_DSPI_CLK clock */ 2252 0U, /*!< SPI2_CLK clock */ 2253 0U, /*!< SPI3_CLK clock */ 2254 0U, /*!< SPI4_CLK clock */ 2255 0U, /*!< P4_DSPI_CLK clock */ 2256 0U, /*!< SPI5_CLK clock */ 2257 0U, /*!< SPI6_CLK clock */ 2258 0U, /*!< SPI7_CLK clock */ 2259 0U, /*!< P5_DSPI_CLK clock */ 2260 0U, /*!< SPI8_CLK clock */ 2261 0U, /*!< SPI9_CLK clock */ 2262 0U, /*!< SRX0_CLK clock */ 2263 0U, /*!< SRX1_CLK clock */ 2264 0U, /*!< CORE_PLL_REFCLKOUT clock */ 2265 0U, /*!< CORE_PLL_FBCLKOUT clock */ 2266 0U, /*!< PERIPH_PLL_REFCLKOUT clock */ 2267 0U, /*!< PERIPH_PLL_FBCLKOUT clock */ 2268 }; 2269 #endif 2270 2271 2272 /* Clock stop constant section data */ 2273 #define MCU_STOP_SEC_CONST_16 2274 #include "Mcu_MemMap.h" 2275 2276 2277 2278 2279 /* Clock start constant section data */ 2280 #define MCU_START_SEC_CONST_32 2281 #include "Mcu_MemMap.h" 2282 2283 #if (defined(CLOCK_IP_DEV_ERROR_DETECT)) 2284 #if (CLOCK_IP_DEV_ERROR_DETECT == STD_ON) 2285 /* Clock name types */ 2286 const uint32 Clock_Ip_au8ClockNameTypes[CLOCK_IP_NAMES_NO] = 2287 { 2288 /* CLOCK_IS_OFF clock */ 0U, /* CLOCK_IS_OFF */ 2289 /* FIRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FIRC_CLK clock */ 2290 /* FXOSC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FXOSC_CLK clock */ 2291 /* SIRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIRC_CLK clock */ 2292 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 2293 /* FIRC_AE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FIRC_AE_CLK clock */ 2294 #endif 2295 /* COREPLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_CLK clock */ 2296 /* PERIPHPLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_CLK clock */ 2297 /* DDRPLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DDRPLL_CLK clock */ 2298 /* LFAST0_PLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LFAST0_PLL_CLK clock */ 2299 /* LFAST1_PLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LFAST1_PLL_CLK clock */ 2300 /* COREPLL_PHI0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_PHI0 clock */ 2301 /* COREPLL_DFS0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS0 clock */ 2302 /* COREPLL_DFS1 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS1 clock */ 2303 /* COREPLL_DFS2 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS2 clock */ 2304 /* COREPLL_DFS3 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS3 clock */ 2305 /* COREPLL_DFS4 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS4 clock */ 2306 /* COREPLL_DFS5 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* COREPLL_DFS5 clock */ 2307 /* PERIPHPLL_PHI0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI0 clock */ 2308 /* PERIPHPLL_PHI1 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI1 clock */ 2309 /* PERIPHPLL_PHI2 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI2 clock */ 2310 /* PERIPHPLL_PHI3 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI3 clock */ 2311 /* PERIPHPLL_PHI4 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI4 clock */ 2312 /* PERIPHPLL_PHI5 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI5 clock */ 2313 /* PERIPHPLL_PHI6 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_PHI6 clock */ 2314 /* PERIPHPLL_DFS0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS0 clock */ 2315 /* PERIPHPLL_DFS1 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS1 clock */ 2316 /* PERIPHPLL_DFS2 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS2 clock */ 2317 /* PERIPHPLL_DFS3 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS3 clock */ 2318 /* PERIPHPLL_DFS4 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS4 clock */ 2319 /* PERIPHPLL_DFS5 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPHPLL_DFS5 clock */ 2320 /* DDRPLL_PHI0 clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DDRPLL_PHI0 clock */ 2321 /* LFAST0_PLL_PH0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LFAST0_PLL_PH0_CLK clock */ 2322 /* LFAST1_PLL_PH0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LFAST0_PLL_PH0_CLK clock */ 2323 /* eth_rgmii_ref clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth_rgmii_ref clock */ 2324 /* eth_ext_ts clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth_ext_ts clock */ 2325 /* eth0_ext_rx clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth0_ext_rx clock */ 2326 /* eth0_ext_tx clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth0_ext_tx clock */ 2327 /* eth1_ext_rx clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth1_ext_rx clock */ 2328 /* eth1_ext_tx clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* eth1_ext_tx clock */ 2329 /* lfast0_ext_ref clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* lfast0_ext_ref clock */ 2330 /* lfast1_ext_ref clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* lfast1_ext_ref clock */ 2331 /* DDR_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DDR_CLK clock */ 2332 /* P0_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_SYS_CLK clock */ 2333 /* P1_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_SYS_CLK clock */ 2334 /* P1_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_SYS_DIV2_CLK clock */ 2335 /* P1_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_SYS_DIV4_CLK clock */ 2336 /* P2_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_SYS_CLK clock */ 2337 /* CORE_M33_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CORE_M33_CLK clock */ 2338 /* P2_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_SYS_DIV2_CLK clock */ 2339 /* P2_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_SYS_DIV4_CLK clock */ 2340 /* P3_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_CLK clock */ 2341 /* CE_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_SYS_DIV2_CLK clock */ 2342 /* CE_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_SYS_DIV4_CLK clock */ 2343 /* P3_SYS_DIV2_NOC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_DIV2_NOC_CLK clock */ 2344 /* P3_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_DIV4_CLK clock */ 2345 /* P4_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SYS_CLK clock */ 2346 /* P4_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SYS_DIV2_CLK clock */ 2347 /* HSE_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* HSE_SYS_DIV2_CLK clock */ 2348 /* P5_SYS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_SYS_CLK clock */ 2349 /* P5_SYS_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_SYS_DIV2_CLK clock */ 2350 /* P5_SYS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_SYS_DIV4_CLK clock */ 2351 /* P2_MATH_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_MATH_CLK clock */ 2352 /* P2_MATH_DIV3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_MATH_DIV3_CLK clock */ 2353 /* GLB_LBIST_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* GLB_LBIST_CLK clock */ 2354 /* RTU0_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_CLK clock */ 2355 /* RTU0_CORE_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_DIV2_CLK clock */ 2356 /* RTU1_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_CLK clock */ 2357 /* RTU1_CORE_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_DIV2_CLK clock */ 2358 /* P0_PSI5_S_UTIL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_UTIL_CLK clock */ 2359 /* P4_PSI5_S_UTIL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_UTIL_CLK clock */ 2360 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 2361 /* SYSTEM_DRUN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_DRUN_CLK clock */ 2362 #endif 2363 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 2364 /* SYSTEM_RUN0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_RUN0_CLK clock */ 2365 #endif 2366 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 2367 /* SYSTEM_SAFE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_SAFE_CLK clock */ 2368 #endif 2369 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 2370 /* SYSTEM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_CLK clock */ 2371 #endif 2372 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2373 /* SYSTEM_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_DIV2_CLK clock */ 2374 #endif 2375 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 2376 /* SYSTEM_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SYSTEM_DIV4_CLK clock */ 2377 #endif 2378 /* THE_LAST_PRODUCER_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* THE_LAST_PRODUCER_CLK */ 2379 /* ADC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ADC0_CLK clock */ 2380 /* ADC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ADC1_CLK clock */ 2381 /* CE_EDMA_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_EDMA_CLK clock */ 2382 /* CE_PIT0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT0_CLK clock */ 2383 /* CE_PIT1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT1_CLK clock */ 2384 /* CE_PIT2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT2_CLK clock */ 2385 /* CE_PIT3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT3_CLK clock */ 2386 /* CE_PIT4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT4_CLK clock */ 2387 /* CE_PIT5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CE_PIT5_CLK clock */ 2388 /* CLKOUT0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT0_CLK clock */ 2389 /* CLKOUT1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT1_CLK clock */ 2390 /* CLKOUT3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT3_CLK clock */ 2391 /* CLKOUT4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT4_CLK clock */ 2392 /* CLKOUT5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CLKOUT5_CLK clock */ 2393 /* CTU_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CTU_CLK clock */ 2394 /* DMACRC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMACRC0_CLK clock */ 2395 /* DMACRC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMACRC1_CLK clock */ 2396 /* DMACRC4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMACRC4_CLK clock */ 2397 /* DMACRC5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMACRC5_CLK clock */ 2398 /* DMAMUX0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMAMUX0_CLK clock */ 2399 /* DMAMUX1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMAMUX1_CLK clock */ 2400 /* DMAMUX4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMAMUX4_CLK clock */ 2401 /* DMAMUX5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* DMAMUX5_CLK clock */ 2402 /* EDMA0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA0_CLK clock */ 2403 /* EDMA1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA1_CLK clock */ 2404 /* EDMA3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA3_CLK clock */ 2405 /* EDMA4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA4_CLK clock */ 2406 /* EDMA5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* EDMA5_CLK clock */ 2407 /* ETH0_TX_MII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_TX_MII_CLK clock */ 2408 /* ENET0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ENET0_CLK clock */ 2409 /* P3_CAN_PE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_CAN_PE_CLK clock */ 2410 /* FLEXCAN0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN0_CLK clock */ 2411 /* FLEXCAN1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN1_CLK clock */ 2412 /* FLEXCAN2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN2_CLK clock */ 2413 /* FLEXCAN3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN3_CLK clock */ 2414 /* FLEXCAN4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN4_CLK clock */ 2415 /* FLEXCAN5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN5_CLK clock */ 2416 /* FLEXCAN6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN6_CLK clock */ 2417 /* FLEXCAN7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN7_CLK clock */ 2418 /* FLEXCAN8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN8_CLK clock */ 2419 /* FLEXCAN9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN9_CLK clock */ 2420 /* FLEXCAN10_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN10_CLK clock */ 2421 /* FLEXCAN11_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN11_CLK clock */ 2422 /* FLEXCAN12_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN12_CLK clock */ 2423 /* FLEXCAN13_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN13_CLK clock */ 2424 /* FLEXCAN14_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN14_CLK clock */ 2425 /* FLEXCAN15_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN15_CLK clock */ 2426 /* FLEXCAN16_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN16_CLK clock */ 2427 /* FLEXCAN17_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN17_CLK clock */ 2428 /* FLEXCAN18_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN18_CLK clock */ 2429 /* FLEXCAN19_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN19_CLK clock */ 2430 /* FLEXCAN20_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN20_CLK clock */ 2431 /* FLEXCAN21_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN21_CLK clock */ 2432 /* FLEXCAN22_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN22_CLK clock */ 2433 /* FLEXCAN23_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FLEXCAN23_CLK clock */ 2434 /* P0_FR_PE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_FR_PE_CLK clock */ 2435 /* FRAY0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FRAY0_CLK clock */ 2436 /* FRAY1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* FRAY1_CLK clock */ 2437 /* GTM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* GTM_CLK clock */ 2438 /* IIIC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* IIIC0_CLK clock */ 2439 /* IIIC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* IIIC1_CLK clock */ 2440 /* IIIC2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* IIIC2_CLK clock */ 2441 /* P0_LIN_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_LIN_BAUD_CLK clock */ 2442 /* LIN0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN0_CLK clock */ 2443 /* LIN1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN1_CLK clock */ 2444 /* LIN2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN2_CLK clock */ 2445 /* P1_LIN_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LIN_BAUD_CLK clock */ 2446 /* LIN3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN3_CLK clock */ 2447 /* LIN4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN4_CLK clock */ 2448 /* LIN5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN5_CLK clock */ 2449 /* P4_LIN_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_LIN_BAUD_CLK clock */ 2450 /* LIN6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN6_CLK clock */ 2451 /* LIN7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN7_CLK clock */ 2452 /* LIN8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN8_CLK clock */ 2453 /* P5_LIN_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_LIN_BAUD_CLK clock */ 2454 /* LIN9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN9_CLK clock */ 2455 /* LIN10_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN10_CLK clock */ 2456 /* LIN11_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* LIN11_CLK clock */ 2457 /* MSCDSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* MSCDSPI_CLK clock */ 2458 /* MSCLIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* MSCLIN_CLK clock */ 2459 /* NANO_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* NANO_CLK clock */ 2460 /* P0_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_CLKOUT_SRC_CLK clock */ 2461 /* P0_CTU_PER_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_CTU_PER_CLK clock */ 2462 /* P0_DSPI_MSC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_DSPI_MSC_CLK clock */ 2463 /* P0_EMIOS_LCU_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_EMIOS_LCU_CLK clock */ 2464 /* P0_GTM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_GTM_CLK clock */ 2465 /* P0_GTM_NOC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_GTM_NOC_CLK clock */ 2466 /* P0_GTM_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_GTM_TS_CLK clock */ 2467 /* P0_LIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_LIN_CLK clock */ 2468 /* P0_NANO_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_NANO_CLK clock */ 2469 /* P0_PSI5_125K_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_125K_CLK clock */ 2470 /* P0_PSI5_189K_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_189K_CLK clock */ 2471 /* P0_PSI5_S_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_BAUD_CLK clock */ 2472 /* P0_PSI5_S_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_CORE_CLK clock */ 2473 /* P0_PSI5_S_TRIG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_TRIG0_CLK clock */ 2474 /* P0_PSI5_S_TRIG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_TRIG1_CLK clock */ 2475 /* P0_PSI5_S_TRIG2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_TRIG2_CLK clock */ 2476 /* P0_PSI5_S_TRIG3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_TRIG3_CLK clock */ 2477 /* P0_PSI5_S_UART_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_UART_CLK clock */ 2478 /* P0_PSI5_S_WDOG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_WDOG0_CLK clock */ 2479 /* P0_PSI5_S_WDOG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_WDOG1_CLK clock */ 2480 /* P0_PSI5_S_WDOG2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_WDOG2_CLK clock */ 2481 /* P0_PSI5_S_WDOG3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_S_WDOG3_CLK clock */ 2482 /* P0_REG_INTF_2X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_REG_INTF_2X_CLK clock */ 2483 /* P0_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_REG_INTF_CLK clock */ 2484 /* P1_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_CLKOUT_SRC_CLK clock */ 2485 /* P1_DSPI60_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_DSPI60_CLK clock */ 2486 /* ETH_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH_TS_CLK clock */ 2487 /* ETH_TS_DIV4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH_TS_DIV4_CLK clock */ 2488 /* ETH0_REF_RMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_REF_RMII_CLK clock */ 2489 /* ETH0_RX_MII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_RX_MII_CLK clock */ 2490 /* ETH0_RX_RGMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_RX_RGMII_CLK clock */ 2491 /* ETH0_TX_RGMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_TX_RGMII_CLK clock */ 2492 /* ETH0_TX_RGMII_LPBK_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH0_TX_RGMII_LPBK_CLK */ 2493 /* ETH1_REF_RMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_REF_RMII_CLK clock */ 2494 /* ETH1_RX_MII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_RX_MII_CLK clock */ 2495 /* ETH1_RX_RGMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_RX_RGMII_CLK clock */ 2496 /* ETH1_TX_MII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_TX_MII_CLK clock */ 2497 /* ETH1_TX_RGMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_TX_RGMII_CLK clock */ 2498 /* ETH1_TX_RGMII_LPBK_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* ETH1_TX_RGMII_LPBK_CLK */ 2499 /* P1_LFAST0_REF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LFAST0_REF_CLK clock */ 2500 /* P1_LFAST1_REF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LFAST1_REF_CLK clock */ 2501 /* P1_LFAST_DFT_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LFAST_DFT_CLK clock */ 2502 /* P1_NETC_AXI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_NETC_AXI_CLK clock */ 2503 /* P1_LIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_LIN_CLK clock */ 2504 /* P1_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_REG_INTF_CLK clock */ 2505 /* P2_DBG_ATB_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_DBG_ATB_CLK clock */ 2506 /* P2_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P2_REG_INTF_CLK clock */ 2507 /* P3_AES_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_AES_CLK clock */ 2508 /* P3_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_CLKOUT_SRC_CLK clock */ 2509 /* P3_DBG_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_DBG_TS_CLK clock */ 2510 /* P3_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_REG_INTF_CLK clock */ 2511 /* P3_SYS_MON1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_MON1_CLK clock */ 2512 /* P3_SYS_MON2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_MON2_CLK clock */ 2513 /* P3_SYS_MON3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P3_SYS_MON3_CLK clock */ 2514 /* P4_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_CLKOUT_SRC_CLK clock */ 2515 /* P4_DSPI60_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_DSPI60_CLK clock */ 2516 /* P4_EMIOS_LCU_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_EMIOS_LCU_CLK clock */ 2517 /* P4_LIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_LIN_CLK clock */ 2518 /* P4_PSI5_125K_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_125K_CLK clock */ 2519 /* P4_PSI5_189K_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_189K_CLK clock */ 2520 /* P4_PSI5_S_BAUD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_BAUD_CLK clock */ 2521 /* P4_PSI5_S_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_CORE_CLK clock */ 2522 /* P4_PSI5_S_TRIG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_TRIG0_CLK clock */ 2523 /* P4_PSI5_S_TRIG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_TRIG1_CLK clock */ 2524 /* P4_PSI5_S_TRIG2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_TRIG2_CLK clock */ 2525 /* P4_PSI5_S_TRIG3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_TRIG3_CLK clock */ 2526 /* P4_PSI5_S_UART_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_UART_CLK clock */ 2527 /* P4_PSI5_S_WDOG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_WDOG0_CLK clock */ 2528 /* P4_PSI5_S_WDOG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_WDOG1_CLK clock */ 2529 /* P4_PSI5_S_WDOG2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_WDOG2_CLK clock */ 2530 /* P4_PSI5_S_WDOG3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_S_WDOG3_CLK clock */ 2531 /* P4_QSPI0_2X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_QSPI0_2X_CLK clock */ 2532 /* P4_QSPI0_1X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_QSPI0_1X_CLK clock */ 2533 /* P4_QSPI1_2X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_QSPI1_2X_CLK clock */ 2534 /* P4_QSPI1_1X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_QSPI1_1X_CLK clock */ 2535 /* P4_REG_INTF_2X_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_REG_INTF_2X_CLK clock */ 2536 /* P4_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_REG_INTF_CLK clock */ 2537 /* P4_SDHC_IP_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SDHC_IP_CLK clock */ 2538 /* P4_SDHC_IP_DIV2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SDHC_IP_DIV2_CLK clock */ 2539 /* P5_DIPORT_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_DIPORT_CLK clock */ 2540 /* P5_AE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_AE_CLK clock */ 2541 /* P5_CANXL_PE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_CANXL_PE_CLK clock */ 2542 /* P5_CANXL_CHI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_CANXL_CHI_CLK clock */ 2543 /* P5_CLKOUT_SRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_CLKOUT_SRC_CLK clock */ 2544 /* P5_LIN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_LIN_CLK clock */ 2545 /* P5_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_REG_INTF_CLK clock */ 2546 /* P6_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P6_REG_INTF_CLK clock */ 2547 /* PIT0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PIT0_CLK clock */ 2548 /* PIT1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PIT1_CLK clock */ 2549 /* PIT4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PIT4_CLK clock */ 2550 /* PIT5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PIT5_CLK clock */ 2551 /* P0_PSI5_1US_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_PSI5_1US_CLK clock */ 2552 /* PSI5_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PSI5_0_CLK clock */ 2553 /* P4_PSI5_1US_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_PSI5_1US_CLK clock */ 2554 /* PSI5_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PSI5_1_CLK clock */ 2555 /* PSI5S_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PSI5S_0_CLK clock */ 2556 /* PSI5S_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PSI5S_1_CLK clock */ 2557 /* QSPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* QSPI0_CLK clock */ 2558 /* QSPI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* QSPI1_CLK clock */ 2559 /* RTU0_CORE_MON1_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_MON1_CLK */ 2560 /* RTU0_CORE_MON2_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_MON2_CLK */ 2561 /* RTU0_CORE_DIV2_MON1_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_DIV2_MON1_CLK */ 2562 /* RTU0_CORE_DIV2_MON2_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_DIV2_MON2_CLK */ 2563 /* RTU0_CORE_DIV2_MON3_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_CORE_DIV2_MON3_CLK */ 2564 /* RTU0_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU0_REG_INTF_CLK clock */ 2565 /* RTU1_CORE_MON1_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_MON1_CLK */ 2566 /* RTU1_CORE_MON2_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_MON2_CLK */ 2567 /* RTU1_CORE_DIV2_MON1_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_DIV2_MON1_CLK */ 2568 /* RTU1_CORE_DIV2_MON2_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_DIV2_MON2_CLK */ 2569 /* RTU1_CORE_DIV2_MON3_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_CORE_DIV2_MON3_CLK */ 2570 /* RTU1_REG_INTF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RTU1_REG_INTF_CLK clock */ 2571 /* P4_SDHC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_SDHC_CLK clock */ 2572 /* RXLUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* RXLUT clock */ 2573 /* SDHC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SDHC0_CLK clock */ 2574 /* SINC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SINC_CLK clock */ 2575 /* SIPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIPI0_CLK clock */ 2576 /* SIPI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIPI1_CLK clock */ 2577 /* SIUL2_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIUL2_0_CLK clock */ 2578 /* SIUL2_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIUL2_1_CLK clock */ 2579 /* SIUL2_4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIUL2_4_CLK clock */ 2580 /* SIUL2_5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SIUL2_5_CLK clock */ 2581 /* P0_DSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P0_DSPI_CLK clock */ 2582 /* SPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI0_CLK clock */ 2583 /* SPI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI1_CLK clock */ 2584 /* P1_DSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P1_DSPI_CLK clock */ 2585 /* SPI2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI2_CLK clock */ 2586 /* SPI3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI3_CLK clock */ 2587 /* SPI4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI4_CLK clock */ 2588 /* P4_DSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P4_DSPI_CLK clock */ 2589 /* SPI5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI5_CLK clock */ 2590 /* SPI6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI6_CLK clock */ 2591 /* SPI7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI7_CLK clock */ 2592 /* P5_DSPI_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* P5_DSPI_CLK clock */ 2593 /* SPI8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI8_CLK clock */ 2594 /* SPI9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SPI9_CLK clock */ 2595 /* SRX0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SRX0_CLK clock */ 2596 /* SRX1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* SRX1_CLK clock */ 2597 /* CORE_PLL_REFCLKOUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CORE_PLL_REFCLKOUT clock */ 2598 /* CORE_PLL_FBCLKOUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* CORE_PLL_FBCLKOUT clock */ 2599 /* PERIPH_PLL_REFCLKOUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPH_PLL_REFCLKOUT clock */ 2600 /* PERIPH_PLL_FBCLKOUT clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) , /* PERIPH_PLL_FBCLKOUT clock */ 2601 }; 2602 #endif /* CLOCK_IP_DEV_ERROR_DETECT == STD_ON */ 2603 #endif /* CLOCK_IP_DEV_ERROR_DETECT */ 2604 /* Clock stop constant section data */ 2605 #define MCU_STOP_SEC_CONST_32 2606 #include "Mcu_MemMap.h" 2607 2608 2609 /* Clock start constant section data */ 2610 #define MCU_START_SEC_CONST_UNSPECIFIED 2611 #include "Mcu_MemMap.h" 2612 2613 Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_MUXS_COUNT] = 2614 { 2615 { 2616 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_0_CSC), 2617 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_1_CSC), 2618 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_2_CSC), 2619 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_3_CSC), 2620 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_4_CSC), 2621 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_5_CSC), 2622 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_6_CSC), 2623 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_7_CSC), 2624 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_8_CSC), 2625 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_9_CSC), 2626 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_10_CSC), 2627 NULL_PTR, 2628 NULL_PTR, 2629 NULL_PTR, 2630 NULL_PTR, 2631 }, 2632 2633 2634 { 2635 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_0_CSC), 2636 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_1_CSC), 2637 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_2_CSC), 2638 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_3_CSC), 2639 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_4_CSC), 2640 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_5_CSC), 2641 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_6_CSC), 2642 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_7_CSC), 2643 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_8_CSC), 2644 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_9_CSC), 2645 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_10_CSC), 2646 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_11_CSC), 2647 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_12_CSC), 2648 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_13_CSC), 2649 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_14_CSC), 2650 }, 2651 2652 2653 { 2654 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_0_CSC), 2655 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_1_CSC), 2656 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_2_CSC), 2657 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_3_CSC), 2658 NULL_PTR, 2659 NULL_PTR, 2660 NULL_PTR, 2661 NULL_PTR, 2662 NULL_PTR, 2663 NULL_PTR, 2664 NULL_PTR, 2665 NULL_PTR, 2666 NULL_PTR, 2667 NULL_PTR, 2668 NULL_PTR, 2669 }, 2670 2671 2672 { 2673 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_0_CSC), 2674 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_1_CSC), 2675 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_2_CSC), 2676 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_3_CSC), 2677 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_4_CSC), 2678 NULL_PTR, 2679 NULL_PTR, 2680 NULL_PTR, 2681 NULL_PTR, 2682 NULL_PTR, 2683 NULL_PTR, 2684 NULL_PTR, 2685 NULL_PTR, 2686 NULL_PTR, 2687 NULL_PTR, 2688 }, 2689 2690 2691 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_0_CSC), 2692 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_1_CSC), 2693 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_2_CSC), 2694 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_3_CSC), 2695 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_4_CSC), 2696 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_5_CSC), 2697 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_6_CSC), 2698 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_7_CSC), 2699 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_8_CSC), 2700 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_9_CSC), 2701 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_10_CSC), 2702 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_11_CSC), 2703 NULL_PTR, 2704 NULL_PTR, 2705 NULL_PTR, 2706 }, 2707 2708 2709 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_0_CSC), 2710 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_1_CSC), 2711 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_2_CSC), 2712 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_3_CSC), 2713 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_4_CSC), 2714 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_5_CSC), 2715 NULL_PTR, 2716 NULL_PTR, 2717 NULL_PTR, 2718 NULL_PTR, 2719 NULL_PTR, 2720 NULL_PTR, 2721 NULL_PTR, 2722 NULL_PTR, 2723 NULL_PTR, 2724 }, 2725 2726 2727 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_6->MUX_0_CSC), 2728 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_6->MUX_1_CSC), 2729 NULL_PTR, 2730 NULL_PTR, 2731 NULL_PTR, 2732 NULL_PTR, 2733 NULL_PTR, 2734 NULL_PTR, 2735 NULL_PTR, 2736 NULL_PTR, 2737 NULL_PTR, 2738 NULL_PTR, 2739 NULL_PTR, 2740 NULL_PTR, 2741 NULL_PTR, 2742 }, 2743 2744 2745 { (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU0__MC_CGM->MUX_0_CSC), 2746 (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU0__MC_CGM->MUX_1_CSC), 2747 NULL_PTR, 2748 NULL_PTR, 2749 NULL_PTR, 2750 NULL_PTR, 2751 NULL_PTR, 2752 NULL_PTR, 2753 NULL_PTR, 2754 NULL_PTR, 2755 NULL_PTR, 2756 NULL_PTR, 2757 NULL_PTR, 2758 NULL_PTR, 2759 NULL_PTR, 2760 }, 2761 2762 2763 { (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU1__MC_CGM->MUX_0_CSC), 2764 (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU1__MC_CGM->MUX_1_CSC), 2765 NULL_PTR, 2766 NULL_PTR, 2767 NULL_PTR, 2768 NULL_PTR, 2769 NULL_PTR, 2770 NULL_PTR, 2771 NULL_PTR, 2772 NULL_PTR, 2773 NULL_PTR, 2774 NULL_PTR, 2775 NULL_PTR, 2776 NULL_PTR, 2777 NULL_PTR, 2778 }, 2779 2780 /* No mux is implemented in CGM_AE */ 2781 { NULL_PTR, 2782 NULL_PTR, 2783 NULL_PTR, 2784 NULL_PTR, 2785 NULL_PTR, 2786 NULL_PTR, 2787 NULL_PTR, 2788 NULL_PTR, 2789 NULL_PTR, 2790 NULL_PTR, 2791 NULL_PTR, 2792 NULL_PTR, 2793 NULL_PTR, 2794 NULL_PTR, 2795 NULL_PTR, 2796 }, 2797 2798 }; 2799 volatile Clock_Ip_CgmPcfsType* const Clock_Ip_apxCgmPcfs[CLOCK_IP_MC_CGM_INSTANCES_COUNT] = 2800 { 2801 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_0->PCFS_SDUR)), 2802 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_1->PCFS_SDUR)), 2803 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_2->PCFS_SDUR)), 2804 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_3->PCFS_SDUR)), 2805 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_4->PCFS_SDUR)), 2806 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_5->PCFS_SDUR)), 2807 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_6->PCFS_SDUR)), 2808 (volatile Clock_Ip_CgmPcfsType*)(&(CLOCK_IP_RTU0__MC_CGM->PCFS_SDUR)), 2809 (volatile Clock_Ip_CgmPcfsType*)(&(CLOCK_IP_RTU1__MC_CGM->PCFS_SDUR)), 2810 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 2811 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_AE->PCFS_SDUR)), 2812 #else 2813 NULL_PTR, 2814 #endif 2815 }; 2816 2817 volatile uint32* const Clock_Ip_apxGprClkout[CLOCK_IP_GPR_INSTANCES_COUNT][CLOCK_IP_CLKOUTS_COUNT] = 2818 { 2819 /* GPR0 instance */ 2820 { 2821 (volatile uint32*)(&IP_GPR0->CLKOUT0SEL), 2822 NULL_PTR, 2823 NULL_PTR, 2824 NULL_PTR, 2825 NULL_PTR, 2826 }, 2827 2828 /* GPR1 instance */ 2829 { 2830 NULL_PTR, 2831 (volatile uint32*)(&IP_GPR1->CLKOUT1SEL), 2832 NULL_PTR, 2833 NULL_PTR, 2834 NULL_PTR, 2835 }, 2836 2837 /* GPR2 instance */ 2838 { 2839 NULL_PTR, 2840 NULL_PTR, 2841 NULL_PTR, 2842 NULL_PTR, 2843 NULL_PTR, 2844 }, 2845 2846 /* GPR3 instance */ 2847 { 2848 NULL_PTR, 2849 NULL_PTR, 2850 NULL_PTR, 2851 NULL_PTR, 2852 (volatile uint32*)(&IP_GPR3->CLKOUT4SEL), 2853 }, 2854 2855 /* GPR4 instance */ 2856 { 2857 NULL_PTR, 2858 NULL_PTR, 2859 (volatile uint32*)(&IP_GPR4->CLKOUT2SEL), 2860 NULL_PTR, 2861 NULL_PTR, 2862 2863 }, 2864 2865 /* GPR5 instance */ 2866 { 2867 NULL_PTR, 2868 NULL_PTR, 2869 NULL_PTR, 2870 (volatile uint32*)(&IP_GPR5->CLKOUT3SEL), 2871 NULL_PTR, 2872 2873 }, 2874 }; 2875 2876 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 2877 Clock_Ip_SystemClockType* const Clock_Ip_apxSystemClock = (Clock_Ip_SystemClockType*)(&(IP_MC_ME_AE->SAFE_MC)); 2878 #endif 2879 2880 Clock_Ip_ExtOSCType* const Clock_Ip_apxXosc[CLOCK_IP_XOSC_INSTANCES_ARRAY_SIZE] = {(Clock_Ip_ExtOSCType*)IP_FXOSC}; 2881 Clock_Ip_PllType const Clock_Ip_apxPll[CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE] = { 2882 { 2883 IP_CORE_PLL, 2884 CLOCK_IP_COREPLL_DIVIDER_COUNT, 2885 }, 2886 { 2887 IP_PERIPH_PLL, 2888 CLOCK_IP_PERIPHPLL_DIVIDER_COUNT, 2889 }, 2890 { 2891 IP_DDR_PLL, 2892 CLOCK_IP_DDRPLL_DIVIDER_COUNT, 2893 } 2894 }; 2895 2896 Clock_Ip_LfastPllType const Clock_Ip_apxLfastPll[CLOCK_IP_LFASTPLL_INSTANCES_ARRAY_SIZE] = 2897 { 2898 { 2899 IP_LFAST_0, 2900 }, 2901 { 2902 IP_LFAST_1, 2903 }, 2904 }; 2905 2906 DFS_Type* const Clock_Ip_apxDfs[CLOCK_IP_DFS_INSTANCES_ARRAY_SIZE] = { 2907 IP_CORE_DFS, 2908 IP_PERIPH_DFS, 2909 }; 2910 Clock_Ip_ClockMonitorType* const Clock_Ip_apxCmu[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE] = 2911 { 2912 (Clock_Ip_ClockMonitorType*)IP_SMU__CMU_FC, 2913 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_0, 2914 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_1, 2915 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2A, 2916 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2B, 2917 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2C, 2918 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_3, 2919 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_4, 2920 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_5, 2921 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_6, 2922 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_0, 2923 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_1, 2924 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_2, 2925 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_0, 2926 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_1, 2927 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_2, 2928 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_3, 2929 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_4, 2930 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_0, 2931 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_1, 2932 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_2, 2933 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_3, 2934 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_4, 2935 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_DEBUG_1, 2936 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_DEBUG_2, 2937 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2938 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_1, 2939 #else 2940 NULL_PTR, 2941 #endif 2942 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 2943 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_2, 2944 #else 2945 NULL_PTR, 2946 #endif 2947 2948 }; 2949 Clock_Ip_NameType const Clock_Ip_aeCmuNames[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE] = 2950 { 2951 P2_SYS_CLK, 2952 P0_REG_INTF_CLK, 2953 P1_REG_INTF_CLK, 2954 FIRC_CLK, 2955 FXOSC_CLK, 2956 P2_MATH_CLK, 2957 P3_SYS_MON1_CLK, 2958 P4_REG_INTF_CLK, 2959 P5_REG_INTF_CLK, 2960 DDR_CLK, 2961 P3_SYS_MON2_CLK, 2962 P3_SYS_MON3_CLK, 2963 CE_SYS_DIV2_CLK, 2964 RTU0_CORE_MON1_CLK, 2965 RTU0_CORE_DIV2_MON1_CLK, 2966 RTU0_CORE_DIV2_MON2_CLK, 2967 RTU0_CORE_MON2_CLK, 2968 RTU0_CORE_DIV2_MON3_CLK, 2969 RTU1_CORE_MON1_CLK, 2970 RTU1_CORE_DIV2_MON1_CLK, 2971 RTU1_CORE_DIV2_MON2_CLK, 2972 RTU1_CORE_MON2_CLK, 2973 RTU1_CORE_DIV2_MON3_CLK, 2974 P0_CLKOUT_SRC_CLK, 2975 P1_CLKOUT_SRC_CLK, 2976 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2977 SYSTEM_DIV2_CLK, 2978 #else 2979 RESERVED_CLK, 2980 #endif 2981 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 2982 SYSTEM_DIV4_CLK, 2983 #else 2984 RESERVED_CLK, 2985 #endif 2986 }; 2987 2988 Clock_Ip_CmuInfoType const Clock_Ip_axCmuInfo[CLOCK_IP_CMU_INFO_SIZE] = { 2989 2990 /* CLOCK_IP_SMU_CMU_FC_INSTANCE */ 2991 { 2992 P2_SYS_CLK, /* Name of the clock that supports cmu (clock monitor) */ 2993 FXOSC_CLK, /* Name of the reference clock */ 2994 P2_SYS_DIV4_CLK, /* Name of the bus clock */ 2995 (Clock_Ip_ClockMonitorType*)IP_SMU__CMU_FC, /* Cmu instance */ 2996 }, 2997 /* CLOCK_IP_CMU_FC_0_INSTANCE */ 2998 { 2999 P0_REG_INTF_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3000 FXOSC_CLK, /* Name of the reference clock */ 3001 P0_REG_INTF_CLK, /* Name of the bus clock */ 3002 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_0, /* Cmu instance */ 3003 }, 3004 /* CLOCK_IP_CMU_FC_1_INSTANCE */ 3005 { 3006 P1_REG_INTF_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3007 FXOSC_CLK, /* Name of the reference clock */ 3008 P1_REG_INTF_CLK, /* Name of the bus clock */ 3009 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_1, /* Cmu instance */ 3010 }, 3011 /* CLOCK_IP_CMU_FC_2A_INSTANCE */ 3012 { 3013 FIRC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3014 FXOSC_CLK, /* Name of the reference clock */ 3015 P2_REG_INTF_CLK, /* Name of the bus clock */ 3016 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2A, /* Cmu instance */ 3017 }, 3018 /* CLOCK_IP_CMU_FC_2B_INSTANCE */ 3019 { 3020 FXOSC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3021 FIRC_CLK, /* Name of the reference clock */ 3022 P2_REG_INTF_CLK, /* Name of the bus clock */ 3023 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2B, /* Cmu instance */ 3024 }, 3025 /* CLOCK_IP_CMU_FC_2C_INSTANCE */ 3026 { 3027 P2_MATH_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3028 FXOSC_CLK, /* Name of the reference clock */ 3029 P2_REG_INTF_CLK, /* Name of the bus clock */ 3030 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2C, /* Cmu instance */ 3031 }, 3032 /* CLOCK_IP_CMU_FC_2D_INSTANCE */ 3033 { 3034 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3035 FXOSC_CLK, /* Name of the reference clock */ 3036 P2_MATH_DIV3_CLK, /* Name of the bus clock */ 3037 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_2D, /* Cmu instance */ 3038 }, 3039 /* CLOCK_IP_CMU_FC_3_INSTANCE */ 3040 { 3041 P3_SYS_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3042 FXOSC_CLK, /* Name of the reference clock */ 3043 P3_REG_INTF_CLK, /* Name of the bus clock */ 3044 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_3, /* Cmu instance */ 3045 }, 3046 /* CLOCK_IP_CMU_FC_4_INSTANCE */ 3047 { 3048 P4_REG_INTF_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3049 FXOSC_CLK, /* Name of the reference clock */ 3050 P4_REG_INTF_CLK, /* Name of the bus clock */ 3051 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_4, /* Cmu instance */ 3052 }, 3053 /* CLOCK_IP_CMU_FC_5_INSTANCE */ 3054 { 3055 P5_REG_INTF_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3056 FXOSC_CLK, /* Name of the reference clock */ 3057 P5_REG_INTF_CLK, /* Name of the bus clock */ 3058 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_5, /* Cmu instance */ 3059 }, 3060 /* CLOCK_IP_CMU_FC_6_INSTANCE */ 3061 { 3062 DDR_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3063 FXOSC_CLK, /* Name of the reference clock */ 3064 P6_REG_INTF_CLK, /* Name of the bus clock */ 3065 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_6, /* Cmu instance */ 3066 }, 3067 /* CLOCK_IP_CE_CMU_FC_0_INSTANCE */ 3068 { 3069 P3_SYS_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3070 FXOSC_CLK, /* Name of the reference clock */ 3071 CE_SYS_DIV4_CLK, /* Name of the bus clock */ 3072 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_0, /* Cmu instance */ 3073 }, 3074 /* CLOCK_IP_CE_CMU_FC_1_INSTANCE */ 3075 { 3076 P3_SYS_MON3_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3077 FXOSC_CLK, /* Name of the reference clock */ 3078 CE_SYS_DIV4_CLK, /* Name of the bus clock */ 3079 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_1, /* Cmu instance */ 3080 }, 3081 /* CLOCK_IP_CE_CMU_FC_2_INSTANCE */ 3082 { 3083 CE_SYS_DIV2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3084 FXOSC_CLK, /* Name of the reference clock */ 3085 CE_SYS_DIV4_CLK, /* Name of the bus clock */ 3086 (Clock_Ip_ClockMonitorType*)IP_CE_CMU_FC_2, /* Cmu instance */ 3087 }, 3088 /* CLOCK_IP_RTU0_CMU_FC_0_INSTANCE */ 3089 { 3090 RTU0_CORE_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3091 FXOSC_CLK, /* Name of the reference clock */ 3092 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3093 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_0, /* Cmu instance */ 3094 }, 3095 /* CLOCK_IP_RTU0_CMU_FC_1_INSTANCE */ 3096 { 3097 RTU0_CORE_DIV2_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3098 FXOSC_CLK, /* Name of the reference clock */ 3099 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3100 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_1, /* Cmu instance */ 3101 }, 3102 /* CLOCK_IP_RTU0_CMU_FC_2_INSTANCE */ 3103 { 3104 RTU0_CORE_DIV2_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3105 FXOSC_CLK, /* Name of the reference clock */ 3106 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3107 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_2, /* Cmu instance */ 3108 }, 3109 /* CLOCK_IP_RTU0_CMU_FC_3_INSTANCE */ 3110 { 3111 RTU0_CORE_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3112 FXOSC_CLK, /* Name of the reference clock */ 3113 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3114 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_3, /* Cmu instance */ 3115 }, 3116 /* CLOCK_IP_RTU0_CMU_FC_4_INSTANCE */ 3117 { 3118 RTU0_CORE_DIV2_MON3_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3119 FXOSC_CLK, /* Name of the reference clock */ 3120 RTU0_REG_INTF_CLK, /* Name of the bus clock */ 3121 (Clock_Ip_ClockMonitorType*)IP_RTU0__CMU_FC_4, /* Cmu instance */ 3122 }, 3123 /* CLOCK_IP_RTU1_CMU_FC_0_INSTANCE */ 3124 { 3125 RTU1_CORE_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3126 FXOSC_CLK, /* Name of the reference clock */ 3127 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3128 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_0, /* Cmu instance */ 3129 }, 3130 /* CLOCK_IP_RTU1_CMU_FC_1_INSTANCE */ 3131 { 3132 RTU1_CORE_DIV2_MON1_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3133 FXOSC_CLK, /* Name of the reference clock */ 3134 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3135 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_1, /* Cmu instance */ 3136 }, 3137 /* CLOCK_IP_RTU1_CMU_FC_2_INSTANCE */ 3138 { 3139 RTU1_CORE_DIV2_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3140 FXOSC_CLK, /* Name of the reference clock */ 3141 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3142 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_2, /* Cmu instance */ 3143 }, 3144 /* CLOCK_IP_RTU1_CMU_FC_3_INSTANCE */ 3145 { 3146 RTU1_CORE_MON2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3147 FXOSC_CLK, /* Name of the reference clock */ 3148 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3149 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_3, /* Cmu instance */ 3150 }, 3151 /* CLOCK_IP_RTU1_CMU_FC_4_INSTANCE */ 3152 { 3153 RTU1_CORE_DIV2_MON3_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3154 FXOSC_CLK, /* Name of the reference clock */ 3155 RTU1_REG_INTF_CLK, /* Name of the bus clock */ 3156 (Clock_Ip_ClockMonitorType*)IP_RTU1__CMU_FC_4, /* Cmu instance */ 3157 }, 3158 /* CLOCK_IP_CMU_FC_DEBUG_1_INSTANCE */ 3159 { 3160 P0_CLKOUT_SRC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3161 FXOSC_CLK, /* Name of the reference clock */ 3162 P0_REG_INTF_CLK, /* Name of the bus clock */ 3163 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_DEBUG_1, /* Cmu instance */ 3164 }, 3165 /* CLOCK_IP_CMU_FC_DEBUG_2_INSTANCE */ 3166 { 3167 P1_CLKOUT_SRC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3168 FXOSC_CLK, /* Name of the reference clock */ 3169 P1_REG_INTF_CLK, /* Name of the bus clock */ 3170 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_DEBUG_2, /* Cmu instance */ 3171 }, 3172 3173 3174 3175 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 3176 /* CLOCK_IP_CMU_FC_AE_1_INSTANCE */ 3177 { 3178 SYSTEM_DIV2_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3179 FXOSC_CLK, /* Name of the reference clock */ 3180 RESERVED_CLK, /* Name of the bus clock */ 3181 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_1, /* Cmu instance */ 3182 }, 3183 #else 3184 { 3185 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3186 RESERVED_CLK, /* Name of the reference clock */ 3187 RESERVED_CLK, /* Name of the bus clock */ 3188 NULL_PTR, /* Cmu instance */ 3189 }, 3190 #endif 3191 3192 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 3193 /* CLOCK_IP_CMU_FC_AE_2_INSTANCE */ 3194 { 3195 SYSTEM_DIV4_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3196 FXOSC_CLK, /* Name of the reference clock */ 3197 RESERVED_CLK, /* Name of the bus clock */ 3198 (Clock_Ip_ClockMonitorType*)IP_CMU_FC_AE_2, /* Cmu instance */ 3199 }, 3200 #else 3201 { 3202 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3203 RESERVED_CLK, /* Name of the reference clock */ 3204 RESERVED_CLK, /* Name of the bus clock */ 3205 NULL_PTR, /* Cmu instance */ 3206 }, 3207 #endif 3208 }; 3209 Clock_Ip_GprClockControlEnable_Type* const Clock_Ip_apxGprClockControlEnable[CLOCK_IP_PERIPHERAL_GROUPS_COUNT] = 3210 { 3211 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR0_PCTL_BASE), 3212 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR1_PCTL_BASE), 3213 NULL_PTR, 3214 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR3_PCTL_BASE), 3215 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR4_PCTL_BASE), 3216 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR5_PCTL_BASE), 3217 (Clock_Ip_GprClockControlEnable_Type*)(IP_GPR6_PCTL_BASE), 3218 }; 3219 3220 const Clock_Ip_ClockNameSourceType Clock_Ip_aeSourceTypeClockName[CLOCK_IP_PRODUCERS_NO] = { 3221 UKNOWN_TYPE, /*!< CLOCK_IS_OFF */ 3222 IRCOSC_TYPE, /*!< FIRC_CLK */ 3223 XOSC_TYPE, /*!< FXOSC_CLK */ 3224 IRCOSC_TYPE, /*!< SIRC_CLK */ 3225 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 3226 IRCOSC_TYPE, /*!< FIRC_AE_CLK */ 3227 #endif 3228 PLL_TYPE, /*!< COREPLL_CLK */ 3229 PLL_TYPE, /*!< PERIPHPLL_CLK */ 3230 PLL_TYPE, /*!< DDRPLL_CLK */ 3231 PLL_TYPE, /*!< LFAST0_PLL_CLK */ 3232 PLL_TYPE, /*!< LFAST1_PLL_CLK */ 3233 PLL_TYPE, /*!< CORE_PLL_PHI0_CLK */ 3234 PLL_TYPE, /*!< CORE_PLL_DFS0_CLK */ 3235 PLL_TYPE, /*!< CORE_PLL_DFS1_CLK */ 3236 PLL_TYPE, /*!< CORE_PLL_DFS2_CLK */ 3237 PLL_TYPE, /*!< CORE_PLL_DFS3_CLK */ 3238 PLL_TYPE, /*!< CORE_PLL_DFS4_CLK */ 3239 PLL_TYPE, /*!< CORE_PLL_DFS5_CLK */ 3240 PLL_TYPE, /*!< PERIPH_PLL_PHI0_CLK */ 3241 PLL_TYPE, /*!< PERIPH_PLL_PHI1_CLK */ 3242 PLL_TYPE, /*!< PERIPH_PLL_PHI2_CLK */ 3243 PLL_TYPE, /*!< PERIPH_PLL_PHI3_CLK */ 3244 PLL_TYPE, /*!< PERIPH_PLL_PHI4_CLK */ 3245 PLL_TYPE, /*!< PERIPH_PLL_PHI5_CLK */ 3246 PLL_TYPE, /*!< PERIPH_PLL_PHI6_CLK */ 3247 PLL_TYPE, /*!< PERIPH_PLL_DFS0_CLK */ 3248 PLL_TYPE, /*!< PERIPH_PLL_DFS1_CLK */ 3249 PLL_TYPE, /*!< PERIPH_PLL_DFS2_CLK */ 3250 PLL_TYPE, /*!< PERIPH_PLL_DFS3_CLK */ 3251 PLL_TYPE, /*!< PERIPH_PLL_DFS4_CLK */ 3252 PLL_TYPE, /*!< PERIPH_PLL_DFS5_CLK */ 3253 PLL_TYPE, /*!< DDR_PLL_PHI0_CLK */ 3254 UKNOWN_TYPE, /*!< LFAST0_PLL_PH0_CLK */ 3255 UKNOWN_TYPE, /*!< LFAST1_PLL_PH0_CLK */ 3256 EXT_CLK_TYPE, /*!< ENET_EXT_REF_CLK */ 3257 EXT_CLK_TYPE, /*!< ENET_EXT_TS_CLK */ 3258 EXT_CLK_TYPE, /*!< ENET0_EXT_RX_CLK */ 3259 EXT_CLK_TYPE, /*!< ENET0_EXT_TX_CLK */ 3260 EXT_CLK_TYPE, /*!< ENET1_EXT_RX_CLK */ 3261 EXT_CLK_TYPE, /*!< ENET1_EXT_TX_CLK */ 3262 EXT_CLK_TYPE, /*!< LFAST0_EXT_TX_CLK */ 3263 EXT_CLK_TYPE, /*!< LFAST1_EXT_TX_CLK */ 3264 UKNOWN_TYPE, /*!< DDR_CLK */ 3265 UKNOWN_TYPE, /*!< P0_SYS_CLK */ 3266 UKNOWN_TYPE, /*!< P1_SYS_CLK */ 3267 UKNOWN_TYPE, /*!< P1_SYS_DIV2_CLK */ 3268 UKNOWN_TYPE, /*!< P1_SYS_DIV4_CLK */ 3269 UKNOWN_TYPE, /*!< P2_SYS_CLK */ 3270 UKNOWN_TYPE, /*!< CORE_M33_CLK */ 3271 UKNOWN_TYPE, /*!< P2_SYS_DIV2_CLK */ 3272 UKNOWN_TYPE, /*!< P2_SYS_DIV4_CLK */ 3273 UKNOWN_TYPE, /*!< P3_SYS_CLK */ 3274 UKNOWN_TYPE, /*!< CE_SYS_DIV2_CLK */ 3275 UKNOWN_TYPE, /*!< CE_SYS_DIV4_CLK */ 3276 UKNOWN_TYPE, /*!< P3_SYS_DIV2_NOC_CLK */ 3277 UKNOWN_TYPE, /*!< P3_SYS_DIV4_CLK */ 3278 UKNOWN_TYPE, /*!< P4_SYS_CLK */ 3279 UKNOWN_TYPE, /*!< P4_SYS_DIV2_CLK */ 3280 UKNOWN_TYPE, /*!< HSE_SYS_DIV2_CLK */ 3281 UKNOWN_TYPE, /*!< P5_SYS_CLK */ 3282 UKNOWN_TYPE, /*!< P5_SYS_DIV2_CLK */ 3283 UKNOWN_TYPE, /*!< P5_SYS_DIV4_CLK */ 3284 UKNOWN_TYPE, /*!< P2_MATH_CLK */ 3285 UKNOWN_TYPE, /*!< P2_MATH_DIV3_CLK */ 3286 UKNOWN_TYPE, /*!< GLB_LBIST_CLK */ 3287 UKNOWN_TYPE, /*!< RTU0_CORE_CLK */ 3288 UKNOWN_TYPE, /*!< RTU0_CORE_DIV2_CLK */ 3289 UKNOWN_TYPE, /*!< RTU1_CORE_CLK */ 3290 UKNOWN_TYPE, /*!< RTU1_CORE_DIV2_CLK */ 3291 PLL_TYPE, /*!< P0_PSI5_S_UTIL_CLK */ 3292 PLL_TYPE, /*!< P4_PSI5_S_UTIL_CLK */ 3293 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 3294 UKNOWN_TYPE, /*!< SYSTEM_DRUN_CLK */ 3295 #endif 3296 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK) 3297 UKNOWN_TYPE, /*!< SYSTEM_RUN0_CLK */ 3298 #endif 3299 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK) 3300 UKNOWN_TYPE, /*!< SYSTEM_SAFE_CLK */ 3301 #endif 3302 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 3303 UKNOWN_TYPE, /*!< SYSTEM_CLK */ 3304 #endif 3305 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 3306 UKNOWN_TYPE, /*!< SYSTEM_DIV2_CL */ 3307 #endif 3308 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 3309 UKNOWN_TYPE, /*!< SYSTEM_DIV4_CLK */ 3310 #endif 3311 }; 3312 3313 const Clock_Ip_NameType Clock_Ip_aeHwPllName[CLOCK_IP_HARDWARE_PLL_ARRAY_SIZE] = 3314 { 3315 COREPLL_CLK, /* COREPLL_CLK Clock */ 3316 PERIPHPLL_CLK, /* PERIPHPLL_CLK Clock */ 3317 DDRPLL_CLK, /* DDRPLL_CLK Clock */ 3318 LFAST0_PLL_CLK, /* LFAST0_PLL_CLK Clock */ 3319 LFAST1_PLL_CLK, /* LFAST1_PLL_CLK Clock */ 3320 }; 3321 const Clock_Ip_NameType Clock_Ip_aeHwDfsName[CLOCK_IP_NUMBER_OF_HARDWARE_DFS] = 3322 { 3323 COREPLL_DFS0_CLK, /* COREPLL_DFS0_CLK Clock */ 3324 COREPLL_DFS1_CLK, /* COREPLL_DFS1_CLK Clock */ 3325 COREPLL_DFS2_CLK, /* COREPLL_DFS2_CLK Clock */ 3326 COREPLL_DFS3_CLK, /* COREPLL_DFS3_CLK Clock */ 3327 COREPLL_DFS4_CLK, /* COREPLL_DFS4_CLK Clock */ 3328 COREPLL_DFS5_CLK, /* COREPLL_DFS5_CLK Clock */ 3329 PERIPHPLL_DFS0_CLK, /* PERIPHPLL_DFS0_CLK Clock */ 3330 PERIPHPLL_DFS1_CLK, /* PERIPHPLL_DFS1_CLK Clock */ 3331 PERIPHPLL_DFS2_CLK, /* PERIPHPLL_DFS2_CLK Clock */ 3332 PERIPHPLL_DFS3_CLK, /* PERIPHPLL_DFS3_CLK Clock */ 3333 PERIPHPLL_DFS4_CLK, /* PERIPHPLL_DFS4_CLK Clock */ 3334 PERIPHPLL_DFS5_CLK, /* PERIPHPLL_DFS5_CLK Clock */ 3335 3336 }; 3337 3338 3339 const Clock_Ip_ClockExtensionType Clock_Ip_axFeatureExtensions[CLOCK_IP_EXTENSIONS_SIZE] = { 3340 /* Selector value mask Selector value shift Divider value mask Divider value shift */ 3341 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_0_DIV_MASK, MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_DDR_EXTENSION */ 3342 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_SYS_EXTENSION */ 3343 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_SYS_EXTENSION */ 3344 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_SYS_DIV2_EXTENSION */ 3345 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_SYS_DIV4_EXTENSION */ 3346 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_SYS_EXTENSION */ 3347 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_CORE_M33_EXTENSION */ 3348 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_SYS_DIV2_EXTENSION */ 3349 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_SYS_DIV4_EXTENSION */ 3350 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P3_SYS_EXTENSION */ 3351 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_CE_SYS_DIV2_EXTENSION */ 3352 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_CE_SYS_DIV4_EXTENSION */ 3353 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P3_SYS_DIV2_NOC_EXTENSION */ 3354 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P3_SYS_DIV4_EXTENSION */ 3355 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_SYS_EXTENSION */ 3356 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_SYS_DIV2_EXTENSION */ 3357 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_HSE_SYS_DIV2_EXTENSION */ 3358 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_0_DIV_MASK, MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_P5_SYS_EXTENSION */ 3359 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_SYS_DIV2_EXTENSION */ 3360 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_SYS_DIV4_EXTENSION */ 3361 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_MATH_EXTENSION */ 3362 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_MATH_DIV3_EXTENSION */ 3363 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_0_DIV_MASK, MC_CGM_MUX_8_DC_0_DIV_SHIFT}, /* CLOCK_IP_GLB_LBIST_EXTENSION */ 3364 {RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT, RTU_MC_CGM_MUX_0_DC_0_DIV_MASK, RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_RTU0_CORE_EXTENSION */ 3365 {RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_RTU0_CORE_DIV2_EXTENSION */ 3366 {RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT, RTU_MC_CGM_MUX_0_DC_0_DIV_MASK, RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_RTU1_CORE_EXTENSION */ 3367 {RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_RTU1_CORE_DIV2_EXTENSION */ 3368 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_3_DIV_MASK, MC_CGM_MUX_2_DC_3_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_UTIL_EXTENSION */ 3369 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_3_DIV_MASK, MC_CGM_MUX_2_DC_3_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_UTIL_EXTENSION */ 3370 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, MC_CGM_MUX_10_DC_0_DIV_MASK, MC_CGM_MUX_10_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT0_EXTENSION */ 3371 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, MC_CGM_MUX_10_DC_0_DIV_MASK, MC_CGM_MUX_10_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT1_EXTENSION */ 3372 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_0_DIV_MASK, MC_CGM_MUX_6_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT2_EXTENSION */ 3373 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT3_EXTENSION */ 3374 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT4_EXTENSION */ 3375 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_0_DIV_MASK, MC_CGM_MUX_6_DC_0_DIV_SHIFT}, /* P1_ETH0_TX_MII_EXTENSION */ 3376 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_0_DIV_MASK, MC_CGM_MUX_3_DC_0_DIV_SHIFT}, /* CLOCK_IP_P3_CAN_PE_EXTENSION */ 3377 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_0_DIV_MASK, MC_CGM_MUX_6_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_FR_PE_EXTENSION */ 3378 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_LIN_BAUD_EXTENSION */ 3379 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_LIN_BAUD_EXTENSION */ 3380 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_0_DIV_MASK, MC_CGM_MUX_8_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_LIN_BAUD_EXTENSION */ 3381 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_P5_LIN_BAUD_EXTENSION */ 3382 {GPR0_CLKOUT0SEL_MUXSEL_MASK, GPR0_CLKOUT0SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_CLKOUT_SRC_EXTENSION */ 3383 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_0_DIV_MASK, MC_CGM_MUX_9_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_CTU_PER_EXTENSION */ 3384 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_1_DIV_MASK, MC_CGM_MUX_7_DC_1_DIV_SHIFT}, /* CLOCK_IP_P0_DSPI_MSC_EXTENSION */ 3385 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_EMIOS_LCU_EXTENSION */ 3386 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_0_DIV_MASK, MC_CGM_MUX_7_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_GTM_EXTENSION */ 3387 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_GTM_NOC_EXTENSION */ 3388 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_GTM_TS_EXTENSION */ 3389 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_LIN_EXTENSION */ 3390 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_NANO_EXTENSION */ 3391 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_1_DIV_MASK, MC_CGM_MUX_2_DC_1_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_125K_EXTENSION */ 3392 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_2_DIV_MASK, MC_CGM_MUX_2_DC_2_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_189K_EXTENSION */ 3393 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_5_DIV_MASK, MC_CGM_MUX_2_DC_5_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_BAUD_EXTENSION */ 3394 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_PSI5_S_CORE_EXTENSION */ 3395 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_0_DIV_MASK, MC_CGM_MUX_3_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_TRIG0_EXTENSION */ 3396 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_1_DIV_MASK, MC_CGM_MUX_3_DC_1_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_TRIG1_EXTENSION */ 3397 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_2_DIV_MASK, MC_CGM_MUX_3_DC_2_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_TRIG2_EXTENSION */ 3398 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_3_DIV_MASK, MC_CGM_MUX_3_DC_3_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_TRIG3_EXTENSION */ 3399 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_4_DIV_MASK, MC_CGM_MUX_2_DC_4_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_UART_EXTENSION */ 3400 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_4_DIV_MASK, MC_CGM_MUX_3_DC_4_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_WDOG0_EXTENSION */ 3401 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_5_DIV_MASK, MC_CGM_MUX_3_DC_5_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_WDOG1_EXTENSION */ 3402 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_6_DIV_MASK, MC_CGM_MUX_3_DC_6_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_WDOG2_EXTENSION */ 3403 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_7_DIV_MASK, MC_CGM_MUX_3_DC_7_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_S_WDOG3_EXTENSION */ 3404 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_1_DIV_MASK, MC_CGM_MUX_1_DC_1_DIV_SHIFT}, /* CLOCK_IP_P0_REG_INTF_2X_EXTENSION */ 3405 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_REG_INTF_EXTENSION */ 3406 {GPR1_CLKOUT1SEL_MUXSEL_MASK, GPR1_CLKOUT1SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_CLKOUT_SRC_EXTENSION */ 3407 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_DSPI60_EXTENSION */ 3408 {MC_CGM_MUX_11_CSC_SELCTL_MASK, MC_CGM_MUX_11_CSC_SELCTL_SHIFT, MC_CGM_MUX_11_DC_0_DIV_MASK, MC_CGM_MUX_11_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_LFAST0_REF_EXTENSION */ 3409 {MC_CGM_MUX_12_CSC_SELCTL_MASK, MC_CGM_MUX_12_CSC_SELCTL_SHIFT, MC_CGM_MUX_11_DC_0_DIV_MASK, MC_CGM_MUX_12_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_LFAST1_REF_EXTENSION */ 3410 {MC_CGM_MUX_13_CSC_SELCTL_MASK, MC_CGM_MUX_13_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_LFAST_DFT_EXTENSION */ 3411 {MC_CGM_MUX_14_CSC_SELCTL_MASK, MC_CGM_MUX_14_CSC_SELCTL_SHIFT, MC_CGM_MUX_14_DC_0_DIV_MASK, MC_CGM_MUX_14_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_NETC_AXI_EXTENSION */ 3412 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_LIN_EXTENSION */ 3413 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_0_DIV_MASK, MC_CGM_MUX_5_DC_0_DIV_SHIFT}, /* P1_ETH_TS_EXTENSION */ 3414 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_0_DIV_MASK, MC_CGM_MUX_5_DC_0_DIV_SHIFT}, /* P1_ETH_TS_DIV4_EXTENSION */ 3415 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_2_DIV_MASK, MC_CGM_MUX_7_DC_2_DIV_SHIFT}, /* P1_ETH0_REF_RMII_EXTENSION */ 3416 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_0_DIV_MASK, MC_CGM_MUX_7_DC_0_DIV_SHIFT}, /* P1_ETH0_RX_MII_EXTENSION */ 3417 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_1_DIV_MASK, MC_CGM_MUX_7_DC_1_DIV_SHIFT}, /* P1_ETH0_RX_RGMII_EXTENSION */ 3418 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_1_DIV_MASK, MC_CGM_MUX_6_DC_1_DIV_SHIFT}, /* P1_ETH0_TX_RGMII_EXTENSION */ 3419 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_1_DIV_MASK, MC_CGM_MUX_6_DC_1_DIV_SHIFT}, /* P1_ETH0_TX_RGMII_LPBK_EXTENION */ 3420 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_2_DIV_MASK, MC_CGM_MUX_9_DC_2_DIV_SHIFT}, /* P1_ETH1_REF_RMII_EXTENSION */ 3421 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_0_DIV_MASK, MC_CGM_MUX_9_DC_0_DIV_SHIFT}, /* P1_ETH1_RX_MII_EXTENSION */ 3422 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_1_DIV_MASK, MC_CGM_MUX_9_DC_1_DIV_SHIFT}, /* P1_ETH1_RX_RGMII_EXTENSION */ 3423 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_0_DIV_MASK, MC_CGM_MUX_8_DC_0_DIV_SHIFT}, /* P1_ETH1_TX_MII_EXTENSION */ 3424 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_1_DIV_MASK, MC_CGM_MUX_8_DC_1_DIV_SHIFT}, /* P1_ETH1_TX_RGMII_EXTENSION */ 3425 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_1_DIV_MASK, MC_CGM_MUX_8_DC_1_DIV_SHIFT}, /* P1_ETH1_TX_RGMII_LPBK_EXTENSION */ 3426 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P1_REG_INTF_EXTENSION */ 3427 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P2_DBG_ATB_EXTENSION */ 3428 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P2_REG_INTF_EXTENSION */ 3429 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_1_DIV_MASK, MC_CGM_MUX_2_DC_1_DIV_SHIFT}, /* CLOCK_IP_P3_AES_EXTENSION */ 3430 {GPR3_CLKOUT4SEL_MUXSEL_MASK, GPR3_CLKOUT4SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P3_CLKOUT_SRC_EXTENSION */ 3431 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_P3_DBG_TS_EXTENSION */ 3432 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P3_REG_INTF_EXTENSION */ 3433 {GPR4_CLKOUT2SEL_MUXSEL_MASK, GPR4_CLKOUT2SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_CLKOUT_SRC_EXTENSION */ 3434 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_DSPI60_EXTENSION */ 3435 {MC_CGM_MUX_11_CSC_SELCTL_MASK, MC_CGM_MUX_11_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_EMIOS_LCU_EXTENSION */ 3436 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_LIN_EXTENSION */ 3437 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_1_DIV_MASK, MC_CGM_MUX_2_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_125K_EXTENSION */ 3438 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_2_DIV_MASK, MC_CGM_MUX_2_DC_2_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_189K_EXTENSION */ 3439 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_5_DIV_MASK, MC_CGM_MUX_2_DC_5_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_BAUD_EXTENSION */ 3440 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_PSI5_S_CORE_EXTENSION */ 3441 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_0_DIV_MASK, MC_CGM_MUX_3_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_TRIG0_EXTENSION */ 3442 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_1_DIV_MASK, MC_CGM_MUX_3_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_TRIG1_EXTENSION */ 3443 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_2_DIV_MASK, MC_CGM_MUX_3_DC_2_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_TRIG2_EXTENSION */ 3444 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_3_DIV_MASK, MC_CGM_MUX_3_DC_3_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_TRIG3_EXTENSION */ 3445 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_4_DIV_MASK, MC_CGM_MUX_2_DC_4_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_UART_EXTENSION */ 3446 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_4_DIV_MASK, MC_CGM_MUX_3_DC_4_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_WDOG0_EXTENSION */ 3447 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_5_DIV_MASK, MC_CGM_MUX_3_DC_5_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_WDOG1_EXTENSION */ 3448 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_6_DIV_MASK, MC_CGM_MUX_3_DC_6_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_WDOG2_EXTENSION */ 3449 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_7_DIV_MASK, MC_CGM_MUX_3_DC_7_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_S_WDOG3_EXTENSION */ 3450 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_0_DIV_MASK, MC_CGM_MUX_7_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_QSPI0_2X_EXTENSION */ 3451 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_QSPI0_1X_EXTENSION */ 3452 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_1_DIV_MASK, MC_CGM_MUX_9_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_QSPI1_2X_EXTENSION */ 3453 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_1_DIV_MASK, MC_CGM_MUX_9_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_QSPI1_1X_EXTENSION */ 3454 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_1_DIV_MASK, MC_CGM_MUX_1_DC_1_DIV_SHIFT}, /* CLOCK_IP_P4_REG_INTF_2X_EXTENSION */ 3455 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_REG_INTF_EXTENSION */ 3456 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_SDHC_IP_EXTENSION */ 3457 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_SDHC_IP_DIV2_EXTENSION */ 3458 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_0_DIV_MASK, MC_CGM_MUX_5_DC_0_DIV_SHIFT}, /* CLOCK_IP_P5_AE_EXTENSION */ 3459 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_1_DIV_MASK, MC_CGM_MUX_5_DC_1_DIV_SHIFT}, /* CLOCK_IP_P5_CANXL_PE_EXTENSION */ 3460 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_2_DIV_MASK, MC_CGM_MUX_5_DC_2_DIV_SHIFT}, /* CLOCK_IP_P5_CANXL_CHI_EXTENSION */ 3461 {GPR5_CLKOUT3SEL_MUXSEL_MASK, GPR5_CLKOUT3SEL_MUXSEL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_CLKOUT_SRC_EXTENSION */ 3462 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_LIN_EXTENSION */ 3463 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P5_REG_INTF_EXTENSION */ 3464 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_P6_REG_INTF_EXTENSION */ 3465 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_P0_PSI5_1US_EXTENSION */ 3466 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_PSI5_1US_EXTENSION */ 3467 {RTU_MC_CGM_MUX_1_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_1_CSC_SELCTL_SHIFT, RTU_MC_CGM_MUX_1_DC_0_DIV_MASK, RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_RTU0_REG_INTF_EXTENSION */ 3468 {RTU_MC_CGM_MUX_1_CSC_SELCTL_MASK, RTU_MC_CGM_MUX_1_CSC_SELCTL_SHIFT, RTU_MC_CGM_MUX_1_DC_0_DIV_MASK, RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_RTU1_REG_INTF_EXTENSION */ 3469 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_0_DIV_MASK, MC_CGM_MUX_9_DC_0_DIV_SHIFT}, /* CLOCK_IP_P4_SDHC_EXTENSION */ 3470 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P0_DSPI_EXTENSION */ 3471 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P1_DSPI_EXTENSION */ 3472 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P4_DSPI_EXTENSION */ 3473 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_P5_DSPI_EXTENSION */ 3474 }; 3475 3476 Clock_Ip_GateInfoType const Clock_Ip_axGateInfo[CLOCK_IP_GATE_INFO_SIZE] = { 3477 /* Group index Gate index */ 3478 {CLOCK_IP_GROUP_6_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P6_GROUP_0_BIT0_INDEX */ 3479 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_13_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_13_BIT0_INDEX */ 3480 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_12_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_12_BIT0_INDEX */ 3481 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_1_BIT0_INDEX */ 3482 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_27_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_27_BIT0_INDEX */ 3483 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_28_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_28_BIT0_INDEX */ 3484 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_29_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_29_BIT0_INDEX */ 3485 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_30_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_30_BIT0_INDEX */ 3486 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_31_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_31_BIT0_INDEX */ 3487 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_32_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_32_BIT0_INDEX */ 3488 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_20_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_20_BIT0_INDEX */ 3489 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P0_GROUP_5_BIT1_INDEX */ 3490 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P1_GROUP_1_BIT1_INDEX */ 3491 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P4_GROUP_2_BIT1_INDEX */ 3492 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P5_GROUP_0_BIT1_INDEX */ 3493 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_2}, /* CLOCK_IP_P0_GROUP_5_BIT2_INDEX */ 3494 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_2}, /* CLOCK_IP_P1_GROUP_1_BIT2_INDEX */ 3495 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_2}, /* CLOCK_IP_P4_GROUP_2_BIT2_INDEX */ 3496 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_2}, /* CLOCK_IP_P5_GROUP_0_BIT2_INDEX */ 3497 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_5_BIT0_INDEX */ 3498 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_1_BIT0_INDEX */ 3499 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_0_BIT0_INDEX */ 3500 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_2_BIT0_INDEX */ 3501 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_0_BIT0_INDEX */ 3502 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_12_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_12_BIT0_INDEX */ 3503 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_3_BIT0_INDEX */ 3504 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_4_BIT0_INDEX */ 3505 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_5_BIT0_INDEX */ 3506 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_6_BIT0_INDEX */ 3507 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_7_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_7_BIT0_INDEX */ 3508 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_8_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_8_BIT0_INDEX */ 3509 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_9_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_9_BIT0_INDEX */ 3510 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_10_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_10_BIT0_INDEX */ 3511 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_11_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_11_BIT0_INDEX */ 3512 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_12_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_12_BIT0_INDEX */ 3513 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_13_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_13_BIT0_INDEX */ 3514 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_14_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_14_BIT0_INDEX */ 3515 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_15_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_15_BIT0_INDEX */ 3516 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_16_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_16_BIT0_INDEX */ 3517 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_17_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_17_BIT0_INDEX */ 3518 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_18_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_18_BIT0_INDEX */ 3519 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_19_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_19_BIT0_INDEX */ 3520 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_20_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_20_BIT0_INDEX */ 3521 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_21_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_21_BIT0_INDEX */ 3522 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_22_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_22_BIT0_INDEX */ 3523 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_23_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_23_BIT0_INDEX */ 3524 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_24_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_24_BIT0_INDEX */ 3525 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_25_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_25_BIT0_INDEX */ 3526 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_26_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_26_BIT0_INDEX */ 3527 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_2_BIT0_INDEX */ 3528 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_3_BIT0_INDEX */ 3529 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_22_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_22_BIT0_INDEX */ 3530 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_4_BIT0_INDEX */ 3531 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_0_BIT0_INDEX */ 3532 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_11_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_11_BIT0_INDEX */ 3533 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_8_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_8_BIT0_INDEX */ 3534 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_9_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_9_BIT0_INDEX */ 3535 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_10_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_10_BIT0_INDEX */ 3536 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_5_BIT0_INDEX */ 3537 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_6_BIT0_INDEX */ 3538 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_7_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_7_BIT0_INDEX */ 3539 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_6_BIT0_INDEX */ 3540 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_7_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_7_BIT0_INDEX */ 3541 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_8_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_8_BIT0_INDEX */ 3542 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_3_BIT0_INDEX */ 3543 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_4_BIT0_INDEX */ 3544 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_5_BIT0_INDEX */ 3545 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_6_BIT0_INDEX */ 3546 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_11_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_11_BIT0_INDEX */ 3547 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_22_INDEX, CLOCK_IP_GATE_PCTL_1}, /* CLOCK_IP_P0_GROUP_22_BIT1_INDEX */ 3548 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_3}, /* CLOCK_IP_P0_GROUP_5_BIT3_INDEX */ 3549 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_3}, /* CLOCK_IP_P1_GROUP_1_BIT3_INDEX */ 3550 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_3}, /* CLOCK_IP_P4_GROUP_2_BIT3_INDEX */ 3551 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_3}, /* CLOCK_IP_P5_GROUP_0_BIT3_INDEX */ 3552 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_19_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_19_BIT0_INDEX */ 3553 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_12_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_12_BIT0_INDEX */ 3554 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_23_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_23_BIT0_INDEX */ 3555 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_14_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_14_BIT0_INDEX */ 3556 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_0_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_0_BIT0_INDEX */ 3557 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_1_BIT0_INDEX */ 3558 {CLOCK_IP_GROUP_3_INDEX, CLOCK_IP_GATE_33_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P3_GROUP_33_BIT0_INDEX */ 3559 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_9_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_9_BIT0_INDEX */ 3560 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_24_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_24_BIT0_INDEX */ 3561 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_8_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_8_BIT0_INDEX */ 3562 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_9_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_9_BIT0_INDEX */ 3563 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_21_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_21_BIT0_INDEX */ 3564 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_14_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_14_BIT0_INDEX */ 3565 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_13_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_13_BIT0_INDEX */ 3566 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_6_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_6_BIT0_INDEX */ 3567 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_1_BIT0_INDEX */ 3568 {CLOCK_IP_GROUP_0_INDEX, CLOCK_IP_GATE_7_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P0_GROUP_7_BIT0_INDEX */ 3569 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_2_BIT0_INDEX */ 3570 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_3_BIT0_INDEX */ 3571 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_4_BIT0_INDEX */ 3572 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_3_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_3_BIT0_INDEX */ 3573 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_4_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_4_BIT0_INDEX */ 3574 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_5_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_5_BIT0_INDEX */ 3575 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_1_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_1_BIT0_INDEX */ 3576 {CLOCK_IP_GROUP_5_INDEX, CLOCK_IP_GATE_2_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P5_GROUP_2_BIT0_INDEX */ 3577 {CLOCK_IP_GROUP_1_INDEX, CLOCK_IP_GATE_10_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P1_GROUP_10_BIT0_INDEX */ 3578 {CLOCK_IP_GROUP_4_INDEX, CLOCK_IP_GATE_10_INDEX, CLOCK_IP_GATE_PCTL_0}, /* CLOCK_IP_P4_GROUP_10_BIT0_INDEX */ 3579 }; 3580 3581 3582 3583 /* Clock stop constant section data */ 3584 #define MCU_STOP_SEC_CONST_UNSPECIFIED 3585 #include "Mcu_MemMap.h" 3586 3587 /*================================================================================================== 3588 GLOBAL VARIABLES 3589 ==================================================================================================*/ 3590 3591 /*================================================================================================== 3592 * LOCAL FUNCTION PROTOTYPES 3593 ==================================================================================================*/ 3594 3595 /*================================================================================================== 3596 * LOCAL FUNCTIONS 3597 ==================================================================================================*/ 3598 3599 /*================================================================================================== 3600 * GLOBAL FUNCTIONS 3601 ==================================================================================================*/ 3602 3603 3604 3605 3606 #ifdef __cplusplus 3607 } 3608 #endif 3609 3610 /** @} */ 3611 3612
