CLK_GATE_DEFINE (reference) in projects: hal_nxp-3.5.0

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Searched refs:CLK_GATE_DEFINE (Results 1 – 25 of 98) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54607/drivers/
D	fsl_clock.h	303 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 321 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 323 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 325 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 327 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 331 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /!< Clock gate name: Eeprom. / 333 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54606/drivers/
D	fsl_clock.h	303 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 321 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 323 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 325 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 327 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 331 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /!< Clock gate name: Eeprom. / 333 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54608/drivers/
D	fsl_clock.h	303 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 321 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 323 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 325 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 327 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 331 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /!< Clock gate name: Eeprom. / 333 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54605/drivers/
D	fsl_clock.h	303 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 321 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 323 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 325 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 327 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 331 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /!< Clock gate name: Eeprom. / 333 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54628/drivers/
D	fsl_clock.h	303 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 321 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 323 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 325 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 327 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 331 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /!< Clock gate name: Eeprom. / 333 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54618/drivers/
D	fsl_clock.h	303 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 321 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 323 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 325 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 327 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 331 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /!< Clock gate name: Eeprom. / 333 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54616/drivers/
D	fsl_clock.h	303 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 321 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 323 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 325 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 327 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 331 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /!< Clock gate name: Eeprom. / 333 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S016/drivers/
D	fsl_clock.h	291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S005/drivers/
D	fsl_clock.h	291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S018/drivers/
D	fsl_clock.h	291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S018M/drivers/
D	fsl_clock.h	291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54113/drivers/
D	fsl_clock.h	153 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 168 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), 169 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), 170 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), 171 kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), 172 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), 173 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), 174 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), 175 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), 176 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54114/drivers/
D	fsl_clock.h	153 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 168 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), 169 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), 170 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), 171 kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), 172 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), 173 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), 174 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), 175 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), 176 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54016/drivers/
D	fsl_clock.h	291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018/drivers/
D	fsl_clock.h	291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54005/drivers/
D	fsl_clock.h	291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018M/drivers/
D	fsl_clock.h	291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /!< Clock gate name: Spifi. / 317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
D	fsl_clock.h	299 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 317 kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /!< Clock gate name: Dsp/ 318 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /!< Clock gate name: RomCtrlr/ 319 kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /!< Clock gate name: AxiSwitch/ 320 kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /!< Clock gate name: AxiCtrl/ 321 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /!< Clock gate name: PowerQuad/ 322 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /!< Clock gate name: Casper/ 323 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /!< Clock gate name: HashCrypt/ 324 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /!< Clock gate name: Puf/ 325 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /!< Clock gate name: Rng/ [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
D	fsl_clock.h	299 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 317 kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /!< Clock gate name: Dsp/ 318 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /!< Clock gate name: RomCtrlr/ 319 kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /!< Clock gate name: AxiSwitch/ 320 kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /!< Clock gate name: AxiCtrl/ 321 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /!< Clock gate name: PowerQuad/ 322 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /!< Clock gate name: Casper/ 323 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /!< Clock gate name: HashCrypt/ 324 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /!< Clock gate name: Puf/ 325 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /!< Clock gate name: Rng/ [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
D	fsl_clock.h	299 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 317 kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /!< Clock gate name: Dsp/ 318 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /!< Clock gate name: RomCtrlr/ 319 kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /!< Clock gate name: AxiSwitch/ 320 kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /!< Clock gate name: AxiCtrl/ 321 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /!< Clock gate name: PowerQuad/ 322 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /!< Clock gate name: Casper/ 323 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /!< Clock gate name: HashCrypt/ 324 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /!< Clock gate name: Puf/ 325 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /!< Clock gate name: Rng/ [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5512/drivers/
D	fsl_clock.h	310 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 325 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 327 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 329 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 331 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 333 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 337 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / 339 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /!< Clock gate name: Gpio0. / 341 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /!< Clock gate name: Gpio1. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5528/drivers/
D	fsl_clock.h	300 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 315 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 317 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 319 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 321 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 323 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /!< Clock gate name: Sram4. / 325 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 327 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 329 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 331 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5526/drivers/
D	fsl_clock.h	300 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 315 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 317 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 319 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 321 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 323 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /!< Clock gate name: Sram4. / 325 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 327 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 329 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 331 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S66/drivers/
D	fsl_clock.h	300 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 315 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 317 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 319 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 321 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 323 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /!< Clock gate name: Sram4. / 325 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 327 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 329 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 331 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S69/drivers/
D	fsl_clock.h	300 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ macro 315 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /!< Clock gate name: Rom. / 317 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /!< Clock gate name: Sram1. / 319 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /!< Clock gate name: Sram2. / 321 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /!< Clock gate name: Sram3. / 323 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /!< Clock gate name: Sram4. / 325 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /!< Clock gate name: Flash. / 327 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /!< Clock gate name: Fmc. / 329 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /!< Clock gate name: InputMux. / 331 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /!< Clock gate name: Iocon. / [all …]

12 3 4

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
babblesim_base-3.7.0
babblesim_ext_2G4_channel_NtNcable-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
bsim-3.4.0
bsim-3.6.0-3.5.0
bsim-3.7.0
canopennode-2.7.6
canopennode-3.5.0-3.4.0
chre-3.4.0
civetweb-2.7.6
cmsis-2.7.6
cmsis-3.4.0
cmsis-3.5.0
cmsis-3.7.0-3.6.0
cmsis-dsp-3.5.0
cmsis-dsp-3.7.0-3.6.0
cmsis-nn-3.6.0-3.5.0
cmsis-nn-3.7.0
edtt-2.7.6
edtt-3.6.0-3.5.0-3.4.0
edtt-3.7.0
fatfs-2.7.6
fatfs-3.7.0-3.6.0-3.5.0-3.4.0
hal_adi-3.7.0
hal_altera-2.7.6
hal_altera-3.6.0-3.5.0-3.4.0
hal_altera-3.7.0
hal_ambiq-3.5.0
hal_ambiq-3.6.0
hal_ambiq-3.7.0
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hal_atmel-3.6.0
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hal_espressif-3.6.0
hal_espressif-3.7.0
hal_ethos_u-3.6.0-3.5.0-3.4.0
hal_ethos_u-3.7.0
hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0
hal_infineon-2.7.6
hal_infineon-3.4.0
hal_infineon-3.5.0
hal_infineon-3.6.0
hal_infineon-3.7.0
hal_intel-3.5.0
hal_intel-3.6.0
hal_intel-3.7.0
hal_microchip-2.7.6
hal_microchip-3.6.0-3.5.0-3.4.0
hal_microchip-3.7.0
hal_nordic-2.7.6
hal_nordic-3.4.0
hal_nordic-3.5.0
hal_nordic-3.6.0
hal_nordic-3.7.0
hal_nuvoton-2.7.6
hal_nuvoton-3.4.0
hal_nuvoton-3.5.0
hal_nuvoton-3.6.0
hal_nuvoton-3.7.0
hal_nxp-2.7.6
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hal_nxp-3.7.0
hal_openisa-2.7.6
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hal_openisa-3.7.0-3.6.0
hal_quicklogic-3.6.0-3.5.0-3.4.0-2.7.6
hal_quicklogic-3.7.0
hal_renesas-3.4.0
hal_renesas-3.5.0
hal_renesas-3.6.0
hal_renesas-3.7.0
hal_rpi_pico-3.4.0
hal_rpi_pico-3.7.0-3.6.0-3.5.0
hal_silabs-2.7.6
hal_silabs-3.4.0
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hal_telink-3.7.0
hal_ti-2.7.6
hal_ti-3.4.0
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hal_wurthelektronik-3.5.0-3.4.0
hal_wurthelektronik-3.7.0-3.6.0
hal_xtensa-2.7.6
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liblc3-3.5.0-3.4.0
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littlefs-3.5.0-3.4.0
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lz4-3.4.0-2.7.6
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mipi-sys-t-3.6.0-3.5.0
mipi-sys-t-3.7.0
nanopb-2.7.6
nanopb-3.4.0
net-tools-2.7.6
net-tools-3.4.0
net-tools-3.5.0
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open-amp-3.5.0
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segger-2.7.6
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sof-3.4.0
tf-m-tests-3.4.0
tflite-micro-3.4.0-2.7.6
thrift-3.4.0
tinycbor-2.7.6
tinycrypt-3.6.0-3.5.0-3.4.0-2.7.6
tinycrypt-3.7.0
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trusted-firmware-a-3.6.0-3.5.0
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zscilib-3.4.0