Searched refs:CLCR (Results 1 – 13 of 13) sorted by relevance
| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/cache/cache64/ |
| D | fsl_cache.c | 233 …pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CL… in CACHE64_InvalidateCacheByRange()
234 base->CLCR = pccReg; in CACHE64_InvalidateCacheByRange()
296 …pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CL… in CACHE64_CleanCacheByRange()
297 base->CLCR = pccReg; in CACHE64_CleanCacheByRange()
361 …pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CL… in CACHE64_CleanInvalidateCacheByRange()
362 base->CLCR = pccReg; in CACHE64_CleanInvalidateCacheByRange()
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 856 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
|
| D | MIMXRT685S_cm33.h | 6285 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/ |
| D | MIMXRT633S.h | 6285 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/ |
| D | LPC5536.h | 2084 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/ |
| D | MIMXRT595S_dsp.h | 1272 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
|
| D | MIMXRT595S_cm33.h | 7420 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/ |
| D | LPC5534.h | 2084 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/ |
| D | MIMXRT533S.h | 7416 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/ |
| D | LPC55S36.h | 2083 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/ |
| D | MIMXRT555S.h | 7419 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/ |
| D | MIMX9352_cm33.h | 149416 __IO uint32_t CLCR; /**< Cache line control register, offset: 0x4 */ member
|
| D | MIMX9352_ca55.h | 130458 __IO uint32_t CLCR; /**< Cache line control register, offset: 0x4 */ member
|
