Home
last modified time | relevance | path

Searched refs:CIMR1 (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_ADC.h86 __IO uint32_t CIMR1; /**< Channel Interrupt Mask 1, offset: 0x28 */ member
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_ADC.h91 …__IO uint32_t CIMR1; /**< EOC Interrupt Enable For Standard Inputs, of… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h88101 __IO uint32_t CIMR1; /**< Channel Interrupt Mask 1, offset: 0x28 */ member
DMIMX9352_ca55.h76538 __IO uint32_t CIMR1; /**< Channel Interrupt Mask 1, offset: 0x28 */ member