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Searched refs:CFG (Results 1 – 25 of 160) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcomm/i2c/
Dfsl_i2c.h531 base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; in I2C_MasterEnable()
535 base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; in I2C_MasterEnable()
928 base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_SLVEN_MASK; in I2C_SlaveEnable()
932 base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_SLVEN_MASK; in I2C_SlaveEnable()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/puf/
Dfsl_puf.h295 base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ in PUF_BlockSetKey()
302 base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ in PUF_BlockSetKey()
309 base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ in PUF_BlockEnroll()
316 base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ in PUF_BlockEnroll()
Dfsl_puf.c89 conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; in puf_powerOn()
146 conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; in PUF_PowerCycle()
213 conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); in PUF_Init()
266 conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; in PUF_Deinit()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/adc_12b1msps_sar/
Dfsl_adc.c75 tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ in ADC_Init()
94 base->CFG = tmp32; in ADC_Init()
232 if (0U != (ADC_CFG_ADTRG_MASK & base->CFG)) in ADC_DoAutoCalibration()
369 tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK; in ADC_SetHardwareAverageConfig()
371 base->CFG = tmp32; in ADC_SetHardwareAverageConfig()
Dfsl_adc.h359 base->CFG |= ADC_CFG_ADTRG_MASK; in ADC_EnableHardwareTrigger()
363 base->CFG &= ~ADC_CFG_ADTRG_MASK; in ADC_EnableHardwareTrigger()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcomm/usart/
Dfsl_usart.c236 base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | in USART_Init()
286 base->CFG &= ~(USART_CFG_ENABLE_MASK); in USART_Deinit()
438 if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) in USART_SetBaudRate()
440 if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) in USART_SetBaudRate()
520 base->CFG &= ~(USART_CFG_ENABLE_MASK); in USART_Enable32kMode()
523 base->CFG |= USART_CFG_MODE32K_MASK; in USART_Enable32kMode()
535 base->CFG &= ~(USART_CFG_MODE32K_MASK); in USART_Enable32kMode()
542 base->CFG |= USART_CFG_ENABLE_MASK; in USART_Enable32kMode()
563 temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); in USART_Enable9bitMode()
565 base->CFG = temp; in USART_Enable9bitMode()
[all …]
Dfsl_usart.h459 base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; in USART_EnableMatchAddress()
464 base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; in USART_EnableMatchAddress()
621 base->CFG |= USART_CFG_CTSEN_MASK; in USART_EnableCTS()
625 base->CFG &= ~USART_CFG_CTSEN_MASK; in USART_EnableCTS()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/css_pkc/src/comps/mcuxClPkc/src/
DmcuxClPkc_Initialize.c51 pState->cfg = (uint16_t) PKC->CFG; in MCUX_CSSL_FP_FUNCTION_DEF()
69 PKC->CFG = PKC_CFG_IDLEOP_Msk in MCUX_CSSL_FP_FUNCTION_DEF()
135 PKC->CFG = pState->cfg; in MCUX_CSSL_FP_FUNCTION_DEF()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpc_miniusart/
Dfsl_usart.h525 base->CFG |= USART_CFG_CTSEN_MASK; in USART_EnableCTS()
529 base->CFG &= ~USART_CFG_CTSEN_MASK; in USART_EnableCTS()
546 base->CFG |= USART_CFG_ENABLE_MASK; in USART_EnableTx()
568 base->CFG |= USART_CFG_ENABLE_MASK; in USART_EnableRx()
575 base->CFG &= ~USART_CFG_ENABLE_MASK; in USART_EnableRx()
Dfsl_usart.c232 base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | in USART_Init()
284 base->CFG &= ~(USART_CFG_ENABLE_MASK); in USART_Deinit()
359 if (0U != (base->CFG & USART_CFG_SYNCEN_MASK)) in USART_SetBaudRate()
400 if (0U != (base->CFG & USART_CFG_SYNCEN_MASK)) in USART_SetBaudRate()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpc_i2c/
Dfsl_i2c.h465 base->CFG = (base->CFG & I2C_CFG_MASK) | (uint32_t)I2C_CFG_MSTEN_MASK; in I2C_MasterEnable()
469 base->CFG = (base->CFG & I2C_CFG_MASK) & (~(uint32_t)I2C_CFG_MSTEN_MASK); in I2C_MasterEnable()
833 base->CFG = I2C_CFG_SLVEN(enable); in I2C_SlaveEnable()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpc_dma/
Dfsl_dma.h435 base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; in DMA_EnableChannelPeriphRq()
449 base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; in DMA_DisableChannelPeriphRq()
518 base->CHANNEL[channel].CFG = in DMA_SetChannelPriority()
519 …(base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(p… in DMA_SetChannelPriority()
533 … return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> in DMA_GetChannelPriority()
Dfsl_dma.c192 tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); in DMA_ConfigureChannelTrigger()
194 base->CHANNEL[channel].CFG = tmpReg; in DMA_ConfigureChannelTrigger()
635 tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); in DMA_SetChannelConfig()
644 base->CHANNEL[channel].CFG = tmpReg; in DMA_SetChannelConfig()
1004 if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) in DMA_StartTransfer()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpc_minispi/
Dfsl_spi.h375 base->CFG |= SPI_CFG_ENABLE_MASK; in SPI_Enable()
379 base->CFG &= ~SPI_CFG_ENABLE_MASK; in SPI_Enable()
462 return (bool)(((base->CFG) & SPI_CFG_MASTER_MASK) >> SPI_CFG_MASTER_SHIFT); in SPI_IsMaster()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcomm/spi/
Dfsl_spi.c204 tmpConfig = base->CFG; in SPI_MasterInit()
219 base->CFG = tmpConfig; in SPI_MasterInit()
316 tmpConfig = base->CFG; in SPI_SlaveInit()
327 base->CFG = tmpConfig; in SPI_SlaveInit()
364 base->CFG &= ~(SPI_CFG_ENABLE_MASK); in SPI_Deinit()
489 if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) in SPI_MasterTransferCreateHandle()
Dfsl_spi.h417 base->CFG |= SPI_CFG_ENABLE_MASK; in SPI_Enable()
421 base->CFG &= ~SPI_CFG_ENABLE_MASK; in SPI_Enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S06/drivers/
Dfsl_power.c50 __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ member
357 p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; in POWER_EnterLowPower()
414 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP in POWER_EnterDeepSleep()
501 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN in POWER_EnterPowerDown()
597 PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; in POWER_EnterPowerDown()
666 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN in POWER_EnterDeepPowerDown()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5512/drivers/
Dfsl_power.c50 __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ member
358 p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; in POWER_EnterLowPower()
416 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP in POWER_EnterDeepSleep()
512 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN in POWER_EnterPowerDown()
617 PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; in POWER_EnterPowerDown()
688 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN in POWER_EnterDeepPowerDown()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S04/drivers/
Dfsl_power.c50 __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ member
357 p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; in POWER_EnterLowPower()
414 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP in POWER_EnterDeepSleep()
501 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN in POWER_EnterPowerDown()
597 PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; in POWER_EnterPowerDown()
666 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN in POWER_EnterDeepPowerDown()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S16/drivers/
Dfsl_power.c50 __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ member
358 p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; in POWER_EnterLowPower()
416 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP in POWER_EnterDeepSleep()
512 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN in POWER_EnterPowerDown()
617 PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; in POWER_EnterPowerDown()
688 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN in POWER_EnterDeepPowerDown()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S14/drivers/
Dfsl_power.c50 __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ member
358 p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; in POWER_EnterLowPower()
416 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP in POWER_EnterDeepSleep()
512 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN in POWER_EnterPowerDown()
617 PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; in POWER_EnterPowerDown()
688 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN in POWER_EnterDeepPowerDown()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5514/drivers/
Dfsl_power.c50 __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ member
358 p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; in POWER_EnterLowPower()
416 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP in POWER_EnterDeepSleep()
512 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN in POWER_EnterPowerDown()
617 PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; in POWER_EnterPowerDown()
688 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN in POWER_EnterDeepPowerDown()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5516/drivers/
Dfsl_power.c50 __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ member
358 p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; in POWER_EnterLowPower()
416 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP in POWER_EnterDeepSleep()
512 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN in POWER_EnterPowerDown()
617 PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; in POWER_EnterPowerDown()
688 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN in POWER_EnterDeepPowerDown()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpadc/
Dfsl_lpadc.c176 base->CFG = tmp32; in LPADC_Init()
570 base->CFG |= ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
574 base->CFG &= ~ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5526/drivers/
Dfsl_power.c49 __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ member
369 p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; in POWER_EnterLowPower()
437 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP in POWER_EnterDeepSleep()
527 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN in POWER_EnterPowerDown()
649 lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN in POWER_EnterDeepPowerDown()

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