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Searched refs:CEOCFR0 (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HeaderWrapper_S32K3.h169 #define CEOCFR(base, regIndex) REG_ACCESS((base)->CEOCFR0, (regIndex))
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_ADC.h81 __IO uint32_t CEOCFR0; /**< Channel Pending 0, offset: 0x14 */ member
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_ADC.h86 …__IO uint32_t CEOCFR0; /**< Channel End Of Conversion Flag For Precision… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h88096 __IO uint32_t CEOCFR0; /**< Channel Pending 0, offset: 0x14 */ member
DMIMX9352_ca55.h76533 __IO uint32_t CEOCFR0; /**< Channel Pending 0, offset: 0x14 */ member