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Searched refs:CDOG_SUB_S0B_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h6071 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6075 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h6116 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6120 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5506/
DLPC5506.h6116 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6120 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h6071 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6075 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h6071 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6075 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h6116 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6120 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5512/
DLPC5512.h6546 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6550 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S04/
DLPC55S04.h6498 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6502 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S06/
DLPC55S06.h6498 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6502 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S16/
DLPC55S16.h6930 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6934 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S14/
DLPC55S14.h6929 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6933 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5514/
DLPC5514.h6547 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6551 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5516/
DLPC5516.h6548 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
6552 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h4672 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
4676 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h25310 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25314 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
DMIMXRT1165_cm7.h25313 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25317 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h25631 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25635 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
DMIMXRT1175_cm4.h25628 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25632 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h25631 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25635 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h25328 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25332 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
DMIMXRT1166_cm4.h25325 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25329 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h25643 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25647 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
DMIMXRT1173_cm4.h25640 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25644 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h25646 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25650 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h25646 #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) macro
25650 … (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)

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