Searched refs:CCR0 (Results 1 – 15 of 15) sorted by relevance
| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/hscmp/ |
| D | fsl_hscmp.h | 177 base->CCR0 |= HSCMP_CCR0_CMP_EN_MASK; in HSCMP_Enable()
181 base->CCR0 &= ~HSCMP_CCR0_CMP_EN_MASK; in HSCMP_Enable()
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| D | fsl_hscmp.c | 94 base->CCR0 |= HSCMP_CCR0_CMP_STOP_EN_MASK; in HSCMP_Init()
98 base->CCR0 &= ~HSCMP_CCR0_CMP_STOP_EN_MASK; in HSCMP_Init()
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| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpcmp/ |
| D | fsl_lpcmp.h | 179 base->CCR0 |= LPCMP_CCR0_CMP_EN_MASK; in LPCMP_Enable()
183 base->CCR0 &= ~LPCMP_CCR0_CMP_EN_MASK; in LPCMP_Enable()
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| D | fsl_lpcmp.c | 106 base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK; in LPCMP_Init()
110 base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK; in LPCMP_Init()
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| /hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_LPCMP.h | 75 …__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ member
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| D | S32K344_MU.h | 81 __IO uint32_t CCR0; /**< Core Control Register 0, offset: 0x10 */ member
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| /hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_SIPI.h | 76 …__IO uint32_t CCR0; /**< SIPI Channel Control Register 0, offset: 0x0… member
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| D | S32Z2_MU.h | 81 __IO uint32_t CCR0; /**< Core Control Register 0, offset: 0x10 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/ |
| D | K32L3A60_cm0plus.h | 8575 …__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ member
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| D | K32L3A60_cm4.h | 9210 …__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/ |
| D | LPC5536.h | 18179 …__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/ |
| D | LPC5534.h | 18179 …__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/ |
| D | LPC55S36.h | 22980 …__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/ |
| D | MIMX9352_cm33.h | 65644 __IO uint32_t CCR0; /**< Core Control Register 0, offset: 0x10 */ member
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| D | MIMX9352_ca55.h | 57193 __IO uint32_t CCR0; /**< Core Control Register 0, offset: 0x10 */ member
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