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Searched refs:CCM_REG_OFF (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-3.5.0/imx/drivers/
Dccm_imx7d.h48 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)root + off))) macro
49 #define CCM_REG(root) CCM_REG_OFF(root, 0)
50 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4)
51 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM3/drivers/
Dfsl_clock.h169 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
170 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
171 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
172 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM5/drivers/
Dfsl_clock.h169 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
170 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
171 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
172 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM1/drivers/
Dfsl_clock.h169 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
170 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
171 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
172 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM2/drivers/
Dfsl_clock.h169 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
170 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
171 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
172 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM4/drivers/
Dfsl_clock.h169 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
170 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
171 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
172 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
Dfsl_clock.h167 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off)))) macro
168 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
169 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
170 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN3/drivers/
Dfsl_clock.h176 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
177 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
178 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
179 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
Dfsl_clock.h167 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off)))) macro
168 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
169 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
170 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/
Dfsl_clock.h167 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off)))) macro
168 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
169 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
170 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM6/drivers/
Dfsl_clock.h169 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
170 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
171 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
172 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN1/drivers/
Dfsl_clock.h176 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
177 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
178 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
179 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN5/drivers/
Dfsl_clock.h176 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
177 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
178 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
179 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN2/drivers/
Dfsl_clock.h176 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
177 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
178 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
179 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN4/drivers/
Dfsl_clock.h176 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
177 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
178 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
179 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN6/drivers/
Dfsl_clock.h176 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
177 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
178 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
179 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
Dfsl_clock.h167 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off)))) macro
168 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
169 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
170 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
Dfsl_clock.h167 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off)))) macro
168 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
169 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
170 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML6/drivers/
Dfsl_clock.h194 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
195 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
196 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
197 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML8/drivers/
Dfsl_clock.h194 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
195 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
196 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
197 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML4/drivers/
Dfsl_clock.h194 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
195 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
196 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
197 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
Dfsl_clock.h194 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
195 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
196 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
197 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_clock.h16 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) macro
17 #define CCM_REG(root) CCM_REG_OFF(root, 0U)