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Searched refs:CACHE64_CTRL_CLCR_LADSEL_MASK (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/cache/cache64/
Dfsl_cache.c233 …->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK; in CACHE64_InvalidateCacheByRange()
296 …->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK; in CACHE64_CleanCacheByRange()
361 …->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK; in CACHE64_CleanInvalidateCacheByRange()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h991 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
997 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMIMXRT685S_cm33.h6420 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
6426 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6420 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
6426 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2219 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
2225 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1412 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
1418 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMIMXRT595S_cm33.h7560 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
7566 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2219 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
2225 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7556 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
7562 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2218 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
2224 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7559 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
7565 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)