KINETIS_MUX (reference) in projects: hal_nxp-3.4.0

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Searched refs:KINETIS_MUX (Results 1 – 25 of 40) sorted by relevance

/hal_nxp-3.4.0/dts/nxp/kinetis/
D	MK66FN2M0VLQ18-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 19 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 22 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 23 #define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) / PTA1 / 24 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 / 25 #define UART0_RX_PTA1 KINETIS_MUX('A',1,2) / PTA1 */ [all …]
D	MK66FN2M0VMD18-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 19 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 22 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 23 #define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) / PTA1 / 24 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 / 25 #define UART0_RX_PTA1 KINETIS_MUX('A',1,2) / PTA1 */ [all …]
D	MKV58F1M0VLQ24-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define XB_IN4_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 22 #define XB_IN4_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define XB_IN4/EWM_IN_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 24 #define XB_IN4_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 25 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MKV58F1M0VMD24-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define XB_IN4_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 22 #define XB_IN4_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define XB_IN4/EWM_IN_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 24 #define XB_IN4_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 25 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MK82FN256VLQ15-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 19 #define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 22 #define EMVSIM0_CLK_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 23 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 24 #define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) / PTA1 / 25 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 */ [all …]
D	MKV58F1M0VLL24-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define XB_IN4_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 22 #define XB_IN4_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define XB_IN4/EWM_IN_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 24 #define XB_IN4_PTA0_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 25 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MK82FN256CAX15-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 19 #define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 22 #define EMVSIM0_CLK_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 23 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 24 #define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) / PTA1 / 25 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 */ [all …]
D	MK82FN256VDC15-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 19 #define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 22 #define EMVSIM0_CLK_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 23 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 24 #define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) / PTA1 / 25 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 */ [all …]
D	MK64FN1M0CAJ12-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 22 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 / 23 #define UART0_RX_PTA1 KINETIS_MUX('A',1,2) / PTA1 / 24 #define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) / PTA1 / 25 #define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) / PTA1 */ [all …]
D	MK64FN1M0VLQ12-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 22 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 / 23 #define UART0_RX_PTA1 KINETIS_MUX('A',1,2) / PTA1 / 24 #define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) / PTA1 / 25 #define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) / PTA1 */ [all …]
D	MK64FN1M0VMD12-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 22 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 / 23 #define UART0_RX_PTA1 KINETIS_MUX('A',1,2) / PTA1 / 24 #define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) / PTA1 / 25 #define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) / PTA1 */ [all …]
D	MKE18F512VLL16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MKE18F256VLL16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MKE16F512VLL16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MKE16F256VLL16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MK82FN256VLL15-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 19 #define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 22 #define EMVSIM0_CLK_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 23 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 24 #define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) / PTA1 / 25 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 */ [all …]
D	MKE14F512VLL16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MKE14F256VLL16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MK64FN1M0VDC12-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 22 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 / 23 #define UART0_RX_PTA1 KINETIS_MUX('A',1,2) / PTA1 / 24 #define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) / PTA1 / 25 #define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) / PTA1 */ [all …]
D	MK64FN1M0VLL12-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 20 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 21 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 22 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 / 23 #define UART0_RX_PTA1 KINETIS_MUX('A',1,2) / PTA1 / 24 #define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) / PTA1 / 25 #define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) / PTA1 */ [all …]
D	MK22FN512VDC12-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define PTA0 KINETIS_MUX('A',0,1) /* PTA0 / 18 #define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 19 #define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 20 #define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) / PTA0 / 21 #define PTA1 KINETIS_MUX('A',1,1) / PTA1 / 22 #define UART0_RX_PTA1 KINETIS_MUX('A',1,2) / PTA1 / 23 #define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) / PTA1 / 24 #define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) / PTA1 / 25 #define PTA2 KINETIS_MUX('A',2,1) / PTA2 */ [all …]
D	MKE16F512VLH16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MKE16F256VLH16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MKE14F512VLH16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]
D	MKE14F256VLH16-pinctrl.h	12 #define KINETIS_MUX(port, pin, mux) \ macro 17 #define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA0 / 18 #define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) / PTA0 / 19 #define PTA0 KINETIS_MUX('A',0,1) / PTA0 / 20 #define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) / PTA0 / 21 #define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) / PTA0 / 22 #define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) / PTA0 / 23 #define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) / PTA0 / 24 #define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) / PTA0 / 25 #define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) / PTA0 */ [all …]

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
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