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Searched refs:DMA1_TRIG15_PIO0_17 (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-3.4.0/dts/nxp/lpc/
DLPC55S16JBD64-pinctrl.h1124 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S69JBD64-pinctrl.h1130 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S28JBD64-pinctrl.h1130 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S36JHI48-pinctrl.h2087 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ macro
DLPC55S69JBD100-pinctrl.h1130 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S69JEV98-pinctrl.h1130 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S28JBD100-pinctrl.h1130 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S28JEV98-pinctrl.h1130 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S16JBD100-pinctrl.h1124 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S16JEV98-pinctrl.h1124 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ macro
DLPC55S36JBD100-pinctrl.h2182 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ macro
/hal_nxp-3.4.0/dts/nxp/nxp_imx/rt/
DMIMXRT595SFAWC-pinctrl.h1777 #define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ macro
DMIMXRT595SFFOC-pinctrl.h1779 #define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ macro
DMIMXRT685SFFOB-pinctrl.h1575 #define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ macro
DMIMXRT685SFVKB-pinctrl.h1575 #define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ macro