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Searched refs:DMA0_TRIG5_PIO1_15 (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-3.4.0/dts/nxp/lpc/
DLPC51U68JBD64-pinctrl.h1414 #define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ macro
DLPC54114J256BD64-pinctrl.h1608 #define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ macro
/hal_nxp-3.4.0/dts/nxp/nxp_imx/rt/
DMIMXRT685SFAWBR-pinctrl.h3470 #define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ macro
DMIMXRT595SFAWC-pinctrl.h4037 #define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ macro
DMIMXRT595SFFOC-pinctrl.h4059 #define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ macro
DMIMXRT685SFFOB-pinctrl.h4211 #define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ macro
DMIMXRT685SFVKB-pinctrl.h4211 #define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ macro