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Searched refs:DMA0_TRIG5_PIO1_10 (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-3.4.0/dts/nxp/lpc/
DLPC51U68JBD64-pinctrl.h1260 #define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ macro
DLPC54114J256BD64-pinctrl.h1434 #define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ macro
/hal_nxp-3.4.0/dts/nxp/nxp_imx/rt/
DMIMXRT685SFAWBR-pinctrl.h3072 #define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ macro
DMIMXRT595SFFOC-pinctrl.h3625 #define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ macro
DMIMXRT685SFFOB-pinctrl.h3813 #define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ macro
DMIMXRT685SFVKB-pinctrl.h3813 #define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ macro