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Searched refs:DMA0_TRIG0_PIO1_5 (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-3.4.0/dts/nxp/lpc/
DLPC51U68JBD48-pinctrl.h1033 #define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ macro
DLPC54114J256UK49-pinctrl.h1177 #define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ macro
DLPC51U68JBD64-pinctrl.h1092 #define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ macro
DLPC54114J256BD64-pinctrl.h1245 #define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ macro
/hal_nxp-3.4.0/dts/nxp/nxp_imx/rt/
DMIMXRT685SFAWBR-pinctrl.h2756 #define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ macro
DMIMXRT595SFAWC-pinctrl.h3253 #define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ macro
DMIMXRT595SFFOC-pinctrl.h3255 #define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ macro
DMIMXRT685SFFOB-pinctrl.h3307 #define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ macro
DMIMXRT685SFVKB-pinctrl.h3307 #define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ macro