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/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4_extension.h146 #define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value)) argument
147 …define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~… argument
148 #define ADC_SET_SC1(base, index, value) (BME_OR32(&ADC_SC1_REG(base, index), (uint32_t)(value))) argument
149 #define ADC_CLR_SC1(base, index, value) (BME_AND32(&ADC_SC1_REG(base, index), (uint32_t)(~(value)))) argument
150 #define ADC_TOG_SC1(base, index, value) (BME_XOR32(&ADC_SC1_REG(base, index), (uint32_t)(value))) argument
242 #define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_AD… argument
243 #define ADC_BWR_SC1_ADCH(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu… argument
263 #define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DI… argument
264 #define ADC_BWR_SC1_DIFF(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu… argument
283 #define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AI… argument
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/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_trng.c126 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCM… argument
153 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) argument
154 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (valu… argument
169 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_… argument
184 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_… argument
213 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) argument
214 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (v… argument
231 …define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SC… argument
247 …define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SC… argument
276 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) argument
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Dfsl_common_dsp.h91 #define NVIC_SetPriorityGrouping(value) do {} while(0) argument
93 #define NVIC_EnableIRQ(value) do {} while(0) argument
94 #define NVIC_GetEnableIRQ(value) do {} while(0) argument
95 #define NVIC_DisableIRQ(value) do {} while(0) argument
96 #define NVIC_GetPendingIRQ(value) do {} while(0) argument
97 #define NVIC_SetPendingIRQ(value) do {} while(0) argument
98 #define NVIC_ClearPendingIRQ(value) do {} while(0) argument
99 #define NVIC_GetActive(value) do {} while(0) argument
Dfsl_dmic.h515 static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value) in DMIC_SetGainNoiseEstHwvad() argument
518 base->HWVADTHGN = value & 0xFUL; in DMIC_SetGainNoiseEstHwvad()
528 static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value) in DMIC_SetGainSignalEstHwvad() argument
531 base->HWVADTHGS = value & 0xFUL; in DMIC_SetGainSignalEstHwvad()
541 static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value) in DMIC_SetFilterCtrlHwvad() argument
544 base->HWVADHPFS = value & 0x3UL; in DMIC_SetFilterCtrlHwvad()
554 static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value) in DMIC_SetInputGainHwvad() argument
557 base->HWVADGAIN = value & 0xFUL; in DMIC_SetInputGainHwvad()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_trng.c126 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCM… argument
153 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) argument
154 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (valu… argument
169 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_… argument
184 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_… argument
213 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) argument
214 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (v… argument
231 …define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SC… argument
247 …define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SC… argument
276 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) argument
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Dfsl_aoi.c109 uint16_t value; in AOI_GetEventLogicConfig() local
112 value = base->BFCRT[event].BFCRT01; in AOI_GetEventLogicConfig()
114 temp = (value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT; in AOI_GetEventLogicConfig()
116 temp = (value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT; in AOI_GetEventLogicConfig()
118 temp = (value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT; in AOI_GetEventLogicConfig()
120 temp = (value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT; in AOI_GetEventLogicConfig()
123 temp = (value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT; in AOI_GetEventLogicConfig()
125 temp = (value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT; in AOI_GetEventLogicConfig()
127 temp = (value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT; in AOI_GetEventLogicConfig()
129 temp = (value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT; in AOI_GetEventLogicConfig()
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Dfsl_pmu.h171 static inline void PMU_1P1SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) in PMU_1P1SetRegulatorOutputVoltage() argument
173 base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_OUTPUT_TRG_MASK) | PMU_REG_1P1_OUTPUT_TRG(value); in PMU_1P1SetRegulatorOutputVoltage()
187 static inline void PMU_1P1SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) in PMU_1P1SetBrownoutOffsetVoltage() argument
189 base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_BO_OFFSET_MASK) | PMU_REG_1P1_BO_OFFSET(value); in PMU_1P1SetBrownoutOffsetVoltage()
284 static inline void PMU_3P0SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) in PMU_3P0SetRegulatorOutputVoltage() argument
286 base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_OUTPUT_TRG_MASK) | PMU_REG_3P0_OUTPUT_TRG(value); in PMU_3P0SetRegulatorOutputVoltage()
314 static inline void PMU_3P0SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) in PMU_3P0SetBrownoutOffsetVoltage() argument
316 base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_BO_OFFSET_MASK) | PMU_REG_3P0_BO_OFFSET(value); in PMU_3P0SetBrownoutOffsetVoltage()
415 static inline void PMU_2P5SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) in PMU_2P5SetRegulatorOutputVoltage() argument
417 base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value); in PMU_2P5SetRegulatorOutputVoltage()
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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_trng.c125 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCM… argument
152 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) argument
153 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (valu… argument
168 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_… argument
183 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_… argument
212 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) argument
213 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (v… argument
230 …define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SC… argument
246 …define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SC… argument
275 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) argument
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Dfsl_aoi.c109 uint16_t value; in AOI_GetEventLogicConfig() local
112 value = base->BFCRT[event].BFCRT01; in AOI_GetEventLogicConfig()
114 temp = (value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT; in AOI_GetEventLogicConfig()
116 temp = (value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT; in AOI_GetEventLogicConfig()
118 temp = (value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT; in AOI_GetEventLogicConfig()
120 temp = (value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT; in AOI_GetEventLogicConfig()
123 temp = (value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT; in AOI_GetEventLogicConfig()
125 temp = (value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT; in AOI_GetEventLogicConfig()
127 temp = (value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT; in AOI_GetEventLogicConfig()
129 temp = (value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT; in AOI_GetEventLogicConfig()
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Dfsl_rnga.c38 #define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value)) argument
39 #define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value))) argument
58 #define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value))) argument
76 #define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value))) argument
152 #define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value)) argument
Dfsl_ftm.h735 static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) in FTM_SetSoftwareCtrlEnable() argument
737 if (value) in FTM_SetSoftwareCtrlEnable()
754 static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) in FTM_SetSoftwareCtrlVal() argument
756 if (value) in FTM_SetSoftwareCtrlVal()
816 static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) in FTM_SetPwmOutputEnable() argument
818 if (value) in FTM_SetPwmOutputEnable()
841 static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) in FTM_SetFaultControlEnable() argument
847 if (value) in FTM_SetFaultControlEnable()
866 static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) in FTM_SetDeadTimeEnable() argument
868 if (value) in FTM_SetDeadTimeEnable()
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Dfsl_sysmpu.c300 uint32_t value; in SYSMPU_GetDetailErrorAccessInfo() local
309 value = (base->SP[slaveNum].EDR & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT; in SYSMPU_GetDetailErrorAccessInfo()
310 if (value == 0U) in SYSMPU_GetDetailErrorAccessInfo()
314 else if ((value & (uint16_t)(value - 1U)) == 0U) in SYSMPU_GetDetailErrorAccessInfo()
323 value = base->SP[slaveNum].EDR & (~SYSMPU_EDR_EACD_MASK); in SYSMPU_GetDetailErrorAccessInfo()
324 attributes_temp = (value & SYSMPU_EDR_EATTR_MASK) >> SYSMPU_EDR_EATTR_SHIFT; in SYSMPU_GetDetailErrorAccessInfo()
325 accessType_temp = (value & SYSMPU_EDR_ERW_MASK) >> SYSMPU_EDR_ERW_SHIFT; in SYSMPU_GetDetailErrorAccessInfo()
327 errInform->master = (value & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT; in SYSMPU_GetDetailErrorAccessInfo()
331 …errInform->processorIdentification = (uint8_t)((value & SYSMPU_EDR_EPID_MASK) >> SYSMPU_EDR_EPID_S… in SYSMPU_GetDetailErrorAccessInfo()
Dfsl_ftfx_flexnvm.c423 …LEXNVM_GetProperty(flexnvm_config_t *config, flexnvm_property_tag_t whichProperty, uint32_t *value) in FLEXNVM_GetProperty() argument
425 if ((config == NULL) || (value == NULL)) in FLEXNVM_GetProperty()
436 *value = config->ftfxConfig.flashDesc.sectorSize; in FLEXNVM_GetProperty()
440 *value = config->ftfxConfig.flashDesc.totalSize; in FLEXNVM_GetProperty()
444 … *value = config->ftfxConfig.flashDesc.totalSize / config->ftfxConfig.flashDesc.blockCount; in FLEXNVM_GetProperty()
448 *value = config->ftfxConfig.flashDesc.blockCount; in FLEXNVM_GetProperty()
452 *value = config->ftfxConfig.flashDesc.blockBase; in FLEXNVM_GetProperty()
456 *value = config->ftfxConfig.flashDesc.aliasBlockBase; in FLEXNVM_GetProperty()
460 *value = config->ftfxConfig.flexramBlockBase; in FLEXNVM_GetProperty()
464 *value = config->ftfxConfig.flexramTotalSize; in FLEXNVM_GetProperty()
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Dfsl_trgmux.c39 uint32_t value; in TRGMUX_SetTriggerSource() local
42 value = base->TRGCFG[index]; in TRGMUX_SetTriggerSource()
43 if (0U != (value & TRGMUX_TRGCFG_LK_MASK)) in TRGMUX_SetTriggerSource()
51 value = (value & ~((uint32_t)TRGMUX_TRGCFG_SEL0_MASK << (uint32_t)input)) | in TRGMUX_SetTriggerSource()
53 base->TRGCFG[index] = value; in TRGMUX_SetTriggerSource()
Dfsl_ftfx_flash.c1055 …us_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) in FLASH_GetProperty() argument
1057 if ((config == NULL) || (value == NULL)) in FLASH_GetProperty()
1068 *value = config->ftfxConfig[0].flashDesc.sectorSize; in FLASH_GetProperty()
1072 *value = config->ftfxConfig[0].flashDesc.totalSize; in FLASH_GetProperty()
1076 … *value = config->ftfxConfig[0].flashDesc.totalSize / config->ftfxConfig[0].flashDesc.blockCount; in FLASH_GetProperty()
1080 *value = config->ftfxConfig[0].flashDesc.blockCount; in FLASH_GetProperty()
1084 *value = config->ftfxConfig[0].flashDesc.blockBase; in FLASH_GetProperty()
1088 *value = (uint32_t)config->ftfxConfig[0].flashDesc.feature.hasXaccControl; in FLASH_GetProperty()
1092 *value = config->ftfxConfig[0].flashDesc.accessSegmentMem.size; in FLASH_GetProperty()
1096 *value = config->ftfxConfig[0].flashDesc.accessSegmentMem.count; in FLASH_GetProperty()
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Dfsl_ftfx_cache.c304 uint32_t value = MCM0_CACHE_REG; in FTFx_CACHE_PflashGetPrefetchSpeculation() local
305 if (0U != (value & MCM_PLACR_DFCS_MASK)) in FTFx_CACHE_PflashGetPrefetchSpeculation()
314 if (0U == (value & MCM_PLACR_EFDS_MASK)) in FTFx_CACHE_PflashGetPrefetchSpeculation()
323 uint32_t value = FMC_CACHE_REG; in FTFx_CACHE_PflashGetPrefetchSpeculation() local
324 if (0U == (value & FMC_CACHE_B0DPE_MASK)) in FTFx_CACHE_PflashGetPrefetchSpeculation()
329 if (0U == (value & FMC_CACHE_B0IPE_MASK)) in FTFx_CACHE_PflashGetPrefetchSpeculation()
337 uint32_t value = MSCM_OCMDR0_REG; in FTFx_CACHE_PflashGetPrefetchSpeculation() local
338 if (0U != (value & MSCM_OCMDR_OCMC1_DFCS_MASK)) in FTFx_CACHE_PflashGetPrefetchSpeculation()
347 if (0U != (value & MSCM_OCMDR_OCMC1_DFDS_MASK)) in FTFx_CACHE_PflashGetPrefetchSpeculation()
Dfsl_pdb.h428 static inline void PDB_SetModulusValue(PDB_Type *base, uint32_t value) in PDB_SetModulusValue() argument
430 base->MOD = PDB_MOD_MOD(value); in PDB_SetModulusValue()
451 static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value) in PDB_SetCounterDelayValue() argument
453 base->IDLY = PDB_IDLY_IDLY(value); in PDB_SetCounterDelayValue()
494 uint32_t value) in PDB_SetADCPreTriggerDelayValue() argument
500 base->CH[channel].DLY[pretriggerNumber] = PDB_DLY_DLY(value); in PDB_SetADCPreTriggerDelayValue()
559 …d PDB_SetDACTriggerIntervalValue(PDB_Type *base, pdb_dac_trigger_channel_t channel, uint32_t value) in PDB_SetDACTriggerIntervalValue() argument
563 base->DAC[channel].INT = PDB_INT_INT(value); in PDB_SetDACTriggerIntervalValue()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
Dfsl_nic301.h159 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) in NIC_SetReadQos() argument
161 *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetReadQos()
182 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) in NIC_SetWriteQos() argument
184 *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetWriteQos()
228 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) in NIC_SetWrTideMark() argument
230 *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); in NIC_SetWrTideMark()
251 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod() argument
253 *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; in NIC_SetFnMod()
274 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod2() argument
276 *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value; in NIC_SetFnMod2()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
Dfsl_nic301.h159 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) in NIC_SetReadQos() argument
161 *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetReadQos()
182 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) in NIC_SetWriteQos() argument
184 *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetWriteQos()
228 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) in NIC_SetWrTideMark() argument
230 *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); in NIC_SetWrTideMark()
251 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod() argument
253 *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; in NIC_SetFnMod()
274 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod2() argument
276 *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value; in NIC_SetFnMod2()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
Dfsl_nic301.h159 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) in NIC_SetReadQos() argument
161 *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetReadQos()
182 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) in NIC_SetWriteQos() argument
184 *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetWriteQos()
228 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) in NIC_SetWrTideMark() argument
230 *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); in NIC_SetWrTideMark()
251 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod() argument
253 *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; in NIC_SetFnMod()
274 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod2() argument
276 *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value; in NIC_SetFnMod2()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
Dfsl_nic301.h159 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) in NIC_SetReadQos() argument
161 *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetReadQos()
182 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) in NIC_SetWriteQos() argument
184 *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetWriteQos()
228 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) in NIC_SetWrTideMark() argument
230 *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); in NIC_SetWrTideMark()
251 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod() argument
253 *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; in NIC_SetFnMod()
274 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod2() argument
276 *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value; in NIC_SetFnMod2()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
Dfsl_nic301.h173 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) in NIC_SetReadQos() argument
175 *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetReadQos()
196 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) in NIC_SetWriteQos() argument
198 *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetWriteQos()
242 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) in NIC_SetWrTideMark() argument
244 *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); in NIC_SetWrTideMark()
265 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod() argument
267 *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; in NIC_SetFnMod()
288 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod2() argument
290 *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value; in NIC_SetFnMod2()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
Dfsl_nic301.h178 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) in NIC_SetReadQos() argument
180 *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetReadQos()
201 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) in NIC_SetWriteQos() argument
203 *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetWriteQos()
247 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) in NIC_SetWrTideMark() argument
249 *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); in NIC_SetWrTideMark()
270 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod() argument
272 *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; in NIC_SetFnMod()
293 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod2() argument
295 *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value; in NIC_SetFnMod2()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
Dfsl_nic301.h178 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) in NIC_SetReadQos() argument
180 *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetReadQos()
201 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) in NIC_SetWriteQos() argument
203 *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetWriteQos()
247 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) in NIC_SetWrTideMark() argument
249 *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); in NIC_SetWrTideMark()
270 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod() argument
272 *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; in NIC_SetFnMod()
293 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod2() argument
295 *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value; in NIC_SetFnMod2()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
Dfsl_nic301.h181 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) in NIC_SetReadQos() argument
183 *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetReadQos()
204 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) in NIC_SetWriteQos() argument
206 *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); in NIC_SetWriteQos()
250 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) in NIC_SetWrTideMark() argument
252 *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); in NIC_SetWrTideMark()
273 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) in NIC_SetFnMod() argument
275 *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; in NIC_SetFnMod()

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