Home
last modified time | relevance | path

Searched refs:tmp32 (Results 1 – 25 of 46) sorted by relevance

12

/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_acmp.c74 uint32_t tmp32; in ACMP_Init() local
87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
90 tmp32 &= ~CMP_C0_OFFSET_MASK; in ACMP_Init()
94 tmp32 |= CMP_C0_PMODE_MASK; in ACMP_Init()
98 tmp32 |= CMP_C0_INVT_MASK; in ACMP_Init()
102 tmp32 |= CMP_C0_COS_MASK; in ACMP_Init()
106 tmp32 |= CMP_C0_OPE_MASK; in ACMP_Init()
108 tmp32 |= CMP_C0_HYSTCTR(config->hysteresisMode); in ACMP_Init()
110 tmp32 |= CMP_C0_OFFSET(config->offsetMode); in ACMP_Init()
112 base->C0 = tmp32; in ACMP_Init()
[all …]
Dfsl_lpadc.c68 uint32_t tmp32 = 0U; in LPADC_Init() local
106 tmp32 |= ADC_CFG_ADCKEN_MASK; in LPADC_Init()
112 tmp32 |= ADC_CFG_VREF1RNG_MASK; in LPADC_Init()
117 tmp32 |= ADC_CFG_PWREN_MASK; in LPADC_Init()
119 tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ in LPADC_Init()
123 base->CFG = tmp32; in LPADC_Init()
230 uint32_t tmp32; in LPADC_GetConvResult() local
232 tmp32 = base->RESFIFO[index]; in LPADC_GetConvResult()
234 if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) in LPADC_GetConvResult()
239 result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; in LPADC_GetConvResult()
[all …]
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_acmp.c74 uint32_t tmp32; in ACMP_Init() local
87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
90 tmp32 &= ~CMP_C0_OFFSET_MASK; in ACMP_Init()
94 tmp32 |= CMP_C0_PMODE_MASK; in ACMP_Init()
98 tmp32 |= CMP_C0_INVT_MASK; in ACMP_Init()
102 tmp32 |= CMP_C0_COS_MASK; in ACMP_Init()
106 tmp32 |= CMP_C0_OPE_MASK; in ACMP_Init()
108 tmp32 |= CMP_C0_HYSTCTR(config->hysteresisMode); in ACMP_Init()
110 tmp32 |= CMP_C0_OFFSET(config->offsetMode); in ACMP_Init()
112 base->C0 = tmp32; in ACMP_Init()
[all …]
Dfsl_dcdc.c93 uint32_t tmp32 = 0U; in DCDC_GetStatusFlags() local
98 tmp32 |= kDCDC_LockedOKStatus; in DCDC_GetStatusFlags()
103 tmp32 |= kDCDC_PSwitchStatus; in DCDC_GetStatusFlags()
108 tmp32 |= kDCDC_PSwitchInterruptStatus; in DCDC_GetStatusFlags()
111 return tmp32; in DCDC_GetStatusFlags()
128 …uint32_t tmp32 = base->REG6 & ~(DCDC_REG6_PSWITCH_INT_RISE_EN_MASK | DCDC_REG6_PSWITCH_INT_FALL_EN… in DCDC_SetPSwitchInterruptConfig() local
130 tmp32 |= mask; in DCDC_SetPSwitchInterruptConfig()
131 base->REG6 = tmp32; in DCDC_SetPSwitchInterruptConfig()
151 uint32_t tmp32; in DCDC_SetLowPowerConfig() local
153 tmp32 = in DCDC_SetLowPowerConfig()
[all …]
Dfsl_adc16.c68 uint32_t tmp32; in ADC16_Init() local
76 tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); in ADC16_Init()
79 tmp32 |= ADC_CFG1_ADLSMP_MASK; in ADC16_Init()
81 tmp32 |= ADC_CFG1_ADIV(config->clockDivider); in ADC16_Init()
84 tmp32 |= ADC_CFG1_ADLPC_MASK; in ADC16_Init()
86 base->CFG1 = tmp32; in ADC16_Init()
89 tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); in ADC16_Init()
92 tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); in ADC16_Init()
96 tmp32 |= ADC_CFG2_ADHSC_MASK; in ADC16_Init()
100 tmp32 |= ADC_CFG2_ADACKEN_MASK; in ADC16_Init()
[all …]
Dfsl_adc12.c137 uint32_t tmp32; in ADC12_Init() local
145 tmp32 = (base->CFG1 & ~(ADC_CFG1_ADICLK_MASK | ADC_CFG1_ADIV_MASK | ADC_CFG1_MODE_MASK)); in ADC12_Init()
146 tmp32 |= (ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_ADIV(config->clockDivider) | in ADC12_Init()
148 base->CFG1 = tmp32; in ADC12_Init()
151 tmp32 = (base->CFG2 & ~ADC_CFG2_SMPLTS_MASK); in ADC12_Init()
152 tmp32 |= ADC_CFG2_SMPLTS(config->sampleClockCount - 1U); in ADC12_Init()
153 base->CFG2 = tmp32; in ADC12_Init()
156 tmp32 = (base->SC2 & ~ADC_SC2_REFSEL_MASK); in ADC12_Init()
157 tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); in ADC12_Init()
158 base->SC2 = tmp32; in ADC12_Init()
[all …]
Dfsl_rtc.c392 uint32_t tmp32 = 0U; in RTC_EnableInterrupts() local
397 tmp32 |= RTC_IER_TIIE_MASK; in RTC_EnableInterrupts()
401 tmp32 |= RTC_IER_TOIE_MASK; in RTC_EnableInterrupts()
405 tmp32 |= RTC_IER_TAIE_MASK; in RTC_EnableInterrupts()
409 tmp32 |= RTC_IER_TSIE_MASK; in RTC_EnableInterrupts()
414 tmp32 |= RTC_IER_MOIE_MASK; in RTC_EnableInterrupts()
417 base->IER |= tmp32; in RTC_EnableInterrupts()
420 tmp32 = 0U; in RTC_EnableInterrupts()
425 tmp32 |= RTC_TIR_TMIE_MASK; in RTC_EnableInterrupts()
429 tmp32 |= RTC_TIR_FSIE_MASK; in RTC_EnableInterrupts()
[all …]
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_acmp.c74 uint32_t tmp32; in ACMP_Init() local
87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
90 tmp32 &= ~CMP_C0_OFFSET_MASK; in ACMP_Init()
94 tmp32 |= CMP_C0_PMODE_MASK; in ACMP_Init()
98 tmp32 |= CMP_C0_INVT_MASK; in ACMP_Init()
102 tmp32 |= CMP_C0_COS_MASK; in ACMP_Init()
106 tmp32 |= CMP_C0_OPE_MASK; in ACMP_Init()
108 tmp32 |= CMP_C0_HYSTCTR(config->hysteresisMode); in ACMP_Init()
110 tmp32 |= CMP_C0_OFFSET(config->offsetMode); in ACMP_Init()
112 base->C0 = tmp32; in ACMP_Init()
[all …]
Dfsl_adc.c68 uint32_t tmp32; in ADC_Init() local
75 tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ in ADC_Init()
76 …tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) | in ADC_Init()
80 tmp32 |= ADC_CFG_OVWREN_MASK; in ADC_Init()
84 tmp32 |= ADC_CFG_ADLSMP_MASK; in ADC_Init()
88 tmp32 |= ADC_CFG_ADLPC_MASK; in ADC_Init()
92 tmp32 |= ADC_CFG_ADHSC_MASK; in ADC_Init()
94 base->CFG = tmp32; in ADC_Init()
97 tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK); in ADC_Init()
100 tmp32 |= ADC_GC_ADCO_MASK; in ADC_Init()
[all …]
Dfsl_lpadc.c68 uint32_t tmp32 = 0U; in LPADC_Init() local
106 tmp32 |= ADC_CFG_ADCKEN_MASK; in LPADC_Init()
112 tmp32 |= ADC_CFG_VREF1RNG_MASK; in LPADC_Init()
117 tmp32 |= ADC_CFG_PWREN_MASK; in LPADC_Init()
119 tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ in LPADC_Init()
123 base->CFG = tmp32; in LPADC_Init()
230 uint32_t tmp32; in LPADC_GetConvResult() local
232 tmp32 = base->RESFIFO[index]; in LPADC_GetConvResult()
234 if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) in LPADC_GetConvResult()
239 result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; in LPADC_GetConvResult()
[all …]
Dfsl_adc_etc.c70 uint32_t tmp32 = 0U; in ADC_ETC_Init() local
83 tmp32 = in ADC_ETC_Init()
100 tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK; in ADC_ETC_Init()
106 tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK; in ADC_ETC_Init()
112 tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK; in ADC_ETC_Init()
115 base->CTRL = tmp32; in ADC_ETC_Init()
196 uint32_t tmp32 = 0U; in ADC_ETC_SetTriggerConfig() local
199 tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) | in ADC_ETC_SetTriggerConfig()
203 tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK; in ADC_ETC_SetTriggerConfig()
207 tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK; in ADC_ETC_SetTriggerConfig()
[all …]
Dfsl_tsc.c69 uint32_t tmp32; in TSC_Init() local
76 tmp32 = TSC_BASIC_SETTING_MEASURE_DELAY_TIME(config->measureDelayTime) | in TSC_Init()
80 tmp32 |= TSC_BASIC_SETTING_AUTO_MEASURE_MASK; in TSC_Init()
82 base->BASIC_SETTING = tmp32; in TSC_Init()
136 uint32_t tmp32 = 0; in TSC_GetMeasureValue() local
140 …tmp32 = ((base->MEASEURE_VALUE) & TSC_MEASEURE_VALUE_X_VALUE_MASK) >> TSC_MEASEURE_VALUE_X_VALUE_S… in TSC_GetMeasureValue()
144 …tmp32 = ((base->MEASEURE_VALUE) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) >> TSC_MEASEURE_VALUE_Y_VALUE_S… in TSC_GetMeasureValue()
151 return tmp32; in TSC_GetMeasureValue()
225 uint32_t tmp32; in TSC_DebugSetPortMode() local
227 tmp32 = base->DEBUG_MODE2; in TSC_DebugSetPortMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
Dfsl_acmp.c74 uint32_t tmp32; in ACMP_Init() local
87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
90 tmp32 &= ~CMP_C0_OFFSET_MASK; in ACMP_Init()
94 tmp32 |= CMP_C0_PMODE_MASK; in ACMP_Init()
98 tmp32 |= CMP_C0_INVT_MASK; in ACMP_Init()
102 tmp32 |= CMP_C0_COS_MASK; in ACMP_Init()
106 tmp32 |= CMP_C0_OPE_MASK; in ACMP_Init()
108 tmp32 |= CMP_C0_HYSTCTR(config->hysteresisMode); in ACMP_Init()
110 tmp32 |= CMP_C0_OFFSET(config->offsetMode); in ACMP_Init()
112 base->C0 = tmp32; in ACMP_Init()
[all …]
Dfsl_dcdc.c95 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
97 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
101 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
105 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
107 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
108 base->CTRL0 = tmp32; in DCDC_Init()
197 uint32_t tmp32; in DCDC_SetDetectionConfig() local
199 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
204 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); in DCDC_SetDetectionConfig()
207 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
[all …]
Dfsl_gpc.c96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep() local
100 tmp32 &= ~(GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK | in GPC_CM_ConfigCpuModeTransitionStep()
102 tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(config->cntMode); in GPC_CM_ConfigCpuModeTransitionStep()
105 tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(config->stepCount); in GPC_CM_ConfigCpuModeTransitionStep()
107 tmp32 &= ~GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK; in GPC_CM_ConfigCpuModeTransitionStep()
111 tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK; in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
133 uint32_t tmp32 = base->CM_SP_CTRL; in GPC_CM_RequestSleepModeSetPointTransition() local
135 …tmp32 &= ~(GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_S… in GPC_CM_RequestSleepModeSetPointTransition()
138 tmp32 |= in GPC_CM_RequestSleepModeSetPointTransition()
[all …]
Dfsl_pmu.c735 uint32_t tmp32; in PMU_WellBiasInit() local
737 tmp32 = base->PMU_BIAS_CTRL; in PMU_WellBiasInit()
738 …tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK… in PMU_WellBiasInit()
739 tmp32 |= ((uint32_t)config->wellBiasOption.wellBiasData & in PMU_WellBiasInit()
741 base->PMU_BIAS_CTRL = tmp32; in PMU_WellBiasInit()
743 tmp32 = base->PMU_BIAS_CTRL2; in PMU_WellBiasInit()
744 tmp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK; in PMU_WellBiasInit()
745 tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(config->adjustment); in PMU_WellBiasInit()
746 base->PMU_BIAS_CTRL2 = tmp32; in PMU_WellBiasInit()
824 uint32_t tmp32; in PMU_EnableBodyBias() local
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
202 uint32_t tmp32; in DCDC_SetClockSource() local
205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; in DCDC_SetClockSource()
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
202 uint32_t tmp32; in DCDC_SetClockSource() local
205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; in DCDC_SetClockSource()
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
202 uint32_t tmp32; in DCDC_SetClockSource() local
205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; in DCDC_SetClockSource()
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
202 uint32_t tmp32; in DCDC_SetClockSource() local
205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; in DCDC_SetClockSource()
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
202 uint32_t tmp32; in DCDC_SetClockSource() local
205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; in DCDC_SetClockSource()
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
202 uint32_t tmp32; in DCDC_SetClockSource() local
205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; in DCDC_SetClockSource()
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
202 uint32_t tmp32; in DCDC_SetClockSource() local
205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; in DCDC_SetClockSource()
[all …]
/hal_nxp-2.7.6/mcux/drivers/lpc/
Dfsl_adc.c52 uint32_t tmp32 = 0U; in ADC_Init() local
63 tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber); in ADC_Init()
70 tmp32 |= ADC_CTRL_ASYNMODE_MASK; in ADC_Init()
80 tmp32 |= ADC_CTRL_RESOL(config->resolution); in ADC_Init()
86 tmp32 |= ADC_CTRL_BYPASSCAL_MASK; in ADC_Init()
96 tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); in ADC_Init()
104 tmp32 |= ADC_CTRL_LPWRMODE_MASK; in ADC_Init()
108 base->CTRL = tmp32; in ADC_Init()
120 tmp32 = *(uint32_t *)FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL; in ADC_Init()
121 if (tmp32 & FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID) in ADC_Init()
[all …]
Dfsl_lpadc.c68 uint32_t tmp32 = 0U; in LPADC_Init() local
106 tmp32 |= ADC_CFG_ADCKEN_MASK; in LPADC_Init()
112 tmp32 |= ADC_CFG_VREF1RNG_MASK; in LPADC_Init()
117 tmp32 |= ADC_CFG_PWREN_MASK; in LPADC_Init()
119 tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ in LPADC_Init()
123 base->CFG = tmp32; in LPADC_Init()
230 uint32_t tmp32; in LPADC_GetConvResult() local
232 tmp32 = base->RESFIFO[index]; in LPADC_GetConvResult()
234 if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) in LPADC_GetConvResult()
239 result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; in LPADC_GetConvResult()
[all …]

12