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Searched refs:scgc5_clock_ena_bits (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-2.7.6/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/
Dfsl_xcvr_ant_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK
Dfsl_xcvr_ble_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK,
Dfsl_xcvr_zgbe_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK,
Dfsl_xcvr_gfsk_bt_0p3_h_0p5_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
Dfsl_xcvr_gfsk_bt_0p5_h_0p32_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
Dfsl_xcvr_gfsk_bt_0p5_h_0p7_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
Dfsl_xcvr_gfsk_bt_0p5_h_1p0_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
Dfsl_xcvr_gfsk_bt_0p7_h_0p5_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
Dfsl_xcvr_msk_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
Dfsl_xcvr_gfsk_bt_0p5_h_0p5_config.c51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
/hal_nxp-2.7.6/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/
Dfsl_xcvr.c534 …RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assig… in XCVR_Configure()
536 SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits; in XCVR_Configure()
Dfsl_xcvr.h701 uint32_t scgc5_clock_ena_bits; member