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Searched refs:rxBuffSizeAlign (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_enet_qos.c605 …reg |= ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(buffCfg->rxBuffSizeAlign >> ENET_QOS_RXBUFF_IGNORELSB_BI… in ENET_QOS_RxDescriptorsInit()
1454 handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign; in ENET_QOS_CreateHandler()
2030 rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()
2033 DCACHE_InvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()
2046 rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()
2049 rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()
2052 DCACHE_InvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()
2054 DCACHE_InvalidateByRange(buff2Addr, rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()
2074 if (len > rxBdRing->rxBuffSizeAlign) in ENET_QOS_ReadFrame()
2079 rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()
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Dfsl_enet.c467 assert(buffCfg->rxBuffSizeAlign * buffCfg->rxBdNumber > config->rxMaxFrameLen); in ENET_SetHandler()
470 handle->rxBuffSizeAlign[count] = buffCfg->rxBuffSizeAlign; in ENET_SetHandler()
675 base->MRBR = (uint32_t)bufferConfig->rxBuffSizeAlign; in ENET_SetMacController()
693 base->MRBR1 = (uint32_t)buffCfg->rxBuffSizeAlign; in ENET_SetMacController()
708 base->MRBR2 = (uint32_t)buffCfg->rxBuffSizeAlign; in ENET_SetMacController()
853 uint16_t rxBuffSizeAlign; in ENET_SetRxBufferDescriptors() local
863 assert(buffCfg->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); in ENET_SetRxBufferDescriptors()
884 rxBuffSizeAlign = buffCfg->rxBuffSizeAlign; in ENET_SetRxBufferDescriptors()
895 … DCACHE_InvalidateByRange((uint32_t)rxBuffer, ((uint32_t)buffCfg->rxBdNumber * rxBuffSizeAlign)); in ENET_SetRxBufferDescriptors()
905 … curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffer[count * rxBuffSizeAlign]); in ENET_SetRxBufferDescriptors()
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Dfsl_enet_qos.h529 uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ member
625 uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */ member
Dfsl_enet.h560 uint16_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ member
701 uint16_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ member
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_enet.c467 assert(buffCfg->rxBuffSizeAlign * buffCfg->rxBdNumber > config->rxMaxFrameLen); in ENET_SetHandler()
470 handle->rxBuffSizeAlign[count] = buffCfg->rxBuffSizeAlign; in ENET_SetHandler()
675 base->MRBR = (uint32_t)bufferConfig->rxBuffSizeAlign; in ENET_SetMacController()
693 base->MRBR1 = (uint32_t)buffCfg->rxBuffSizeAlign; in ENET_SetMacController()
708 base->MRBR2 = (uint32_t)buffCfg->rxBuffSizeAlign; in ENET_SetMacController()
853 uint16_t rxBuffSizeAlign; in ENET_SetRxBufferDescriptors() local
863 assert(buffCfg->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); in ENET_SetRxBufferDescriptors()
884 rxBuffSizeAlign = buffCfg->rxBuffSizeAlign; in ENET_SetRxBufferDescriptors()
895 … DCACHE_InvalidateByRange((uint32_t)rxBuffer, ((uint32_t)buffCfg->rxBdNumber * rxBuffSizeAlign)); in ENET_SetRxBufferDescriptors()
905 … curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffer[count * rxBuffSizeAlign]); in ENET_SetRxBufferDescriptors()
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Dfsl_enet.h560 uint16_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ member
701 uint16_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ member